Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs

5 files changed, 138 insertions, 7 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 0475598b77b..e891f20b373 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -75,6 +75,14 @@ enum {
 	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
 };
 
+/* CRU_CLKSEL8_CON */
+enum {
+	I2S0_FRAC_DENOM_SHIFT	= 0,
+	I2S0_FRAC_DENOM_MASK	= 0xffff << I2S0_FRAC_DENOM_SHIFT,
+	I2S0_FRAC_NUMER_SHIFT	= 16,
+	I2S0_FRAC_NUMER_MASK	= 0xffffu << I2S0_FRAC_NUMER_SHIFT,
+};
+
 /* CRU_CLKSEL12_CON */
 enum {
 	EMMC_PLL_SHIFT		= 0xe,
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
index e204dcfd1dd..1aaec5faecc 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -24,4 +24,34 @@ struct rockchip_gpio_regs {
 };
 check_member(rockchip_gpio_regs, ls_sync, 0x60);
 
+enum gpio_pu_pd {
+	GPIO_PULL_NORMAL = 0,
+	GPIO_PULL_UP,
+	GPIO_PULL_DOWN,
+	GPIO_PULL_REPEAT,
+};
+
+/* These defines are only used by spl_gpio.h */
+enum {
+	/* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */
+	GPIO_BANK_SHIFT		= 3,
+	GPIO_BANK_MASK		= 3 << GPIO_BANK_SHIFT,
+
+	GPIO_OFFSET_MASK	= 0x1f,
+};
+
+#define GPIO(bank, offset)	((bank) << GPIO_BANK_SHIFT | (offset))
+
+enum gpio_bank_t {
+	BANK_A = 0,
+	BANK_B,
+	BANK_C,
+	BANK_D,
+};
+
+enum gpio_dir_t {
+	GPIO_INPUT = 0,
+	GPIO_OUTPUT,
+};
+
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index c235607cee5..894d3a40b09 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -561,6 +561,49 @@ enum {
 	GPIO5C0_TS0_SYNC,
 };
 
+/* GRF_GPIO6A_IOMUX */
+enum {
+	GPIO6A7_SHIFT		= 0xe,
+	GPIO6A7_MASK		= 1,
+	GPIO6A7_GPIO		= 0,
+	GPIO6A7_I2S_SDO3,
+
+	GPIO6A6_SHIFT		= 0xc,
+	GPIO6A6_MASK		= 1,
+	GPIO6A6_GPIO		= 0,
+	GPIO6A6_I2S_SDO2,
+
+	GPIO6A5_SHIFT		= 0xa,
+	GPIO6A5_MASK		= 1,
+	GPIO6A5_GPIO		= 0,
+	GPIO6A5_I2S_SDO1,
+
+	GPIO6A4_SHIFT		= 8,
+	GPIO6A4_MASK		= 1,
+	GPIO6A4_GPIO		= 0,
+	GPIO6A4_I2S_SDO0,
+
+	GPIO6A3_SHIFT		= 6,
+	GPIO6A3_MASK		= 1,
+	GPIO6A3_GPIO		= 0,
+	GPIO6A3_I2S_SDI,
+
+	GPIO6A2_SHIFT		= 4,
+	GPIO6A2_MASK		= 1,
+	GPIO6A2_GPIO		= 0,
+	GPIO6A2_I2S_LRCKTX,
+
+	GPIO6A1_SHIFT		= 2,
+	GPIO6A1_MASK		= 1,
+	GPIO6A1_GPIO		= 0,
+	GPIO6A1_I2S_LRCKRX,
+
+	GPIO6A0_SHIFT		= 0,
+	GPIO6A0_MASK		= 1,
+	GPIO6A0_GPIO		= 0,
+	GPIO6A0_I2S_SCLK,
+};
+
 /* GRF_GPIO6B_IOMUX */
 enum {
 	GPIO6B3_SHIFT		= 6,
@@ -1042,6 +1085,59 @@ enum GRF_SOC_CON8 {
 	RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
 };
 
+/* GRF_IO_VSEL */
+enum {
+	GPIO1830_V18SEL_SHIFT		= 9,
+	GPIO1830_V18SEL_MASK		= 1,
+	GPIO1830_V18SEL_3_3V		= 0,
+	GPIO1830_V18SEL_1_8V,
+
+	GPIO30_V18SEL_SHIFT	= 8,
+	GPIO30_V18SEL_MASK	= 1,
+	GPIO30_V18SEL_3_3V	= 0,
+	GPIO30_V18SEL_1_8V,
+
+	SDCARD_V18SEL_SHIFT	= 7,
+	SDCARD_V18SEL_MASK	= 1,
+	SDCARD_V18SEL_3_3V	= 0,
+	SDCARD_V18SEL_1_8V,
+
+	AUDIO_V18SEL_SHIFT	= 6,
+	AUDIO_V18SEL_MASK	= 1,
+	AUDIO_V18SEL_3_3V	= 0,
+	AUDIO_V18SEL_1_8V,
+
+	BB_V18SEL_SHIFT		= 5,
+	BB_V18SEL_MASK		= 1,
+	BB_V18SEL_3_3V		= 0,
+	BB_V18SEL_1_8V,
+
+	WIFI_V18SEL_SHIFT	= 4,
+	WIFI_V18SEL_MASK	= 1,
+	WIFI_V18SEL_3_3V	= 0,
+	WIFI_V18SEL_1_8V,
+
+	FLASH1_V18SEL_SHIFT	= 3,
+	FLASH1_V18SEL_MASK	= 1,
+	FLASH1_V18SEL_3_3V	= 0,
+	FLASH1_V18SEL_1_8V,
+
+	FLASH0_V18SEL_SHIFT	= 2,
+	FLASH0_V18SEL_MASK	= 1,
+	FLASH0_V18SEL_3_3V	= 0,
+	FLASH0_V18SEL_1_8V,
+
+	DVP_V18SEL_SHIFT	= 1,
+	DVP_V18SEL_MASK		= 1,
+	DVP_V18SEL_3_3V		= 0,
+	DVP_V18SEL_1_8V,
+
+	LCDC_V18SEL_SHIFT	= 0,
+	LCDC_V18SEL_MASK	= 1,
+	LCDC_V18SEL_3_3V	= 0,
+	LCDC_V18SEL_1_8V,
+};
+
 /* GPIO Bias settings */
 enum GPIO_BIAS {
 	GPIO_BIAS_2MA = 0,
@@ -1053,13 +1149,6 @@ enum GPIO_BIAS {
 #define GPIO_BIAS_MASK	0x3
 #define GPIO_BIAS_SHIFT(x)  ((x) * 2)
 
-enum GPIO_PU_PD {
-	GPIO_PULL_NORMAL = 0,
-	GPIO_PULL_UP,
-	GPIO_PULL_DOWN,
-	GPIO_PULL_REPEAT,
-};
-
 #define GPIO_PULL_MASK	0x3
 #define GPIO_PULL_SHIFT(x)  ((x) * 2)
 
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
index 514baf6a535..2191b7d43a8 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -45,6 +45,7 @@ enum periph_id {
 	PERIPH_ID_HDMI,
 	PERIPH_ID_GMAC,
 	PERIPH_ID_SFC,
+	PERIPH_ID_I2S,
 
 	PERIPH_ID_COUNT,
 
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 925fcc888c9..928e4f258bb 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -29,4 +29,7 @@ static void configure_l2ctlr(void)
 }
 #endif /* CONFIG_ROCKCHIP_RK3288 */
 
+/* provided to defeat compiler optimisation in board_init_f() */
+void gru_dummy_function(int i);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */