arm: meson: initial u-boot SPL support for GX SoCs

Add initial boilerplate for U-Boot SPL support on Amlogic.

Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Ferass El Hafidi <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>

2 files changed, 50 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-meson/clock-gx.h b/arch/arm/include/asm/arch-meson/clock-gx.h
index 13a2e7688fc..72e4bac7aad 100644
--- a/arch/arm/include/asm/arch-meson/clock-gx.h
+++ b/arch/arm/include/asm/arch-meson/clock-gx.h
@@ -87,6 +87,7 @@
 #define HHI_VDAC_CNTL0			0x2F4 /* 0xbd offset in data sheet */
 #define HHI_VDAC_CNTL1			0x2F8 /* 0xbe offset in data sheet */
 
+#define HHI_SYS_PLL_CNTL1		0x2fc /* 0xbf offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL2		0x304 /* 0xc1 offset in data sheet */
 #define HHI_SYS_PLL_CNTL3		0x308 /* 0xc2 offset in data sheet */
@@ -114,4 +115,17 @@
 
 ulong meson_measure_clk_rate(unsigned int clk);
 
+#if defined(CONFIG_SPL_BUILD)
+#define HHI_SCC_CNTL0_FINAL_MUX_SEL	BIT(11)
+#define HHI_SCC_CNTL0_FINAL_DYN_MUX_SEL	BIT(10)
+#define HHI_SCC_CNTL0_MUX0_DIVN_TCNT	(0x3f << 4)
+#define HHI_SCC_CNTL0_MUX1_DIVN_TCNT	(0x3f << 20)
+#define HHI_SCC_CNTL0_POSTMUX0	BIT(2)
+#define HHI_SCC_CNTL0_POSTMUX1	BIT(18)
+#define HHI_SCC_CNTL0_PREMUX0	3
+#define HHI_SCC_CNTL0_PREMUX1	(3 << 16)
+#define HHI_SCC_CNTL0_DYN_ENABLE	BIT(26)
+#define HHI_SCC_CNTL0_BUSY	BIT(28)
+#endif
+
 #endif
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
index 8cfc6b00329..b4cb2a5ddbc 100644
--- a/arch/arm/include/asm/arch-meson/gx.h
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -12,7 +12,10 @@
 
 #define GX_FIRMWARE_MEM_SIZE	0x1000000
 
+#define GX_MB_SRAM_BASE		0xd9013800
 #define GX_AOBUS_BASE		0xc8100000
+#define GX_SEC_HIU_MB_BASE	0xda83c400
+#define GX_SEC_AOBUS_BASE	0xda100000
 #define GX_PERIPHS_BASE	0xc8834400
 #define GX_HIU_BASE		0xc883c000
 #define GX_ETH_BASE		0xc9410000
@@ -24,6 +27,10 @@
 #define GX_AO_SEC_GP_CFG3	GX_AO_ADDR(0x93)
 #define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
 #define GX_AO_SEC_GP_CFG5	GX_AO_ADDR(0x95)
+#define GX_AO_SEC_SD_CFG15	GX_AO_ADDR(0x8f)
+
+#define GX_SEC_AO_ADDR(off)	(GX_SEC_AOBUS_BASE + ((off) << 2))
+#define GX_SEC_AO_SEC_GP_CFG0	GX_SEC_AO_ADDR(0x90)
 
 #define GX_AO_BOOT_DEVICE	0xF
 #define GX_AO_MEM_SIZE_MASK	0xFFFF0000
@@ -41,9 +48,38 @@
 #define GX_GPIO_IN(n)		GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
 #define GX_GPIO_OUT(n)	GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
 
+/* Mailbox registers */
+#define GX_SEC_HIU_MB_ADDR(off)	(GX_SEC_HIU_MB_BASE + ((off) << 2))
+#define GX_SEC_HIU_MAILBOX_SET_0	GX_SEC_HIU_MB_ADDR(0x01)
+#define GX_SEC_HIU_MAILBOX_STAT_0	GX_SEC_HIU_MB_ADDR(0x02)
+#define GX_SEC_HIU_MAILBOX_CLR_0	GX_SEC_HIU_MB_ADDR(0x03)
+
+/* Mailbox commands */
+#define GX_MB_CMD_SHA	0xc0de0001
+#define GX_MB_CMD_DATA	0xc0dec0de
+#define GX_MB_CMD_END	0xe00de00d
+#define GX_MB_CMD_OP_SHA	0xc0de0002
+#define GX_MB_CMD_DATA_LEN	0xc0dec0d0
+
+/* PIN_MUX registers */
+#define GX_PIN_MUX_REG1		(0xda834400 + (0x2d << 2))
+#define GX_PIN_MUX_REG2		(0xda834400 + (0x2e << 2))
+#define GX_PIN_MUX_REG3		(0xda834400 + (0x2f << 2))
+#define GX_PIN_MUX_REG7		(0xda834400 + (0x33 << 2))
+
+/* PWM registers */
+#define GX_PWM_PWM_B	(0xc1100000 + (0x2155 << 2))
+#define GX_PWM_PWM_D	(0xc1100000 + (0x2195 << 2))
+#define GX_PWM_MISC_REG_CD	(0xc1100000 + (0x2196 << 2))
+#define GX_PWM_MISC_REG_AB	(0xc1100000 + (0x2156 << 2))
+
 /* Non-DM MMC init */
 #if CONFIG_IS_ENABLED(MMC) && !CONFIG_IS_ENABLED(DM_MMC)
 struct mmc *meson_mmc_init(int mmc_no);
 #endif
 
+#if !CONFIG_IS_ENABLED(WDT_MESON_GXBB) && defined(CONFIG_SPL_BUILD)
+#define GX_WDT_CTRL_REG		0xc11098d0
+#endif
+
 #endif /* __GX_H__ */