diff options
| author | Tom Rini <[email protected]> | 2023-01-10 11:19:45 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-01-20 12:27:24 -0500 |
| commit | 6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd (patch) | |
| tree | ae38e9dcf468b2e4e58293561fae87895d9b549f /arch/m68k/cpu | |
| parent | ad242344681f6a0076a6bf100aa83ac9ecbea355 (diff) | |
global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Diffstat (limited to 'arch/m68k/cpu')
| -rw-r--r-- | arch/m68k/cpu/mcf523x/interrupts.c | 8 | ||||
| -rw-r--r-- | arch/m68k/cpu/mcf52x2/interrupts.c | 14 | ||||
| -rw-r--r-- | arch/m68k/cpu/mcf530x/interrupts.c | 2 | ||||
| -rw-r--r-- | arch/m68k/cpu/mcf532x/interrupts.c | 8 | ||||
| -rw-r--r-- | arch/m68k/cpu/mcf5445x/interrupts.c | 8 |
5 files changed, 20 insertions, 20 deletions
diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c index b554c51fcbe..331288e0060 100644 --- a/arch/m68k/cpu/mcf523x/interrupts.c +++ b/arch/m68k/cpu/mcf523x/interrupts.c @@ -13,7 +13,7 @@ int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrl0, 0x1); @@ -25,10 +25,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); clrbits_be32(&intp->imrl0, INTC_IPRL_INT0); - clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); + clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c index 35ed1e7901b..e8a1e132d27 100644 --- a/arch/m68k/cpu/mcf52x2/interrupts.c +++ b/arch/m68k/cpu/mcf52x2/interrupts.c @@ -37,10 +37,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); + intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE); clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); - setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); + setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ @@ -49,7 +49,7 @@ void dtimer_intr_setup(void) defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ #if defined(CONFIG_M5208) @@ -66,11 +66,11 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); clrbits_be32(&intp->imrl0, 0x00000001); - clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); + clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ @@ -87,7 +87,7 @@ int interrupt_init(void) void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); + mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c index 2659e3478f0..11686202dc7 100644 --- a/arch/m68k/cpu/mcf530x/interrupts.c +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -24,6 +24,6 @@ void dtimer_intr_setup(void) /* clearing TIMER2 mask, so enabling the related interrupt */ out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400); /* set TIMER2 interrupt priority */ - out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI); + out_8(&icr->icr2, CFG_SYS_TMRINTR_PRI); } #endif diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index 8f2df452bae..64e04664a52 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -13,7 +13,7 @@ int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrh0, 0xffffffff); @@ -26,9 +26,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); - clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c index 5a6a88cd571..ea0cf87990c 100644 --- a/arch/m68k/cpu/mcf5445x/interrupts.c +++ b/arch/m68k/cpu/mcf5445x/interrupts.c @@ -16,7 +16,7 @@ int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrh0, 0xffffffff); @@ -29,9 +29,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); - clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK); } #endif |
