Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64

3 files changed, 90 insertions, 3 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 997e145450c..e0f6b6c4b3c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -112,9 +112,11 @@ config ARCH_OCTEON
 	select DISPLAY_CPUINFO
 	select DMA_ADDR_T_64BIT
 	select DM
-	select DM_SERIAL
-	select DM_GPIO
 	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_SERIAL
+	select DM_SPI
 	select MIPS_L2_CACHE
 	select MIPS_MACH_EARLY_INIT
 	select MIPS_TUNE_OCTEON3
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index a7bd55f8ad0..f5ad4a6213a 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -5,6 +5,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/clock/octeon-clock.h>
+
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -38,6 +40,38 @@
 			#size-cells = <1>;
 		};
 
+		clk: clock {
+			compatible = "mrvl,octeon-clk";
+			#clock-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		gpio: gpio-controller@1070000000800 {
+			#gpio-cells = <2>;
+			compatible = "cavium,octeon-7890-gpio";
+			reg = <0x10700 0x00000800 0x0 0x100>;
+			gpio-controller;
+			nr-gpios = <32>;
+			/* Interrupts are specified by two parts:
+			 * 1) GPIO pin number (0..15)
+			 * 2) Triggering (1 - edge rising
+			 *		  2 - edge falling
+			 *		  4 - level active high
+			 *		  8 - level active low)
+			 */
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			/* The GPIO pins connect to 16 consecutive CUI bits */
+			interrupts = <0x03000 4>, <0x03001 4>,
+				     <0x03002 4>, <0x03003 4>,
+				     <0x03004 4>, <0x03005 4>,
+				     <0x03006 4>, <0x03007 4>,
+				     <0x03008 4>, <0x03009 4>,
+				     <0x0300a 4>, <0x0300b 4>,
+				     <0x0300c 4>, <0x0300d 4>,
+				     <0x0300e 4>, <0x0300f 4>;
+		};
+
 		reset: reset@1180006001600 {
 			compatible = "mrvl,cn7xxx-rst";
 			reg = <0x11800 0x06001600 0x0 0x200>;
@@ -60,5 +94,37 @@
 			reg-shift = <3>;
 			interrupts = <0x08040 4>;
 		};
+
+		i2c0: i2c@1180000001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cavium,octeon-7890-twsi";
+			reg = <0x11800 0x00001000 0x0 0x200>;
+			/* INT_ST, INT_TS, INT_CORE */
+			interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
+			clock-frequency = <100000>;
+			clocks = <&clk OCTEON_CLK_IO>;
+		};
+
+		i2c1: i2c@1180000001200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cavium,octeon-7890-twsi";
+			reg = <0x11800 0x00001200 0x0 0x200>;
+			/* INT_ST, INT_TS, INT_CORE */
+			interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
+			clock-frequency = <100000>;
+			clocks = <&clk OCTEON_CLK_IO>;
+		};
+
+		spi: spi@1070000001000 {
+			compatible = "cavium,octeon-3010-spi";
+			reg = <0x10700 0x00001000 0x0 0x100>;
+			interrupts = <0x05001 1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spi-max-frequency = <25000000>;
+			clocks = <&clk OCTEON_CLK_IO>;
+		};
 	};
 };
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 4e9c2de7d40..6b2e5e84bc6 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-/include/ "mrvl,cn73xx.dtsi"
+#include "mrvl,cn73xx.dtsi"
 
 / {
 	model = "cavium,ebb7304";
@@ -13,6 +13,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		spi0 = &spi;
 	};
 
 	chosen {
@@ -94,3 +95,21 @@
 &uart0 {
 	clock-frequency = <1200000000>;
 };
+
+&i2c0 {
+	u-boot,dm-pre-reloc;	/* Needed early for DDR SPD EEPROM */
+	clock-frequency = <100000>;
+};
+
+&i2c1 {
+	u-boot,dm-pre-reloc;	/* Needed early for DDR SPD EEPROM */
+	clock-frequency = <100000>;
+};
+
+&spi {
+	flash@0 {
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		spi-max-frequency = <2000000>;
+		reg = <0>;
+	};
+};