diff options
| author | Yao Zi <[email protected]> | 2025-05-13 09:04:54 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2025-05-21 16:49:52 +0800 |
| commit | 3dbff9eecc869bc28ce010cf97d2cfee25c44f3a (patch) | |
| tree | 9439bba2cf554b27e6a6a50f974f6f7fdda105f4 /arch/riscv/Kconfig | |
| parent | bbf5f79bba07703c85ab9e3f4101758afb402c09 (diff) | |
riscv: lib: Split out support for T-Head cache management operations
Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.
This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.
Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b24623590f2..dc36d9b8566 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -77,6 +77,14 @@ config SYS_DCACHE_OFF help Do not enable data cache in U-Boot. +config SYS_CACHE_THEAD_CMO + bool "THEAD non-standard cache operations" + depends on !SYS_DCACHE_OFF + default n + help + Support for non-standard cache management operations on SoCs based on + T-Head C906/C910 cores. + config SPL_SYS_DCACHE_OFF bool "Do not enable dcache in SPL" depends on SPL |