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authorKautuk Consul <[email protected]>2022-12-07 17:12:35 +0530
committerLeo Yu-Chi Liang <[email protected]>2022-12-08 15:15:58 +0800
commitae3527f088062dc4e117b0c4d4319e068f5e44cd (patch)
treefa08dd5ee80ff563cb71240bafd1ad0b23ff22cd /arch/riscv/include
parent1c03ab9f4bdf19d1ac7afc157788bd0102ccd969 (diff)
arch/riscv: add semihosting support for RISC-V
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <[email protected]> Signed-off-by: Kautuk Consul <[email protected]> Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Diffstat (limited to 'arch/riscv/include')
-rw-r--r--arch/riscv/include/asm/spl.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
index e8a94fcb1fe..2898a770ee2 100644
--- a/arch/riscv/include/asm/spl.h
+++ b/arch/riscv/include/asm/spl.h
@@ -25,6 +25,7 @@ enum {
BOOT_DEVICE_DFU,
BOOT_DEVICE_XIP,
BOOT_DEVICE_BOOTROM,
+ BOOT_DEVICE_SMH,
BOOT_DEVICE_NONE
};