Merge tag 'v2024.10-rc5' into next

Prepare v2024.10-rc5

3 files changed, 57 insertions, 4 deletions

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6b854cc0b65..fa371027d45 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -138,6 +138,7 @@ config FRAMEPOINTER
 
 config SPL_FRAMEPOINTER
 	bool "Build SPL with frame pointer for stack unwinding"
+	depends on SPL
 	help
 	  Choose this option to use the frame pointer so the stack can be
 	  unwound if needed. This is useful for tracing where faults came
@@ -445,7 +446,20 @@ config AVAILABLE_HARTS
 	  If disable this, it will send IPI by CPUs node numbers of device tree.
 
 config SHOW_REGS
+	default y
 	bool "Show registers on unhandled exception"
+	help
+	  By default only the program counter and the return address register
+	  are shown in crash dumps. Enable this symbol to show all registers in
+	  main U-Boot.
+
+config SPL_SHOW_REGS
+	bool "In SPL show registers on unhandled exception"
+	depends on SPL
+	help
+	  By default only the program counter and the return address register
+	  are shown in crash dumps. Enable this symbol to show all registers in
+	  SPL.
 
 config RISCV_PRIV_1_9
 	bool "Use version 1.9 of the RISC-V priviledged specification"
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 35f1368b837..2f2994c4ddc 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -138,6 +138,43 @@ static inline unsigned long ffz(unsigned long word)
 	return k;
 }
 
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG);
+	unsigned long result = offset & ~(BITS_PER_LONG - 1);
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= (BITS_PER_LONG - 1);
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (BITS_PER_LONG - offset);
+		if (size < BITS_PER_LONG)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= BITS_PER_LONG;
+		result += BITS_PER_LONG;
+	}
+	while (size & ~(BITS_PER_LONG - 1)) {
+		tmp = *(p++);
+		if (~tmp)
+			goto found_middle;
+		result += BITS_PER_LONG;
+		size -= BITS_PER_LONG;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
 /*
  * ffs: find first bit set. This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
@@ -158,6 +195,9 @@ static inline unsigned long ffz(unsigned long word)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
 
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
 #define test_and_set_bit		__test_and_set_bit
 #define test_and_clear_bit		__test_and_clear_bit
 
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index f9a1428a486..714cc92d03e 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -34,9 +34,8 @@ static void show_efi_loaded_images(uintptr_t epc)
 	efi_print_image_infos((void *)epc);
 }
 
-static void show_regs(struct pt_regs *regs)
+static void __maybe_unused show_regs(struct pt_regs *regs)
 {
-#ifdef CONFIG_SHOW_REGS
 	printf("\nSP:  " REG_FMT " GP:  " REG_FMT " TP:  " REG_FMT "\n",
 	       regs->sp, regs->gp, regs->tp);
 	printf("T0:  " REG_FMT " T1:  " REG_FMT " T2:  " REG_FMT "\n",
@@ -57,7 +56,6 @@ static void show_regs(struct pt_regs *regs)
 	       regs->s10, regs->s11, regs->t3);
 	printf("T4:  " REG_FMT " T5:  " REG_FMT " T6:  " REG_FMT "\n",
 	       regs->t4, regs->t5, regs->t6);
-#endif
 }
 
 static void __maybe_unused show_backtrace(struct pt_regs *regs)
@@ -157,7 +155,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
 		printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
 		       epc - gd->reloc_off, regs->ra - gd->reloc_off);
 
-	show_regs(regs);
+	if (CONFIG_IS_ENABLED(SHOW_REGS))
+		show_regs(regs);
 	if (CONFIG_IS_ENABLED(FRAMEPOINTER))
 		show_backtrace(regs);
 	show_code(epc);