diff options
| author | Simon Glass <[email protected]> | 2024-08-27 19:44:25 -0600 |
|---|---|---|
| committer | Simon Glass <[email protected]> | 2024-10-18 14:10:21 -0600 |
| commit | 3b2e4f542e3ea5d116d5830f4eef9be97d872312 (patch) | |
| tree | 67c7f6ee2d38f7ecfe80ddf6cff9c89a151c4135 /arch/x86/cpu | |
| parent | 6ab545ba21668132d9dad27026c91d298b6e5a77 (diff) | |
x86: Ensure the CPU identity exists for timer init
When bootstage is used the timer can be inited before the CPU identity
is set up, resulting in the checks for the vendor not working.
Add a special call to work around this.
Signed-off-by: Simon Glass <[email protected]>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/i386/cpu.c | 5 | ||||
| -rw-r--r-- | arch/x86/cpu/x86_64/cpu.c | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 532f690c874..a51a24498a7 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -501,6 +501,11 @@ int x86_cpu_reinit_f(void) return 0; } +void x86_get_identity_for_timer(void) +{ + setup_identity(); +} + void x86_enable_caches(void) { unsigned long cr0; diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 80eab710315..71bc07f872a 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -75,3 +75,9 @@ void board_debug_uart_init(void) /* this was already done in SPL */ } #endif + +void x86_get_identity_for_timer(void) +{ + /* set the vendor to Intel so that native_calibrate_tsc() works */ + gd->arch.x86_vendor = X86_VENDOR_INTEL; +} |
