Merge tag 'u-boot-rockchip-20240812' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

Please pull the updates for rockchip platform:
- Add board support:
        RK3566: Radxa ROCK 3 Model C
                Radxa ZERO 3W/3E
                Xunlong Orange Pi 3B
        RK3568J: Radxa ROCK 3B
        RK3308B: Radxa ROCK S0
        RK3588: Radxa ROCK 5 ITX
                FriendlyElec CM3588 NAS board
- dw-mmc: allow 4-bit mode;
- dts and config updates;

CI:
https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/21997

31 files changed, 229 insertions, 4542 deletions

diff --git a/arch/arm/dts/px30-firefly.dts b/arch/arm/dts/px30-firefly.dts
index c0a8e3009ad..e678d6a0b28 100644
--- a/arch/arm/dts/px30-firefly.dts
+++ b/arch/arm/dts/px30-firefly.dts
@@ -13,6 +13,10 @@
 	model = "Firefly Core-PX30-JD4";
 	compatible = "rockchip,px30-firefly", "rockchip,px30";
 
+	aliases {
+		ethernet0 = &gmac;
+	};
+
 	chosen {
 		stdout-path = "serial2:115200n8";
 	};
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 59fa9f43a97..abc6b49e666 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -99,16 +99,20 @@
 
 &gpio0 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 0 32>;
 };
 
 &gpio1 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 32 32>;
 };
 
 &gpio2 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 64 32>;
 };
 
 &gpio3 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 96 32>;
 };
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
deleted file mode 100644
index 3152bf107db..00000000000
--- a/arch/arm/dts/px30.dtsi
+++ /dev/null
@@ -1,2415 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/clock/px30-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/px30-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	compatible = "rockchip,px30";
-
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		ethernet0 = &gmac;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		serial5 = &uart5;
-		spi0 = &spi0;
-		spi1 = &spi1;
-	};
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-			#cooling-cells = <2>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			dynamic-power-coefficient = <90>;
-			operating-points-v2 = <&cpu0_opp_table>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x1>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-			#cooling-cells = <2>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			dynamic-power-coefficient = <90>;
-			operating-points-v2 = <&cpu0_opp_table>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x2>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-			#cooling-cells = <2>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			dynamic-power-coefficient = <90>;
-			operating-points-v2 = <&cpu0_opp_table>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x3>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-			#cooling-cells = <2>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			dynamic-power-coefficient = <90>;
-			operating-points-v2 = <&cpu0_opp_table>;
-		};
-
-		idle-states {
-			entry-method = "psci";
-
-			CPU_SLEEP: cpu-sleep {
-				compatible = "arm,idle-state";
-				local-timer-stop;
-				arm,psci-suspend-param = <0x0010000>;
-				entry-latency-us = <120>;
-				exit-latency-us = <250>;
-				min-residency-us = <900>;
-			};
-
-			CLUSTER_SLEEP: cluster-sleep {
-				compatible = "arm,idle-state";
-				local-timer-stop;
-				arm,psci-suspend-param = <0x1010000>;
-				entry-latency-us = <400>;
-				exit-latency-us = <500>;
-				min-residency-us = <2000>;
-			};
-		};
-	};
-
-	cpu0_opp_table: opp-table-0 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-600000000 {
-			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <950000 950000 1350000>;
-			clock-latency-ns = <40000>;
-			opp-suspend;
-		};
-		opp-816000000 {
-			opp-hz = /bits/ 64 <816000000>;
-			opp-microvolt = <1050000 1050000 1350000>;
-			clock-latency-ns = <40000>;
-		};
-		opp-1008000000 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <1175000 1175000 1350000>;
-			clock-latency-ns = <40000>;
-		};
-		opp-1200000000 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <1300000 1300000 1350000>;
-			clock-latency-ns = <40000>;
-		};
-		opp-1296000000 {
-			opp-hz = /bits/ 64 <1296000000>;
-			opp-microvolt = <1350000 1350000 1350000>;
-			clock-latency-ns = <40000>;
-		};
-	};
-
-	arm-pmu {
-		compatible = "arm,cortex-a35-pmu";
-		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
-	};
-
-	display_subsystem: display-subsystem {
-		compatible = "rockchip,display-subsystem";
-		ports = <&vopb_out>, <&vopl_out>;
-		status = "disabled";
-	};
-
-	gmac_clkin: external-gmac-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <50000000>;
-		clock-output-names = "gmac_clkin";
-		#clock-cells = <0>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	thermal_zones: thermal-zones {
-		soc_thermal: soc-thermal {
-			polling-delay-passive = <20>;
-			polling-delay = <1000>;
-			sustainable-power = <750>;
-			thermal-sensors = <&tsadc 0>;
-
-			trips {
-				threshold: trip-point-0 {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-
-				target: trip-point-1 {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-
-				soc_crit: soc-crit {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-
-			cooling-maps {
-				map0 {
-					trip = <&target>;
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-					contribution = <4096>;
-				};
-
-				map1 {
-					trip = <&target>;
-					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-					contribution = <4096>;
-				};
-			};
-		};
-
-		gpu_thermal: gpu-thermal {
-			polling-delay-passive = <100>; /* milliseconds */
-			polling-delay = <1000>; /* milliseconds */
-			thermal-sensors = <&tsadc 1>;
-		};
-	};
-
-	xin24m: xin24m {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "xin24m";
-	};
-
-	pmu: power-management@ff000000 {
-		compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
-		reg = <0x0 0xff000000 0x0 0x1000>;
-
-		power: power-controller {
-			compatible = "rockchip,px30-power-controller";
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* These power domains are grouped by VD_LOGIC */
-			power-domain@PX30_PD_USB {
-				reg = <PX30_PD_USB>;
-				clocks = <&cru HCLK_HOST>,
-					 <&cru HCLK_OTG>,
-					 <&cru SCLK_OTG_ADP>;
-				pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_SDCARD {
-				reg = <PX30_PD_SDCARD>;
-				clocks = <&cru HCLK_SDMMC>,
-					 <&cru SCLK_SDMMC>;
-				pm_qos = <&qos_sdmmc>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_GMAC {
-				reg = <PX30_PD_GMAC>;
-				clocks = <&cru ACLK_GMAC>,
-					 <&cru PCLK_GMAC>,
-					 <&cru SCLK_MAC_REF>,
-					 <&cru SCLK_GMAC_RX_TX>;
-				pm_qos = <&qos_gmac>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_MMC_NAND {
-				reg = <PX30_PD_MMC_NAND>;
-				clocks =  <&cru HCLK_NANDC>,
-					  <&cru HCLK_EMMC>,
-					  <&cru HCLK_SDIO>,
-					  <&cru HCLK_SFC>,
-					  <&cru SCLK_EMMC>,
-					  <&cru SCLK_NANDC>,
-					  <&cru SCLK_SDIO>,
-					  <&cru SCLK_SFC>;
-				pm_qos = <&qos_emmc>, <&qos_nand>,
-					 <&qos_sdio>, <&qos_sfc>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_VPU {
-				reg = <PX30_PD_VPU>;
-				clocks = <&cru ACLK_VPU>,
-					 <&cru HCLK_VPU>,
-					 <&cru SCLK_CORE_VPU>;
-				pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_VO {
-				reg = <PX30_PD_VO>;
-				clocks = <&cru ACLK_RGA>,
-					 <&cru ACLK_VOPB>,
-					 <&cru ACLK_VOPL>,
-					 <&cru DCLK_VOPB>,
-					 <&cru DCLK_VOPL>,
-					 <&cru HCLK_RGA>,
-					 <&cru HCLK_VOPB>,
-					 <&cru HCLK_VOPL>,
-					 <&cru PCLK_MIPI_DSI>,
-					 <&cru SCLK_RGA_CORE>,
-					 <&cru SCLK_VOPB_PWM>;
-				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
-					 <&qos_vop_m0>, <&qos_vop_m1>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_VI {
-				reg = <PX30_PD_VI>;
-				clocks = <&cru ACLK_CIF>,
-					 <&cru ACLK_ISP>,
-					 <&cru HCLK_CIF>,
-					 <&cru HCLK_ISP>,
-					 <&cru SCLK_ISP>;
-				pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
-					 <&qos_isp_wr>, <&qos_isp_m1>,
-					 <&qos_vip>;
-				#power-domain-cells = <0>;
-			};
-			power-domain@PX30_PD_GPU {
-				reg = <PX30_PD_GPU>;
-				clocks = <&cru SCLK_GPU>;
-				pm_qos = <&qos_gpu>;
-				#power-domain-cells = <0>;
-			};
-		};
-	};
-
-	pmugrf: syscon@ff010000 {
-		compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
-		reg = <0x0 0xff010000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		pmu_io_domains: io-domains {
-			compatible = "rockchip,px30-pmu-io-voltage-domain";
-			status = "disabled";
-		};
-
-		reboot-mode {
-			compatible = "syscon-reboot-mode";
-			offset = <0x200>;
-			mode-bootloader = <BOOT_BL_DOWNLOAD>;
-			mode-fastboot = <BOOT_FASTBOOT>;
-			mode-loader = <BOOT_BL_DOWNLOAD>;
-			mode-normal = <BOOT_NORMAL>;
-			mode-recovery = <BOOT_RECOVERY>;
-		};
-	};
-
-	uart0: serial@ff030000 {
-		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
-		reg = <0x0 0xff030000 0x0 0x100>;
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 0>, <&dmac 1>;
-		dma-names = "tx", "rx";
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
-		status = "disabled";
-	};
-
-	i2s0_8ch: i2s@ff060000 {
-		compatible = "rockchip,px30-i2s-tdm";
-		reg = <0x0 0xff060000 0x0 0x1000>;
-		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
-		clock-names = "mclk_tx", "mclk_rx", "hclk";
-		dmas = <&dmac 16>, <&dmac 17>;
-		dma-names = "tx", "rx";
-		rockchip,grf = <&grf>;
-		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
-		reset-names = "tx-m", "rx-m";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
-			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
-			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
-			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
-			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
-			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
-		#sound-dai-cells = <0>;
-		status = "disabled";
-	};
-
-	i2s1_2ch: i2s@ff070000 {
-		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
-		reg = <0x0 0xff070000 0x0 0x1000>;
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
-		clock-names = "i2s_clk", "i2s_hclk";
-		dmas = <&dmac 18>, <&dmac 19>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
-			     &i2s1_2ch_sdi &i2s1_2ch_sdo>;
-		#sound-dai-cells = <0>;
-		status = "disabled";
-	};
-
-	i2s2_2ch: i2s@ff080000 {
-		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
-		reg = <0x0 0xff080000 0x0 0x1000>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
-		clock-names = "i2s_clk", "i2s_hclk";
-		dmas = <&dmac 20>, <&dmac 21>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
-			     &i2s2_2ch_sdi &i2s2_2ch_sdo>;
-		#sound-dai-cells = <0>;
-		status = "disabled";
-	};
-
-	gic: interrupt-controller@ff131000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-		interrupt-controller;
-		reg = <0x0 0xff131000 0 0x1000>,
-		      <0x0 0xff132000 0 0x2000>,
-		      <0x0 0xff134000 0 0x2000>,
-		      <0x0 0xff136000 0 0x2000>;
-		interrupts = <GIC_PPI 9
-		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	grf: syscon@ff140000 {
-		compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
-		reg = <0x0 0xff140000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		io_domains: io-domains {
-			compatible = "rockchip,px30-io-voltage-domain";
-			status = "disabled";
-		};
-
-		lvds: lvds {
-			compatible = "rockchip,px30-lvds";
-			phys = <&dsi_dphy>;
-			phy-names = "dphy";
-			rockchip,grf = <&grf>;
-			rockchip,output = "lvds";
-			status = "disabled";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					lvds_vopb_in: endpoint@0 {
-						reg = <0>;
-						remote-endpoint = <&vopb_out_lvds>;
-					};
-
-					lvds_vopl_in: endpoint@1 {
-						reg = <1>;
-						remote-endpoint = <&vopl_out_lvds>;
-					};
-				};
-			};
-		};
-	};
-
-	uart1: serial@ff158000 {
-		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
-		reg = <0x0 0xff158000 0x0 0x100>;
-		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 2>, <&dmac 3>;
-		dma-names = "tx", "rx";
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
-		status = "disabled";
-	};
-
-	uart2: serial@ff160000 {
-		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
-		reg = <0x0 0xff160000 0x0 0x100>;
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 4>, <&dmac 5>;
-		dma-names = "tx", "rx";
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2m0_xfer>;
-		status = "disabled";
-	};
-
-	uart3: serial@ff168000 {
-		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
-		reg = <0x0 0xff168000 0x0 0x100>;
-		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 6>, <&dmac 7>;
-		dma-names = "tx", "rx";
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
-		status = "disabled";
-	};
-
-	uart4: serial@ff170000 {
-		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
-		reg = <0x0 0xff170000 0x0 0x100>;
-		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 8>, <&dmac 9>;
-		dma-names = "tx", "rx";
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
-		status = "disabled";
-	};
-
-	uart5: serial@ff178000 {
-		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
-		reg = <0x0 0xff178000 0x0 0x100>;
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 10>, <&dmac 11>;
-		dma-names = "tx", "rx";
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
-		status = "disabled";
-	};
-
-	i2c0: i2c@ff180000 {
-		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
-		reg = <0x0 0xff180000 0x0 0x1000>;
-		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
-		clock-names = "i2c", "pclk";
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c0_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c1: i2c@ff190000 {
-		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
-		reg = <0x0 0xff190000 0x0 0x1000>;
-		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
-		clock-names = "i2c", "pclk";
-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c1_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c2: i2c@ff1a0000 {
-		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
-		reg = <0x0 0xff1a0000 0x0 0x1000>;
-		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
-		clock-names = "i2c", "pclk";
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c2_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c3: i2c@ff1b0000 {
-		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
-		reg = <0x0 0xff1b0000 0x0 0x1000>;
-		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
-		clock-names = "i2c", "pclk";
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c3_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	spi0: spi@ff1d0000 {
-		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
-		reg = <0x0 0xff1d0000 0x0 0x1000>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
-		clock-names = "spiclk", "apb_pclk";
-		dmas = <&dmac 12>, <&dmac 13>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	spi1: spi@ff1d8000 {
-		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
-		reg = <0x0 0xff1d8000 0x0 0x1000>;
-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
-		clock-names = "spiclk", "apb_pclk";
-		dmas = <&dmac 14>, <&dmac 15>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	wdt: watchdog@ff1e0000 {
-		compatible = "rockchip,px30-wdt", "snps,dw-wdt";
-		reg = <0x0 0xff1e0000 0x0 0x100>;
-		clocks = <&cru PCLK_WDT_NS>;
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		status = "disabled";
-	};
-
-	pwm0: pwm@ff200000 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff200000 0x0 0x10>;
-		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm0_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm1: pwm@ff200010 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff200010 0x0 0x10>;
-		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm1_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm2: pwm@ff200020 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff200020 0x0 0x10>;
-		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm2_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm3: pwm@ff200030 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff200030 0x0 0x10>;
-		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm3_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm4: pwm@ff208000 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff208000 0x0 0x10>;
-		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm4_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm5: pwm@ff208010 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff208010 0x0 0x10>;
-		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm5_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm6: pwm@ff208020 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff208020 0x0 0x10>;
-		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm6_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pwm7: pwm@ff208030 {
-		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
-		reg = <0x0 0xff208030 0x0 0x10>;
-		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
-		clock-names = "pwm", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm7_pin>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	rktimer: timer@ff210000 {
-		compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
-		reg = <0x0 0xff210000 0x0 0x1000>;
-		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
-		clock-names = "pclk", "timer";
-	};
-
-	dmac: dma-controller@ff240000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0x0 0xff240000 0x0 0x4000>;
-		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		arm,pl330-periph-burst;
-		clocks = <&cru ACLK_DMAC>;
-		clock-names = "apb_pclk";
-		#dma-cells = <1>;
-	};
-
-	tsadc: tsadc@ff280000 {
-		compatible = "rockchip,px30-tsadc";
-		reg = <0x0 0xff280000 0x0 0x100>;
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		assigned-clocks = <&cru SCLK_TSADC>;
-		assigned-clock-rates = <50000>;
-		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
-		clock-names = "tsadc", "apb_pclk";
-		resets = <&cru SRST_TSADC>;
-		reset-names = "tsadc-apb";
-		rockchip,grf = <&grf>;
-		rockchip,hw-tshut-temp = <120000>;
-		pinctrl-names = "init", "default", "sleep";
-		pinctrl-0 = <&tsadc_otp_pin>;
-		pinctrl-1 = <&tsadc_otp_out>;
-		pinctrl-2 = <&tsadc_otp_pin>;
-		#thermal-sensor-cells = <1>;
-		status = "disabled";
-	};
-
-	saradc: saradc@ff288000 {
-		compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
-		reg = <0x0 0xff288000 0x0 0x100>;
-		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-		#io-channel-cells = <1>;
-		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
-		clock-names = "saradc", "apb_pclk";
-		resets = <&cru SRST_SARADC_P>;
-		reset-names = "saradc-apb";
-		status = "disabled";
-	};
-
-	otp: nvmem@ff290000 {
-		compatible = "rockchip,px30-otp";
-		reg = <0x0 0xff290000 0x0 0x4000>;
-		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
-			 <&cru PCLK_OTP_PHY>;
-		clock-names = "otp", "apb_pclk", "phy";
-		resets = <&cru SRST_OTP_PHY>;
-		reset-names = "phy";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* Data cells */
-		cpu_id: id@7 {
-			reg = <0x07 0x10>;
-		};
-		cpu_leakage: cpu-leakage@17 {
-			reg = <0x17 0x1>;
-		};
-		performance: performance@1e {
-			reg = <0x1e 0x1>;
-			bits = <4 3>;
-		};
-	};
-
-	cru: clock-controller@ff2b0000 {
-		compatible = "rockchip,px30-cru";
-		reg = <0x0 0xff2b0000 0x0 0x1000>;
-		clocks = <&xin24m>, <&pmucru PLL_GPLL>;
-		clock-names = "xin24m", "gpll";
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-
-		assigned-clocks = <&cru PLL_NPLL>,
-			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
-			<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
-			<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
-
-		assigned-clock-rates = <1188000000>,
-			<200000000>, <200000000>,
-			<150000000>, <150000000>,
-			<100000000>, <200000000>;
-	};
-
-	pmucru: clock-controller@ff2bc000 {
-		compatible = "rockchip,px30-pmucru";
-		reg = <0x0 0xff2bc000 0x0 0x1000>;
-		clocks = <&xin24m>;
-		clock-names = "xin24m";
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-
-		assigned-clocks =
-			<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
-			<&pmucru SCLK_WIFI_PMU>;
-		assigned-clock-rates =
-			<1200000000>, <100000000>,
-			<26000000>;
-	};
-
-	usb2phy_grf: syscon@ff2c0000 {
-		compatible = "rockchip,px30-usb2phy-grf", "syscon",
-			     "simple-mfd";
-		reg = <0x0 0xff2c0000 0x0 0x10000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		u2phy: usb2phy@100 {
-			compatible = "rockchip,px30-usb2phy";
-			reg = <0x100 0x20>;
-			clocks = <&pmucru SCLK_USBPHY_REF>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-			assigned-clocks = <&cru USB480M>;
-			assigned-clock-parents = <&u2phy>;
-			clock-output-names = "usb480m_phy";
-			status = "disabled";
-
-			u2phy_host: host-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "linestate";
-				status = "disabled";
-			};
-
-			u2phy_otg: otg-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "otg-bvalid", "otg-id",
-						  "linestate";
-				status = "disabled";
-			};
-		};
-	};
-
-	dsi_dphy: phy@ff2e0000 {
-		compatible = "rockchip,px30-dsi-dphy";
-		reg = <0x0 0xff2e0000 0x0 0x10000>;
-		clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
-		clock-names = "ref", "pclk";
-		resets = <&cru SRST_MIPIDSIPHY_P>;
-		reset-names = "apb";
-		#phy-cells = <0>;
-		power-domains = <&power PX30_PD_VO>;
-		status = "disabled";
-	};
-
-	csi_dphy: phy@ff2f0000 {
-		compatible = "rockchip,px30-csi-dphy";
-		reg = <0x0 0xff2f0000 0x0 0x4000>;
-		clocks = <&cru PCLK_MIPICSIPHY>;
-		clock-names = "pclk";
-		#phy-cells = <0>;
-		power-domains = <&power PX30_PD_VI>;
-		resets = <&cru SRST_MIPICSIPHY_P>;
-		reset-names = "apb";
-		rockchip,grf = <&grf>;
-		status = "disabled";
-	};
-
-	usb20_otg: usb@ff300000 {
-		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
-			     "snps,dwc2";
-		reg = <0x0 0xff300000 0x0 0x40000>;
-		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_OTG>;
-		clock-names = "otg";
-		dr_mode = "otg";
-		g-np-tx-fifo-size = <16>;
-		g-rx-fifo-size = <280>;
-		g-tx-fifo-size = <256 128 128 64 32 16>;
-		phys = <&u2phy_otg>;
-		phy-names = "usb2-phy";
-		power-domains = <&power PX30_PD_USB>;
-		status = "disabled";
-	};
-
-	usb_host0_ehci: usb@ff340000 {
-		compatible = "generic-ehci";
-		reg = <0x0 0xff340000 0x0 0x10000>;
-		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_HOST>;
-		phys = <&u2phy_host>;
-		phy-names = "usb";
-		power-domains = <&power PX30_PD_USB>;
-		status = "disabled";
-	};
-
-	usb_host0_ohci: usb@ff350000 {
-		compatible = "generic-ohci";
-		reg = <0x0 0xff350000 0x0 0x10000>;
-		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_HOST>;
-		phys = <&u2phy_host>;
-		phy-names = "usb";
-		power-domains = <&power PX30_PD_USB>;
-		status = "disabled";
-	};
-
-	gmac: ethernet@ff360000 {
-		compatible = "rockchip,px30-gmac";
-		reg = <0x0 0xff360000 0x0 0x10000>;
-		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "macirq";
-		clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
-			 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
-			 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
-			 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
-		clock-names = "stmmaceth", "mac_clk_rx",
-			      "mac_clk_tx", "clk_mac_ref",
-			      "clk_mac_refout", "aclk_mac",
-			      "pclk_mac", "clk_mac_speed";
-		rockchip,grf = <&grf>;
-		phy-mode = "rmii";
-		pinctrl-names = "default";
-		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
-		power-domains = <&power PX30_PD_GMAC>;
-		resets = <&cru SRST_GMAC_A>;
-		reset-names = "stmmaceth";
-		status = "disabled";
-	};
-
-	sdmmc: mmc@ff370000 {
-		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x0 0xff370000 0x0 0x4000>;
-		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
-			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		bus-width = <4>;
-		fifo-depth = <0x100>;
-		max-frequency = <150000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
-		power-domains = <&power PX30_PD_SDCARD>;
-		status = "disabled";
-	};
-
-	sdio: mmc@ff380000 {
-		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x0 0xff380000 0x0 0x4000>;
-		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
-			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		bus-width = <4>;
-		fifo-depth = <0x100>;
-		max-frequency = <150000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
-		power-domains = <&power PX30_PD_MMC_NAND>;
-		status = "disabled";
-	};
-
-	emmc: mmc@ff390000 {
-		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x0 0xff390000 0x0 0x4000>;
-		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
-			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		bus-width = <8>;
-		fifo-depth = <0x100>;
-		max-frequency = <150000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-		power-domains = <&power PX30_PD_MMC_NAND>;
-		status = "disabled";
-	};
-
-	sfc: spi@ff3a0000 {
-		compatible = "rockchip,sfc";
-		reg = <0x0 0xff3a0000 0x0 0x4000>;
-		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-		clock-names = "clk_sfc", "hclk_sfc";
-		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
-		pinctrl-names = "default";
-		power-domains = <&power PX30_PD_MMC_NAND>;
-		status = "disabled";
-	};
-
-	nfc: nand-controller@ff3b0000 {
-		compatible = "rockchip,px30-nfc";
-		reg = <0x0 0xff3b0000 0x0 0x4000>;
-		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
-		clock-names = "ahb", "nfc";
-		assigned-clocks = <&cru SCLK_NANDC>;
-		assigned-clock-rates = <150000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
-			     &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
-		power-domains = <&power PX30_PD_MMC_NAND>;
-		status = "disabled";
-	};
-
-	gpu_opp_table: opp-table-1 {
-		compatible = "operating-points-v2";
-
-		opp-200000000 {
-			opp-hz = /bits/ 64 <200000000>;
-			opp-microvolt = <950000>;
-		};
-		opp-300000000 {
-			opp-hz = /bits/ 64 <300000000>;
-			opp-microvolt = <975000>;
-		};
-		opp-400000000 {
-			opp-hz = /bits/ 64 <400000000>;
-			opp-microvolt = <1050000>;
-		};
-		opp-480000000 {
-			opp-hz = /bits/ 64 <480000000>;
-			opp-microvolt = <1125000>;
-		};
-	};
-
-	gpu: gpu@ff400000 {
-		compatible = "rockchip,px30-mali", "arm,mali-bifrost";
-		reg = <0x0 0xff400000 0x0 0x4000>;
-		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "job", "mmu", "gpu";
-		clocks = <&cru SCLK_GPU>;
-		#cooling-cells = <2>;
-		power-domains = <&power PX30_PD_GPU>;
-		operating-points-v2 = <&gpu_opp_table>;
-		status = "disabled";
-	};
-
-	vpu: video-codec@ff442000 {
-		compatible = "rockchip,px30-vpu";
-		reg = <0x0 0xff442000 0x0 0x800>;
-		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "vepu", "vdpu";
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-		clock-names = "aclk", "hclk";
-		iommus = <&vpu_mmu>;
-		power-domains = <&power PX30_PD_VPU>;
-	};
-
-	vpu_mmu: iommu@ff442800 {
-		compatible = "rockchip,iommu";
-		reg = <0x0 0xff442800 0x0 0x100>;
-		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-		clock-names = "aclk", "iface";
-		#iommu-cells = <0>;
-		power-domains = <&power PX30_PD_VPU>;
-	};
-
-	dsi: dsi@ff450000 {
-		compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
-		reg = <0x0 0xff450000 0x0 0x10000>;
-		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_MIPI_DSI>;
-		clock-names = "pclk";
-		phys = <&dsi_dphy>;
-		phy-names = "dphy";
-		power-domains = <&power PX30_PD_VO>;
-		resets = <&cru SRST_MIPIDSI_HOST_P>;
-		reset-names = "apb";
-		rockchip,grf = <&grf>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				dsi_in_vopb: endpoint@0 {
-					reg = <0>;
-					remote-endpoint = <&vopb_out_dsi>;
-				};
-
-				dsi_in_vopl: endpoint@1 {
-					reg = <1>;
-					remote-endpoint = <&vopl_out_dsi>;
-				};
-			};
-		};
-	};
-
-	vopb: vop@ff460000 {
-		compatible = "rockchip,px30-vop-big";
-		reg = <0x0 0xff460000 0x0 0xefc>;
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
-			 <&cru HCLK_VOPB>;
-		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
-		resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
-		reset-names = "axi", "ahb", "dclk";
-		iommus = <&vopb_mmu>;
-		power-domains = <&power PX30_PD_VO>;
-		status = "disabled";
-
-		vopb_out: port {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			vopb_out_dsi: endpoint@0 {
-				reg = <0>;
-				remote-endpoint = <&dsi_in_vopb>;
-			};
-
-			vopb_out_lvds: endpoint@1 {
-				reg = <1>;
-				remote-endpoint = <&lvds_vopb_in>;
-			};
-		};
-	};
-
-	vopb_mmu: iommu@ff460f00 {
-		compatible = "rockchip,iommu";
-		reg = <0x0 0xff460f00 0x0 0x100>;
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
-		clock-names = "aclk", "iface";
-		power-domains = <&power PX30_PD_VO>;
-		#iommu-cells = <0>;
-		status = "disabled";
-	};
-
-	vopl: vop@ff470000 {
-		compatible = "rockchip,px30-vop-lit";
-		reg = <0x0 0xff470000 0x0 0xefc>;
-		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
-			 <&cru HCLK_VOPL>;
-		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
-		resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
-		reset-names = "axi", "ahb", "dclk";
-		iommus = <&vopl_mmu>;
-		power-domains = <&power PX30_PD_VO>;
-		status = "disabled";
-
-		vopl_out: port {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			vopl_out_dsi: endpoint@0 {
-				reg = <0>;
-				remote-endpoint = <&dsi_in_vopl>;
-			};
-
-			vopl_out_lvds: endpoint@1 {
-				reg = <1>;
-				remote-endpoint = <&lvds_vopl_in>;
-			};
-		};
-	};
-
-	vopl_mmu: iommu@ff470f00 {
-		compatible = "rockchip,iommu";
-		reg = <0x0 0xff470f00 0x0 0x100>;
-		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
-		clock-names = "aclk", "iface";
-		power-domains = <&power PX30_PD_VO>;
-		#iommu-cells = <0>;
-		status = "disabled";
-	};
-
-	isp: isp@ff4a0000 {
-		compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
-		reg = <0x0 0xff4a0000 0x0 0x8000>;
-		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "isp", "mi", "mipi";
-		clocks = <&cru SCLK_ISP>,
-			 <&cru ACLK_ISP>,
-			 <&cru HCLK_ISP>,
-			 <&cru PCLK_ISP>;
-		clock-names = "isp", "aclk", "hclk", "pclk";
-		iommus = <&isp_mmu>;
-		phys = <&csi_dphy>;
-		phy-names = "dphy";
-		power-domains = <&power PX30_PD_VI>;
-		status = "disabled";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-	};
-
-	isp_mmu: iommu@ff4a8000 {
-		compatible = "rockchip,iommu";
-		reg = <0x0 0xff4a8000 0x0 0x100>;
-		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
-		clock-names = "aclk", "iface";
-		power-domains = <&power PX30_PD_VI>;
-		rockchip,disable-mmu-reset;
-		#iommu-cells = <0>;
-	};
-
-	qos_gmac: qos@ff518000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff518000 0x0 0x20>;
-	};
-
-	qos_gpu: qos@ff520000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff520000 0x0 0x20>;
-	};
-
-	qos_sdmmc: qos@ff52c000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff52c000 0x0 0x20>;
-	};
-
-	qos_emmc: qos@ff538000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff538000 0x0 0x20>;
-	};
-
-	qos_nand: qos@ff538080 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff538080 0x0 0x20>;
-	};
-
-	qos_sdio: qos@ff538100 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff538100 0x0 0x20>;
-	};
-
-	qos_sfc: qos@ff538180 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff538180 0x0 0x20>;
-	};
-
-	qos_usb_host: qos@ff540000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff540000 0x0 0x20>;
-	};
-
-	qos_usb_otg: qos@ff540080 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff540080 0x0 0x20>;
-	};
-
-	qos_isp_128: qos@ff548000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff548000 0x0 0x20>;
-	};
-
-	qos_isp_rd: qos@ff548080 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff548080 0x0 0x20>;
-	};
-
-	qos_isp_wr: qos@ff548100 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff548100 0x0 0x20>;
-	};
-
-	qos_isp_m1: qos@ff548180 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff548180 0x0 0x20>;
-	};
-
-	qos_vip: qos@ff548200 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff548200 0x0 0x20>;
-	};
-
-	qos_rga_rd: qos@ff550000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff550000 0x0 0x20>;
-	};
-
-	qos_rga_wr: qos@ff550080 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff550080 0x0 0x20>;
-	};
-
-	qos_vop_m0: qos@ff550100 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff550100 0x0 0x20>;
-	};
-
-	qos_vop_m1: qos@ff550180 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff550180 0x0 0x20>;
-	};
-
-	qos_vpu: qos@ff558000 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff558000 0x0 0x20>;
-	};
-
-	qos_vpu_r128: qos@ff558080 {
-		compatible = "rockchip,px30-qos", "syscon";
-		reg = <0x0 0xff558080 0x0 0x20>;
-	};
-
-	pinctrl: pinctrl {
-		compatible = "rockchip,px30-pinctrl";
-		rockchip,grf = <&grf>;
-		rockchip,pmu = <&pmugrf>;
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		gpio0: gpio@ff040000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x0 0xff040000 0x0 0x100>;
-			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pmucru PCLK_GPIO0_PMU>;
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 0 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio@ff250000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x0 0xff250000 0x0 0x100>;
-			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>;
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 32 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@ff260000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x0 0xff260000 0x0 0x100>;
-			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>;
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 64 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@ff270000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x0 0xff270000 0x0 0x100>;
-			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>;
-			gpio-controller;
-			gpio-ranges = <&pinctrl 0 96 32>;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
-		pcfg_pull_down: pcfg-pull-down {
-			bias-pull-down;
-		};
-
-		pcfg_pull_none: pcfg-pull-none {
-			bias-disable;
-		};
-
-		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
-			bias-disable;
-			drive-strength = <2>;
-		};
-
-		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
-			bias-pull-up;
-			drive-strength = <2>;
-		};
-
-		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
-			bias-pull-up;
-			drive-strength = <4>;
-		};
-
-		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
-			bias-disable;
-			drive-strength = <4>;
-		};
-
-		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
-			bias-pull-down;
-			drive-strength = <4>;
-		};
-
-		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
-			bias-disable;
-			drive-strength = <8>;
-		};
-
-		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
-			bias-pull-up;
-			drive-strength = <8>;
-		};
-
-		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
-			bias-disable;
-			drive-strength = <12>;
-		};
-
-		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
-			bias-pull-up;
-			drive-strength = <12>;
-		};
-
-		pcfg_pull_none_smt: pcfg-pull-none-smt {
-			bias-disable;
-			input-schmitt-enable;
-		};
-
-		pcfg_output_high: pcfg-output-high {
-			output-high;
-		};
-
-		pcfg_output_low: pcfg-output-low {
-			output-low;
-		};
-
-		pcfg_input_high: pcfg-input-high {
-			bias-pull-up;
-			input-enable;
-		};
-
-		pcfg_input: pcfg-input {
-			input-enable;
-		};
-
-		i2c0 {
-			i2c0_xfer: i2c0-xfer {
-				rockchip,pins =
-					<0 RK_PB0 1 &pcfg_pull_none_smt>,
-					<0 RK_PB1 1 &pcfg_pull_none_smt>;
-			};
-		};
-
-		i2c1 {
-			i2c1_xfer: i2c1-xfer {
-				rockchip,pins =
-					<0 RK_PC2 1 &pcfg_pull_none_smt>,
-					<0 RK_PC3 1 &pcfg_pull_none_smt>;
-			};
-		};
-
-		i2c2 {
-			i2c2_xfer: i2c2-xfer {
-				rockchip,pins =
-					<2 RK_PB7 2 &pcfg_pull_none_smt>,
-					<2 RK_PC0 2 &pcfg_pull_none_smt>;
-			};
-		};
-
-		i2c3 {
-			i2c3_xfer: i2c3-xfer {
-				rockchip,pins =
-					<1 RK_PB4 4 &pcfg_pull_none_smt>,
-					<1 RK_PB5 4 &pcfg_pull_none_smt>;
-			};
-		};
-
-		tsadc {
-			tsadc_otp_pin: tsadc-otp-pin {
-				rockchip,pins =
-					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-			};
-
-			tsadc_otp_out: tsadc-otp-out {
-				rockchip,pins =
-					<0 RK_PA6 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart0 {
-			uart0_xfer: uart0-xfer {
-				rockchip,pins =
-					<0 RK_PB2 1 &pcfg_pull_up>,
-					<0 RK_PB3 1 &pcfg_pull_up>;
-			};
-
-			uart0_cts: uart0-cts {
-				rockchip,pins =
-					<0 RK_PB4 1 &pcfg_pull_none>;
-			};
-
-			uart0_rts: uart0-rts {
-				rockchip,pins =
-					<0 RK_PB5 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart1 {
-			uart1_xfer: uart1-xfer {
-				rockchip,pins =
-					<1 RK_PC1 1 &pcfg_pull_up>,
-					<1 RK_PC0 1 &pcfg_pull_up>;
-			};
-
-			uart1_cts: uart1-cts {
-				rockchip,pins =
-					<1 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			uart1_rts: uart1-rts {
-				rockchip,pins =
-					<1 RK_PC3 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart2-m0 {
-			uart2m0_xfer: uart2m0-xfer {
-				rockchip,pins =
-					<1 RK_PD2 2 &pcfg_pull_up>,
-					<1 RK_PD3 2 &pcfg_pull_up>;
-			};
-		};
-
-		uart2-m1 {
-			uart2m1_xfer: uart2m1-xfer {
-				rockchip,pins =
-					<2 RK_PB4 2 &pcfg_pull_up>,
-					<2 RK_PB6 2 &pcfg_pull_up>;
-			};
-		};
-
-		uart3-m0 {
-			uart3m0_xfer: uart3m0-xfer {
-				rockchip,pins =
-					<0 RK_PC0 2 &pcfg_pull_up>,
-					<0 RK_PC1 2 &pcfg_pull_up>;
-			};
-
-			uart3m0_cts: uart3m0-cts {
-				rockchip,pins =
-					<0 RK_PC2 2 &pcfg_pull_none>;
-			};
-
-			uart3m0_rts: uart3m0-rts {
-				rockchip,pins =
-					<0 RK_PC3 2 &pcfg_pull_none>;
-			};
-		};
-
-		uart3-m1 {
-			uart3m1_xfer: uart3m1-xfer {
-				rockchip,pins =
-					<1 RK_PB6 2 &pcfg_pull_up>,
-					<1 RK_PB7 2 &pcfg_pull_up>;
-			};
-
-			uart3m1_cts: uart3m1-cts {
-				rockchip,pins =
-					<1 RK_PB4 2 &pcfg_pull_none>;
-			};
-
-			uart3m1_rts: uart3m1-rts {
-				rockchip,pins =
-					<1 RK_PB5 2 &pcfg_pull_none>;
-			};
-		};
-
-		uart4 {
-			uart4_xfer: uart4-xfer {
-				rockchip,pins =
-					<1 RK_PD4 2 &pcfg_pull_up>,
-					<1 RK_PD5 2 &pcfg_pull_up>;
-			};
-
-			uart4_cts: uart4-cts {
-				rockchip,pins =
-					<1 RK_PD6 2 &pcfg_pull_none>;
-			};
-
-			uart4_rts: uart4-rts {
-				rockchip,pins =
-					<1 RK_PD7 2 &pcfg_pull_none>;
-			};
-		};
-
-		uart5 {
-			uart5_xfer: uart5-xfer {
-				rockchip,pins =
-					<3 RK_PA2 4 &pcfg_pull_up>,
-					<3 RK_PA1 4 &pcfg_pull_up>;
-			};
-
-			uart5_cts: uart5-cts {
-				rockchip,pins =
-					<3 RK_PA3 4 &pcfg_pull_none>;
-			};
-
-			uart5_rts: uart5-rts {
-				rockchip,pins =
-					<3 RK_PA5 4 &pcfg_pull_none>;
-			};
-		};
-
-		spi0 {
-			spi0_clk: spi0-clk {
-				rockchip,pins =
-					<1 RK_PB7 3 &pcfg_pull_up_4ma>;
-			};
-
-			spi0_csn: spi0-csn {
-				rockchip,pins =
-					<1 RK_PB6 3 &pcfg_pull_up_4ma>;
-			};
-
-			spi0_miso: spi0-miso {
-				rockchip,pins =
-					<1 RK_PB5 3 &pcfg_pull_up_4ma>;
-			};
-
-			spi0_mosi: spi0-mosi {
-				rockchip,pins =
-					<1 RK_PB4 3 &pcfg_pull_up_4ma>;
-			};
-
-			spi0_clk_hs: spi0-clk-hs {
-				rockchip,pins =
-					<1 RK_PB7 3 &pcfg_pull_up_8ma>;
-			};
-
-			spi0_miso_hs: spi0-miso-hs {
-				rockchip,pins =
-					<1 RK_PB5 3 &pcfg_pull_up_8ma>;
-			};
-
-			spi0_mosi_hs: spi0-mosi-hs {
-				rockchip,pins =
-					<1 RK_PB4 3 &pcfg_pull_up_8ma>;
-			};
-		};
-
-		spi1 {
-			spi1_clk: spi1-clk {
-				rockchip,pins =
-					<3 RK_PB7 4 &pcfg_pull_up_4ma>;
-			};
-
-			spi1_csn0: spi1-csn0 {
-				rockchip,pins =
-					<3 RK_PB1 4 &pcfg_pull_up_4ma>;
-			};
-
-			spi1_csn1: spi1-csn1 {
-				rockchip,pins =
-					<3 RK_PB2 2 &pcfg_pull_up_4ma>;
-			};
-
-			spi1_miso: spi1-miso {
-				rockchip,pins =
-					<3 RK_PB6 4 &pcfg_pull_up_4ma>;
-			};
-
-			spi1_mosi: spi1-mosi {
-				rockchip,pins =
-					<3 RK_PB4 4 &pcfg_pull_up_4ma>;
-			};
-
-			spi1_clk_hs: spi1-clk-hs {
-				rockchip,pins =
-					<3 RK_PB7 4 &pcfg_pull_up_8ma>;
-			};
-
-			spi1_miso_hs: spi1-miso-hs {
-				rockchip,pins =
-					<3 RK_PB6 4 &pcfg_pull_up_8ma>;
-			};
-
-			spi1_mosi_hs: spi1-mosi-hs {
-				rockchip,pins =
-					<3 RK_PB4 4 &pcfg_pull_up_8ma>;
-			};
-		};
-
-		pdm {
-			pdm_clk0m0: pdm-clk0m0 {
-				rockchip,pins =
-					<3 RK_PC6 2 &pcfg_pull_none>;
-			};
-
-			pdm_clk0m1: pdm-clk0m1 {
-				rockchip,pins =
-					<2 RK_PC6 1 &pcfg_pull_none>;
-			};
-
-			pdm_clk1: pdm-clk1 {
-				rockchip,pins =
-					<3 RK_PC7 2 &pcfg_pull_none>;
-			};
-
-			pdm_sdi0m0: pdm-sdi0m0 {
-				rockchip,pins =
-					<3 RK_PD3 2 &pcfg_pull_none>;
-			};
-
-			pdm_sdi0m1: pdm-sdi0m1 {
-				rockchip,pins =
-					<2 RK_PC5 2 &pcfg_pull_none>;
-			};
-
-			pdm_sdi1: pdm-sdi1 {
-				rockchip,pins =
-					<3 RK_PD0 2 &pcfg_pull_none>;
-			};
-
-			pdm_sdi2: pdm-sdi2 {
-				rockchip,pins =
-					<3 RK_PD1 2 &pcfg_pull_none>;
-			};
-
-			pdm_sdi3: pdm-sdi3 {
-				rockchip,pins =
-					<3 RK_PD2 2 &pcfg_pull_none>;
-			};
-
-			pdm_clk0m0_sleep: pdm-clk0m0-sleep {
-				rockchip,pins =
-					<3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_clk0m_sleep1: pdm-clk0m1-sleep {
-				rockchip,pins =
-					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_clk1_sleep: pdm-clk1-sleep {
-				rockchip,pins =
-					<3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
-				rockchip,pins =
-					<3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
-				rockchip,pins =
-					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_sdi1_sleep: pdm-sdi1-sleep {
-				rockchip,pins =
-					<3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_sdi2_sleep: pdm-sdi2-sleep {
-				rockchip,pins =
-					<3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-
-			pdm_sdi3_sleep: pdm-sdi3-sleep {
-				rockchip,pins =
-					<3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
-			};
-		};
-
-		i2s0 {
-			i2s0_8ch_mclk: i2s0-8ch-mclk {
-				rockchip,pins =
-					<3 RK_PC1 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sclktx: i2s0-8ch-sclktx {
-				rockchip,pins =
-					<3 RK_PC3 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
-				rockchip,pins =
-					<3 RK_PB4 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
-				rockchip,pins =
-					<3 RK_PC2 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
-				rockchip,pins =
-					<3 RK_PB5 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
-				rockchip,pins =
-					<3 RK_PC4 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
-				rockchip,pins =
-					<3 RK_PC0 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
-				rockchip,pins =
-					<3 RK_PB7 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
-				rockchip,pins =
-					<3 RK_PB6 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
-				rockchip,pins =
-					<3 RK_PC5 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
-				rockchip,pins =
-					<3 RK_PB3 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
-				rockchip,pins =
-					<3 RK_PB1 2 &pcfg_pull_none>;
-			};
-
-			i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
-				rockchip,pins =
-					<3 RK_PB0 2 &pcfg_pull_none>;
-			};
-		};
-
-		i2s1 {
-			i2s1_2ch_mclk: i2s1-2ch-mclk {
-				rockchip,pins =
-					<2 RK_PC3 1 &pcfg_pull_none>;
-			};
-
-			i2s1_2ch_sclk: i2s1-2ch-sclk {
-				rockchip,pins =
-					<2 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			i2s1_2ch_lrck: i2s1-2ch-lrck {
-				rockchip,pins =
-					<2 RK_PC1 1 &pcfg_pull_none>;
-			};
-
-			i2s1_2ch_sdi: i2s1-2ch-sdi {
-				rockchip,pins =
-					<2 RK_PC5 1 &pcfg_pull_none>;
-			};
-
-			i2s1_2ch_sdo: i2s1-2ch-sdo {
-				rockchip,pins =
-					<2 RK_PC4 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2s2 {
-			i2s2_2ch_mclk: i2s2-2ch-mclk {
-				rockchip,pins =
-					<3 RK_PA1 2 &pcfg_pull_none>;
-			};
-
-			i2s2_2ch_sclk: i2s2-2ch-sclk {
-				rockchip,pins =
-					<3 RK_PA2 2 &pcfg_pull_none>;
-			};
-
-			i2s2_2ch_lrck: i2s2-2ch-lrck {
-				rockchip,pins =
-					<3 RK_PA3 2 &pcfg_pull_none>;
-			};
-
-			i2s2_2ch_sdi: i2s2-2ch-sdi {
-				rockchip,pins =
-					<3 RK_PA5 2 &pcfg_pull_none>;
-			};
-
-			i2s2_2ch_sdo: i2s2-2ch-sdo {
-				rockchip,pins =
-					<3 RK_PA7 2 &pcfg_pull_none>;
-			};
-		};
-
-		sdmmc {
-			sdmmc_clk: sdmmc-clk {
-				rockchip,pins =
-					<1 RK_PD6 1 &pcfg_pull_none_8ma>;
-			};
-
-			sdmmc_cmd: sdmmc-cmd {
-				rockchip,pins =
-					<1 RK_PD7 1 &pcfg_pull_up_8ma>;
-			};
-
-			sdmmc_det: sdmmc-det {
-				rockchip,pins =
-					<0 RK_PA3 1 &pcfg_pull_up_8ma>;
-			};
-
-			sdmmc_bus1: sdmmc-bus1 {
-				rockchip,pins =
-					<1 RK_PD2 1 &pcfg_pull_up_8ma>;
-			};
-
-			sdmmc_bus4: sdmmc-bus4 {
-				rockchip,pins =
-					<1 RK_PD2 1 &pcfg_pull_up_8ma>,
-					<1 RK_PD3 1 &pcfg_pull_up_8ma>,
-					<1 RK_PD4 1 &pcfg_pull_up_8ma>,
-					<1 RK_PD5 1 &pcfg_pull_up_8ma>;
-			};
-		};
-
-		sdio {
-			sdio_clk: sdio-clk {
-				rockchip,pins =
-					<1 RK_PC5 1 &pcfg_pull_none>;
-			};
-
-			sdio_cmd: sdio-cmd {
-				rockchip,pins =
-					<1 RK_PC4 1 &pcfg_pull_up>;
-			};
-
-			sdio_bus4: sdio-bus4 {
-				rockchip,pins =
-					<1 RK_PC6 1 &pcfg_pull_up>,
-					<1 RK_PC7 1 &pcfg_pull_up>,
-					<1 RK_PD0 1 &pcfg_pull_up>,
-					<1 RK_PD1 1 &pcfg_pull_up>;
-			};
-		};
-
-		emmc {
-			emmc_clk: emmc-clk {
-				rockchip,pins =
-					<1 RK_PB1 2 &pcfg_pull_none_8ma>;
-			};
-
-			emmc_cmd: emmc-cmd {
-				rockchip,pins =
-					<1 RK_PB2 2 &pcfg_pull_up_8ma>;
-			};
-
-			emmc_rstnout: emmc-rstnout {
-				rockchip,pins =
-					<1 RK_PB3 2 &pcfg_pull_none>;
-			};
-
-			emmc_bus1: emmc-bus1 {
-				rockchip,pins =
-					<1 RK_PA0 2 &pcfg_pull_up_8ma>;
-			};
-
-			emmc_bus4: emmc-bus4 {
-				rockchip,pins =
-					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA3 2 &pcfg_pull_up_8ma>;
-			};
-
-			emmc_bus8: emmc-bus8 {
-				rockchip,pins =
-					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA3 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA4 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA5 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA6 2 &pcfg_pull_up_8ma>,
-					<1 RK_PA7 2 &pcfg_pull_up_8ma>;
-			};
-		};
-
-		flash {
-			flash_cs0: flash-cs0 {
-				rockchip,pins =
-					<1 RK_PB0 1 &pcfg_pull_none>;
-			};
-
-			flash_rdy: flash-rdy {
-				rockchip,pins =
-					<1 RK_PB1 1 &pcfg_pull_none>;
-			};
-
-			flash_dqs: flash-dqs {
-				rockchip,pins =
-					<1 RK_PB2 1 &pcfg_pull_none>;
-			};
-
-			flash_ale: flash-ale {
-				rockchip,pins =
-					<1 RK_PB3 1 &pcfg_pull_none>;
-			};
-
-			flash_cle: flash-cle {
-				rockchip,pins =
-					<1 RK_PB4 1 &pcfg_pull_none>;
-			};
-
-			flash_wrn: flash-wrn {
-				rockchip,pins =
-					<1 RK_PB5 1 &pcfg_pull_none>;
-			};
-
-			flash_csl: flash-csl {
-				rockchip,pins =
-					<1 RK_PB6 1 &pcfg_pull_none>;
-			};
-
-			flash_rdn: flash-rdn {
-				rockchip,pins =
-					<1 RK_PB7 1 &pcfg_pull_none>;
-			};
-
-			flash_bus8: flash-bus8 {
-				rockchip,pins =
-					<1 RK_PA0 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA1 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA2 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA3 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA4 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA5 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA6 1 &pcfg_pull_up_12ma>,
-					<1 RK_PA7 1 &pcfg_pull_up_12ma>;
-			};
-		};
-
-		sfc {
-			sfc_bus4: sfc-bus4 {
-				rockchip,pins =
-					<1 RK_PA0 3 &pcfg_pull_none>,
-					<1 RK_PA1 3 &pcfg_pull_none>,
-					<1 RK_PA2 3 &pcfg_pull_none>,
-					<1 RK_PA3 3 &pcfg_pull_none>;
-			};
-
-			sfc_bus2: sfc-bus2 {
-				rockchip,pins =
-					<1 RK_PA0 3 &pcfg_pull_none>,
-					<1 RK_PA1 3 &pcfg_pull_none>;
-			};
-
-			sfc_cs0: sfc-cs0 {
-				rockchip,pins =
-					<1 RK_PA4 3 &pcfg_pull_none>;
-			};
-
-			sfc_clk: sfc-clk {
-				rockchip,pins =
-					<1 RK_PB1 3 &pcfg_pull_none>;
-			};
-		};
-
-		lcdc {
-			lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
-				rockchip,pins =
-					<3 RK_PA0 1 &pcfg_pull_none_12ma>;
-			};
-
-			lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
-				rockchip,pins =
-					<3 RK_PA1 1 &pcfg_pull_none_12ma>;
-			};
-
-			lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
-				rockchip,pins =
-					<3 RK_PA2 1 &pcfg_pull_none_12ma>;
-			};
-
-			lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
-				rockchip,pins =
-					<3 RK_PA3 1 &pcfg_pull_none_12ma>;
-			};
-
-			lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
-				rockchip,pins =
-					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
-					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
-					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
-					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
-					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
-					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
-					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
-					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
-					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
-					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
-					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
-					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
-					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
-					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
-					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
-					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
-					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
-					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
-					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
-					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
-					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
-					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
-					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
-					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
-			};
-
-			lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
-				rockchip,pins =
-					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
-					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
-					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
-					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
-					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
-					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
-					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
-					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
-					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
-					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
-					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
-					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
-					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
-					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
-					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
-					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
-					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
-					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
-			};
-
-			lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
-				rockchip,pins =
-					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
-					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
-					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
-					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
-					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
-					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
-					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
-					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
-					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
-					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
-					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
-					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
-					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
-					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
-					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
-					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
-			};
-
-			lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
-				rockchip,pins =
-					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
-					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
-					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
-					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
-					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
-					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
-					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
-					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
-					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
-					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
-					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
-					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
-					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
-					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
-					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
-					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
-					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
-			};
-
-			lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
-				rockchip,pins =
-					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
-					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
-					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
-					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
-					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
-					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
-					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
-					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
-					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
-					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
-					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
-			};
-
-			lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
-				rockchip,pins =
-					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
-					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
-					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
-					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
-					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
-					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
-					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
-					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
-					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
-			};
-		};
-
-		pwm0 {
-			pwm0_pin: pwm0-pin {
-				rockchip,pins =
-					<0 RK_PB7 1 &pcfg_pull_none>;
-			};
-		};
-
-		pwm1 {
-			pwm1_pin: pwm1-pin {
-				rockchip,pins =
-					<0 RK_PC0 1 &pcfg_pull_none>;
-			};
-		};
-
-		pwm2 {
-			pwm2_pin: pwm2-pin {
-				rockchip,pins =
-					<2 RK_PB5 1 &pcfg_pull_none>;
-			};
-		};
-
-		pwm3 {
-			pwm3_pin: pwm3-pin {
-				rockchip,pins =
-					<0 RK_PC1 1 &pcfg_pull_none>;
-			};
-		};
-
-		pwm4 {
-			pwm4_pin: pwm4-pin {
-				rockchip,pins =
-					<3 RK_PC2 3 &pcfg_pull_none>;
-			};
-		};
-
-		pwm5 {
-			pwm5_pin: pwm5-pin {
-				rockchip,pins =
-					<3 RK_PC3 3 &pcfg_pull_none>;
-			};
-		};
-
-		pwm6 {
-			pwm6_pin: pwm6-pin {
-				rockchip,pins =
-					<3 RK_PC4 3 &pcfg_pull_none>;
-			};
-		};
-
-		pwm7 {
-			pwm7_pin: pwm7-pin {
-				rockchip,pins =
-					<3 RK_PC5 3 &pcfg_pull_none>;
-			};
-		};
-
-		gmac {
-			rmii_pins: rmii-pins {
-				rockchip,pins =
-					<2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
-					<2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
-					<2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
-					<2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
-					<2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
-					<2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
-					<2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
-					<2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
-					<2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
-			};
-
-			mac_refclk_12ma: mac-refclk-12ma {
-				rockchip,pins =
-					<2 RK_PB2 2 &pcfg_pull_none_12ma>;
-			};
-
-			mac_refclk: mac-refclk {
-				rockchip,pins =
-					<2 RK_PB2 2 &pcfg_pull_none>;
-			};
-		};
-
-		cif-m0 {
-			cif_clkout_m0: cif-clkout-m0 {
-				rockchip,pins =
-					<2 RK_PB3 1 &pcfg_pull_none>;
-			};
-
-			dvp_d2d9_m0: dvp-d2d9-m0 {
-				rockchip,pins =
-					<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
-					<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
-					<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
-					<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
-					<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
-					<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
-					<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
-					<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
-					<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
-					<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
-					<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
-					<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
-			};
-
-			dvp_d0d1_m0: dvp-d0d1-m0 {
-				rockchip,pins =
-					<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
-					<2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
-			};
-
-			dvp_d10d11_m0:d10-d11-m0 {
-				rockchip,pins =
-					<2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
-					<2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
-			};
-		};
-
-		cif-m1 {
-			cif_clkout_m1: cif-clkout-m1 {
-				rockchip,pins =
-					<3 RK_PD0 3 &pcfg_pull_none>;
-			};
-
-			dvp_d2d9_m1: dvp-d2d9-m1 {
-				rockchip,pins =
-					<3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
-					<3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
-					<3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
-					<3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
-					<3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
-					<3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
-					<3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
-					<3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
-					<3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
-					<3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
-					<3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
-					<3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
-			};
-
-			dvp_d0d1_m1: dvp-d0d1-m1 {
-				rockchip,pins =
-					<3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
-					<3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
-			};
-
-			dvp_d10d11_m1:d10-d11-m1 {
-				rockchip,pins =
-					<3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
-					<3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
-			};
-		};
-
-		isp {
-			isp_prelight: isp-prelight {
-				rockchip,pins =
-					<3 RK_PD1 4 &pcfg_pull_none>;
-			};
-		};
-	};
-};
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index a6fb8b12da3..ff5bab316a3 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -4,17 +4,6 @@
  */
 #include "rk3308-u-boot.dtsi"
 
-&emmc {
-	cap-sd-highspeed;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
-};
-
-&emmc_bus4 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
 &u2phy_otg {
 	/delete-property/ phy-supply;
 };
@@ -24,14 +13,6 @@
 	clock-frequency = <24000000>;
 };
 
-&uart0_cts {
-	bootph-all;
-};
-
-&uart0_rts {
-	bootph-all;
-};
-
 &uart0_xfer {
 	bootph-all;
 };
diff --git a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi
new file mode 100644
index 00000000000..84ca2ee0d5f
--- /dev/null
+++ b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3308-u-boot.dtsi"
+
+&emmc_pwren {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&uart0 {
+	bootph-all;
+	clock-frequency = <24000000>;
+};
+
+&uart0_xfer {
+	bootph-all;
+};
+
+&vdd_core {
+	regulator-init-microvolt = <1015000>;
+};
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index 684fa7abddb..b7964e2756f 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -21,22 +21,6 @@
 		bootph-all;
 	};
 
-	otp: nvmem@ff210000 {
-		compatible = "rockchip,rk3308-otp";
-		reg = <0x0 0xff210000 0x0 0x4000>;
-		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
-			 <&cru PCLK_OTP_PHY>;
-		clock-names = "otp", "apb_pclk", "phy";
-		resets = <&cru SRST_OTP_PHY>;
-		reset-names = "phy";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		cpu_id: id@7 {
-			reg = <0x07 0x10>;
-		};
-	};
-
 	rng: rng@ff2f0000 {
 		compatible = "rockchip,cryptov2-rng";
 		reg = <0x0 0xff2f0000 0x0 0x4000>;
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index a31dea8db3e..a0ab8b69f2e 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -48,18 +48,22 @@
 
 &gpio0 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 0 32>;
 };
 
 &gpio1 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 32 32>;
 };
 
 &gpio2 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 64 32>;
 };
 
 &gpio3 {
 	bootph-all;
+	gpio-ranges = <&pinctrl 0 96 32>;
 };
 
 &grf {
diff --git a/arch/arm/dts/rk3326.dtsi b/arch/arm/dts/rk3326.dtsi
deleted file mode 100644
index 2ba6da12513..00000000000
--- a/arch/arm/dts/rk3326.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include "px30.dtsi"
-
-&display_subsystem {
-	ports = <&vopb_out>;
-};
-
-/delete-node/ &dsi_in_vopl;
-/delete-node/ &lvds_vopl_in;
-/delete-node/ &vopl;
-/delete-node/ &vopl_mmu;
diff --git a/arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi b/arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi
new file mode 100644
index 00000000000..e44b699af72
--- /dev/null
+++ b/arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&sfc {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
diff --git a/arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi b/arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi
new file mode 100644
index 00000000000..50ea6ede728
--- /dev/null
+++ b/arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-orangepi-3b-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-orangepi-3b-v1.1.dts b/arch/arm/dts/rk3566-orangepi-3b-v1.1.dts
new file mode 100644
index 00000000000..f97e33bd810
--- /dev/null
+++ b/arch/arm/dts/rk3566-orangepi-3b-v1.1.dts
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <arm64/rockchip/rk3566-orangepi-3b-v1.1.dts>
diff --git a/arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi b/arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi
new file mode 100644
index 00000000000..50ea6ede728
--- /dev/null
+++ b/arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-orangepi-3b-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-orangepi-3b-v2.1.dts b/arch/arm/dts/rk3566-orangepi-3b-v2.1.dts
new file mode 100644
index 00000000000..0031e2477ab
--- /dev/null
+++ b/arch/arm/dts/rk3566-orangepi-3b-v2.1.dts
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <arm64/rockchip/rk3566-orangepi-3b-v2.1.dts>
diff --git a/arch/arm/dts/rk3566-orangepi-3b.dts b/arch/arm/dts/rk3566-orangepi-3b.dts
new file mode 100644
index 00000000000..44b9a9c89f0
--- /dev/null
+++ b/arch/arm/dts/rk3566-orangepi-3b.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3566-orangepi-3b.dtsi>
diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1.dts b/arch/arm/dts/rk3566-pinetab2-v0.1.dts
deleted file mode 100644
index 5fe6ca5da9d..00000000000
--- a/arch/arm/dts/rk3566-pinetab2-v0.1.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "rk3566-pinetab2.dtsi"
-
-/ {
-	model = "Pine64 PineTab2 v0.1";
-	compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566";
-};
-
-&lcd {
-	reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
-};
-
-&pinctrl {
-	lcd0 {
-		lcd0_rst_l: lcd0-rst-l {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&sdmmc1 {
-	vmmc-supply = <&vcc3v3_sys>;
-};
diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0.dts b/arch/arm/dts/rk3566-pinetab2-v2.0.dts
deleted file mode 100644
index 9349541cbbd..00000000000
--- a/arch/arm/dts/rk3566-pinetab2-v2.0.dts
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "rk3566-pinetab2.dtsi"
-
-/ {
-	model = "Pine64 PineTab2 v2.0";
-	compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566";
-};
-
-&gpio_keys {
-	pinctrl-0 = <&kb_id_det>, <&hall_int_l>;
-
-	event-hall-sensor {
-		debounce-interval = <20>;
-		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
-		label = "Hall Sensor";
-		linux,code = <SW_LID>;
-		linux,input-type = <EV_SW>;
-		wakeup-event-action = <EV_ACT_DEASSERTED>;
-		wakeup-source;
-	};
-};
-
-&lcd {
-	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
-};
-
-&pinctrl {
-	lcd0 {
-		lcd0_rst_l: lcd0-rst-l {
-			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	hall {
-		hall_int_l: hall-int-l {
-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&sdmmc1 {
-	vmmc-supply = <&vcc_sys>;
-};
diff --git a/arch/arm/dts/rk3566-pinetab2.dtsi b/arch/arm/dts/rk3566-pinetab2.dtsi
deleted file mode 100644
index db40281eafb..00000000000
--- a/arch/arm/dts/rk3566-pinetab2.dtsi
+++ /dev/null
@@ -1,943 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/gpio-keys.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include <dt-bindings/usb/pd.h>
-#include "rk3566.dtsi"
-
-/ {
-	chassis-type = "tablet";
-
-	aliases {
-		mmc0 = &sdhci;
-		mmc1 = &sdmmc0;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	adc-keys {
-		compatible = "adc-keys";
-		io-channels = <&saradc 0>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <25>;
-
-		button-vol-up {
-			label = "Volume Up";
-			linux,code = <KEY_VOLUMEUP>;
-			press-threshold-microvolt = <297500>;
-		};
-
-		button-vol-down {
-			label = "Volume Down";
-			linux,code = <KEY_VOLUMEDOWN>;
-			press-threshold-microvolt = <1750>;
-		};
-	};
-
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		pwms = <&pwm4 0 25000 0>;
-		brightness-levels = <20 220>;
-		num-interpolated-steps = <200>;
-		default-brightness-level = <100>;
-		power-supply = <&vcc_sys>;
-	};
-
-	battery: battery {
-		compatible = "simple-battery";
-		charge-full-design-microamp-hours = <6000000>;
-		charge-term-current-microamp = <300000>;
-		constant-charge-current-max-microamp = <2000000>;
-		constant-charge-voltage-max-microvolt = <4300000>;
-		voltage-max-design-microvolt = <4350000>;
-		voltage-min-design-microvolt = <3400000>;
-
-		ocv-capacity-celsius = <20>;
-		ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>,
-				       <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>,
-				       <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>,
-				       <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>,
-				       <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>,
-				       <3400000 0>;
-	};
-
-	gpio_keys: gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&kb_id_det>;
-
-		tablet-mode-switch {
-			debounce-interval = <20>;
-			gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
-			label = "Tablet Mode";
-			linux,input-type = <EV_SW>;
-			linux,code = <SW_TABLET_MODE>;
-		};
-	};
-
-	hdmi-connector {
-		compatible = "hdmi-connector";
-		type = "d";
-
-		port {
-			hdmi_con_in: endpoint {
-				remote-endpoint = <&hdmi_out_con>;
-			};
-		};
-	};
-
-	led-0 {
-		compatible = "regulator-led";
-		vled-supply = <&vcc5v0_flashled>;
-		color = <LED_COLOR_ID_WHITE>;
-		function = LED_FUNCTION_FLASH;
-	};
-
-	rk817-sound {
-		compatible = "simple-audio-card";
-		pinctrl-names = "default";
-		pinctrl-0 = <&hp_det_l>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,name = "rk817_ext";
-		simple-audio-card,mclk-fs = <256>;
-
-		simple-audio-card,widgets =
-			"Microphone", "Mic Jack",
-			"Headphone", "Headphones",
-			"Speaker", "Internal Speakers";
-
-		simple-audio-card,routing =
-			"MICR", "Mic Jack",
-			"Headphones", "HPOL",
-			"Headphones", "HPOR",
-			"Internal Speakers", "Speaker Amplifier OUTL",
-			"Internal Speakers", "Speaker Amplifier OUTR",
-			"Speaker Amplifier INL", "HPOL",
-			"Speaker Amplifier INR", "HPOR";
-		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
-		simple-audio-card,aux-devs = <&speaker_amp>;
-		simple-audio-card,pin-switches = "Internal Speakers";
-
-		simple-audio-card,cpu {
-			sound-dai = <&i2s1_8ch>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&rk817>;
-		};
-	};
-
-	speaker_amp: speaker-amplifier {
-		compatible = "simple-audio-amplifier";
-		pinctrl-names = "default";
-		pinctrl-0 = <&spk_ctl>;
-		enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
-		sound-name-prefix = "Speaker Amplifier";
-		VCC-supply = <&vcc_bat>;
-	};
-
-	vcc_3v3: vcc-3v3-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_3v3";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_pwren_h>;
-		regulator-name = "vcc3v3_minipcie";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vcc3v3_sd: vcc3v3-sd-regulator {
-		compatible = "regulator-fixed";
-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdmmc_pwren_l>;
-		regulator-name = "vcc3v3_sd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc3v3_sys>;
-	};
-
-	vcc5v0_flashled: vcc5v0-flashled-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&flash_led_en_h>;
-		regulator-name = "vcc5v0_flashled";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v_midu>;
-	};
-
-	vcc5v0_usb_host0: vcc5v0-usb-host0-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&usb_host_pwren1_h>;
-		regulator-name = "vcc5v0_usb_host0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v_midu>;
-	};
-
-	vcc5v0_usb_host2: vcc5v0-usb-host2-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&usb_host_pwren2_h>;
-		regulator-name = "vcc5v0_usb_host2";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v_midu>;
-	};
-
-	vcc_bat: vcc-bat-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_bat";
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc_sys: vcc-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc_bat>;
-	};
-
-	vdd1v2_dvp: vdd1v2-dvp-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd1v2_dvp";
-		regulator-min-microvolt = <1200000>;
-		regulator-max-microvolt = <1200000>;
-		vin-supply = <&vcc_3v3>;
-	};
-};
-
-&combphy1 {
-	status = "okay";
-};
-
-&combphy2 {
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&cru {
-	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
-			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
-	assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>;
-	assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
-};
-
-&csi_dphy {
-	status = "okay";
-};
-
-&dsi0 {
-	status = "okay";
-	clock-master;
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	lcd: panel@0 {
-		compatible = "boe,th101mb31ig002-28a";
-		reg = <0>;
-		backlight = <&backlight>;
-		enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
-		rotation = <90>;
-		power-supply = <&vcc_3v3>;
-
-		port@0 {
-			panel_in_dsi: endpoint@0 {
-				remote-endpoint = <&dsi0_out_con>;
-			};
-		};
-	};
-};
-
-&dsi0_in {
-	dsi0_in_vp1: endpoint {
-		remote-endpoint = <&vp1_out_dsi0>;
-	};
-};
-
-&dsi0_out {
-	dsi0_out_con: endpoint {
-		remote-endpoint = <&panel_in_dsi>;
-	};
-};
-
-&dsi_dphy0 {
-	status = "okay";
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu_npu>;
-	status = "okay";
-};
-
-&hdmi {
-	avdd-0v9-supply = <&vdda_0v9_p>;
-	avdd-1v8-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&hdmi_in {
-	hdmi_in_vp0: endpoint {
-		remote-endpoint = <&vp0_out_hdmi>;
-	};
-};
-
-&hdmi_out {
-	hdmi_out_con: endpoint {
-		remote-endpoint = <&hdmi_con_in>;
-	};
-};
-
-&hdmi_sound {
-	status = "okay";
-};
-
-&i2c0 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	vdd_cpu: regulator@1c {
-		compatible = "tcs,tcs4525";
-		reg = <0x1c>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu";
-		regulator-min-microvolt = <800000>;
-		regulator-max-microvolt = <1150000>;
-		regulator-ramp-delay = <2300>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	rk817: pmic@20 {
-		compatible = "rockchip,rk817";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
-		clock-names = "mclk";
-		clocks = <&cru I2S1_MCLKOUT_TX>;
-		clock-output-names = "rk808-clkout1", "rk808-clkout2";
-		#clock-cells = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
-		rockchip,system-power-controller;
-		#sound-dai-cells = <0>;
-		wakeup-source;
-
-		vcc1-supply = <&vcc_sys>;
-		vcc2-supply = <&vcc_sys>;
-		vcc3-supply = <&vcc_sys>;
-		vcc4-supply = <&vcc_sys>;
-		vcc5-supply = <&vcc_sys>;
-		vcc6-supply = <&vcc_sys>;
-		vcc7-supply = <&vcc_sys>;
-		vcc8-supply = <&vcc_sys>;
-		vcc9-supply = <&vcc5v_midu>;
-
-		regulators {
-			vdd_logic: DCDC_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-				regulator-initial-mode = <0x2>;
-				regulator-name = "vdd_logic";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu_npu: DCDC_REG2 {
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-				regulator-initial-mode = <0x2>;
-				regulator-name = "vdd_gpu_npu";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-name = "vcc_ddr";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc3v3_sys: DCDC_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-initial-mode = <0x2>;
-				regulator-name = "vcc3v3_sys";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcca1v8_pmu: LDO_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcca1v8_pmu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vdda_0v9_p: LDO_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-				regulator-name = "vdda_0v9_p";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdda0v9_pmu: LDO_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <900000>;
-				regulator-name = "vdda0v9_pmu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vccio_acodec: LDO_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vccio_acodec";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vccio_sd";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_pmu: LDO_REG6 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc3v3_pmu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_1v8: LDO_REG7 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc_1v8";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc1v8_dvp: LDO_REG8 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc1v8_dvp";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc2v8_dvp: LDO_REG9 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-name = "vcc2v8_dvp";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc5v_midu: BOOST {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <5000000>;
-				regulator-max-microvolt = <5000000>;
-				regulator-name = "boost";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vbus: OTG_SWITCH {
-				regulator-min-microvolt = <5000000>;
-				regulator-max-microvolt = <5000000>;
-				regulator-name = "otg_switch";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-
-		charger {
-			monitored-battery = <&battery>;
-			rockchip,resistor-sense-micro-ohms = <10000>;
-			rockchip,sleep-enter-current-microamp = <300000>;
-			rockchip,sleep-filter-current-microamp = <100000>;
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	touchscreen@5d {
-		compatible = "goodix,gt911";
-		reg = <0x5d>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>;
-		AVDD28-supply = <&vcc3v3_pmu>;
-		VDDIO-supply = <&vcca1v8_pmu>;
-		irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&i2c2 {
-	clock-frequency = <400000>;
-	pinctrl-0 = <&i2c2m1_xfer>;
-	status = "okay";
-
-	vcm@c {
-		compatible = "dongwoon,dw9714";
-		reg = <0x0c>;
-		vcc-supply = <&vcc1v8_dvp>;
-	};
-
-	camera@36 {
-		compatible = "ovti,ov5648";
-		reg = <0x36>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>;
-
-		clocks = <&cru CLK_CIF_OUT>;
-		assigned-clocks = <&cru CLK_CIF_OUT>;
-		assigned-clock-rates = <24000000>;
-
-		avdd-supply = <&vcc2v8_dvp>;
-		dvdd-supply = <&vdd1v2_dvp>;
-		dovdd-supply = <&vcc1v8_dvp>;
-		powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
-		reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
-
-		port {
-			endpoint {
-				data-lanes = <1 2>;
-				remote-endpoint = <0>;
-				link-frequencies = /bits/ 64 <210000000 168000000>;
-			};
-		};
-	};
-};
-
-&i2c5 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	accelerometer@18 {
-		compatible = "silan,sc7a20";
-		reg = <0x18>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&gsensor_int_l>;
-		st,drdy-int-pin = <1>;
-		vdd-supply = <&vcc_1v8>;
-		vddio-supply = <&vcc_1v8>;
-		mount-matrix = "1", "0", "0",
-			       "0", "0", "1",
-			       "0", "1", "0";
-	};
-};
-
-&i2s0_8ch {
-	status = "okay";
-};
-
-&i2s1_8ch {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2s1m0_sclktx
-		     &i2s1m0_lrcktx
-		     &i2s1m0_sdi0
-		     &i2s1m0_sdo0>;
-	rockchip,trcm-sync-tx-only;
-	status = "okay";
-};
-
-&pcie2x1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_reset_h>;
-	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_minipcie>;
-	status = "okay";
-};
-
-&pinctrl {
-	camerab {
-		camerab_pdn_l: camerab-pdn-l {
-			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		camerab_rst_l: camerab-rst-l {
-			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	cameraf {
-		cameraf_pdn_l: cameraf-pdn-l {
-			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		cameraf_rst_l: cameraf-rst-l {
-			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	flash {
-		flash_led_en_h: flash-led-en-h {
-			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	fspi {
-		fspi_dual_io_pins: fspi-dual-io-pins {
-			rockchip,pins =
-				/* fspi_clk */
-				<1 RK_PD0 1 &pcfg_pull_none>,
-				/* fspi_cs0n */
-				<1 RK_PD3 1 &pcfg_pull_none>,
-				/* fspi_d0 */
-				<1 RK_PD1 1 &pcfg_pull_none>,
-				/* fspi_d1 */
-				<1 RK_PD2 1 &pcfg_pull_none>;
-		};
-	};
-
-	gsensor {
-		gsensor_int_l: gsensor-int-l {
-			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	kb {
-		kb_id_det: kb-id-det {
-			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	lcd {
-		lcd_pwren_h: lcd-pwren-h {
-			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pcie {
-		pcie_pwren_h: pcie-pwren-h {
-			rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		pcie_reset_h: pcie-reset-h {
-			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	sdmmc {
-		sdmmc_pwren_l: sdmmc-pwren-l {
-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	sound {
-		hp_det_l: hp-det-l {
-			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		spk_ctl: spk-ctl {
-			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	tp {
-		tp_int_l_pmuio2: tp-int-l-pmuio2 {
-			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-
-		tp_rst_l_pmuio2: tp-rst-l-pmuio2 {
-			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usb {
-		usbcc_int_l: usbcc-int-l {
-			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		usb_host_pwren1_h: usb-host-pwren1-h {
-			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		usb_host_pwren2_h: usb-host-pwren2-h {
-			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	wifi {
-		host_wake_wl: host-wake-wl {
-			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		wifi_wake_host_h: wifi-wake-host-h {
-			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio1-supply = <&vcc3v3_pmu>;
-	pmuio2-supply = <&vcca1v8_pmu>;
-	vccio1-supply = <&vccio_acodec>;
-	vccio2-supply = <&vcc_1v8>;
-	vccio3-supply = <&vccio_sd>;
-	vccio4-supply = <&vcc_1v8>;
-	vccio5-supply = <&vcc_1v8>;
-	vccio6-supply = <&vcc1v8_dvp>;
-	vccio7-supply = <&vcc_3v3>;
-	status = "okay";
-};
-
-&pwm4 {
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	no-sdio;
-	no-sd;
-	non-removable;
-	max-frequency = <200000000>;
-	mmc-hs200-1_8v;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8
-		     &emmc_clk
-		     &emmc_cmd
-		     &emmc_datastrobe
-		     &emmc_rstnout>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdmmc0 {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_bus4
-		     &sdmmc0_clk
-		     &sdmmc0_cmd
-		     &sdmmc0_det>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&sdmmc1 {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc1_bus4
-		     &sdmmc1_cmd
-		     &sdmmc1_clk>;
-	sd-uhs-sdr104;
-	vqmmc-supply = <&vcca1v8_pmu>;
-	status = "okay";
-};
-
-&sfc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&fspi_dual_io_pins>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <100000000>;
-		spi-rx-bus-width = <2>;
-		spi-tx-bus-width = <1>;
-	};
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <1>;
-	rockchip,hw-tshut-polarity = <0>;
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	status = "okay";
-};
-
-&usb_host1_xhci {
-	status = "okay";
-};
-
-&usb2phy0 {
-	status = "okay";
-};
-
-&usb2phy0_host {
-	phy-supply = <&vcc5v0_usb_host0>;
-	status = "okay";
-};
-
-&usb2phy0_otg {
-	status = "okay";
-};
-
-&usb2phy1 {
-	status = "okay";
-};
-
-&usb2phy1_otg {
-	phy-supply = <&vcc5v0_usb_host2>;
-	status = "okay";
-};
-
-&vop {
-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
-&vp0 {
-	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-		remote-endpoint = <&hdmi_in_vp0>;
-	};
-};
-
-&vp1 {
-	vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
-		reg = <ROCKCHIP_VOP2_EP_MIPI0>;
-		remote-endpoint = <&dsi0_in_vp1>;
-	};
-};
diff --git a/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
new file mode 100644
index 00000000000..8af2581163b
--- /dev/null
+++ b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&saradc {
+	bootph-pre-ram;
+};
+
+&usb_host0_xhci {
+	dr_mode = "otg";
+};
+
+&vcca_1v8 {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
new file mode 100644
index 00000000000..8af2581163b
--- /dev/null
+++ b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&saradc {
+	bootph-pre-ram;
+};
+
+&usb_host0_xhci {
+	dr_mode = "otg";
+};
+
+&vcca_1v8 {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
new file mode 100644
index 00000000000..f4124aa48fc
--- /dev/null
+++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sfc {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+/ {
+	leds {
+		led-0 {
+			default-state = "on";
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
index 5f4f14b3bda..5f4f14b3bda 100644
--- a/arch/arm/dts/rk3568-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 9d18f5d0b36..0da3d9c56b8 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -26,17 +26,12 @@
 };
 
 &sfc {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
 	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
 		bootph-pre-ram;
 		bootph-some-ram;
-		spi-max-frequency = <24000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <1>;
 	};
 };
+
+&usb_host0_ohci {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
new file mode 100644
index 00000000000..b1f324282ba
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sdhci {
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+};
+
+&sfc {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
diff --git a/arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi b/arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi
new file mode 100644
index 00000000000..2e60f2dce8f
--- /dev/null
+++ b/arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&sdhci {
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+};
diff --git a/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi
new file mode 100644
index 00000000000..1e5c2674e49
--- /dev/null
+++ b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim2_pins {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sfc {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+&vcc3v3_mkey {
+	regulator-always-on;
+};
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 8e318e624a8..4dd17ff408c 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -39,18 +39,6 @@
 	status = "okay";
 };
 
-&u2phy1 {
-	status = "okay";
-};
-
-&u2phy1_otg {
-	status = "okay";
-};
-
-&usbdp_phy1 {
-	status = "okay";
-};
-
 &usbdp_phy0 {
 	status = "okay";
 };
@@ -60,8 +48,3 @@
 	maximum-speed = "high-speed";
 	status = "okay";
 };
-
-&usb_host1_xhci {
-	dr_mode = "host";
-	status = "okay";
-};
diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/arch/arm/dts/rk3588-toybrick-x0.dts
deleted file mode 100644
index 9090c5c99f2..00000000000
--- a/arch/arm/dts/rk3588-toybrick-x0.dts
+++ /dev/null
@@ -1,688 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3588.dtsi"
-
-/ {
-	model = "Rockchip Toybrick TB-RK3588X Board";
-	compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588";
-
-	aliases {
-		mmc0 = &sdhci;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	adc-keys {
-		compatible = "adc-keys";
-		io-channels = <&saradc 1>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <100>;
-
-		button-vol-up {
-			label = "Volume Up";
-			linux,code = <KEY_VOLUMEUP>;
-			press-threshold-microvolt = <17000>;
-		};
-
-		button-vol-down {
-			label = "Volume Down";
-			linux,code = <KEY_VOLUMEDOWN>;
-			press-threshold-microvolt = <417000>;
-		};
-
-		button-menu {
-			label = "Menu";
-			linux,code = <KEY_MENU>;
-			press-threshold-microvolt = <890000>;
-		};
-
-		button-escape {
-			label = "Escape";
-			linux,code = <KEY_ESC>;
-			press-threshold-microvolt = <1235000>;
-		};
-	};
-
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		power-supply = <&vcc12v_dcin>;
-		pwms = <&pwm2 0 25000 0>;
-	};
-
-	pcie20_avdd0v85: pcie20-avdd0v85-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie20_avdd0v85";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <850000>;
-		regulator-max-microvolt = <850000>;
-		vin-supply = <&vdd_0v85_s0>;
-	};
-
-	pcie20_avdd1v8: pcie20-avdd1v8-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie20_avdd1v8";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&avcc_1v8_s0>;
-	};
-
-	pcie30_avdd0v75: pcie30-avdd0v75-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd0v75";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <750000>;
-		regulator-max-microvolt = <750000>;
-		vin-supply = <&avdd_0v75_s0>;
-	};
-
-	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "pcie30_avdd1v8";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&avcc_1v8_s0>;
-	};
-
-	vcc12v_dcin: vcc12v-dcin-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc12v_dcin";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc5v0_host: vcc5v0-host-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_host_en>;
-		regulator-name = "vcc5v0_host";
-		regulator-boot-on;
-		regulator-always-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usb>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usbdcin";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	vcc5v0_usb: vcc5v0-usb-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_usb";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc5v0_usbdcin>;
-	};
-
-	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_1v1_nldo_s3";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1100000>;
-		regulator-max-microvolt = <1100000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-};
-
-&combphy0_ps {
-	status = "okay";
-};
-
-&combphy2_psu {
-	status = "okay";
-};
-
-&cpu_b0 {
-	cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
-	cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
-	cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
-	cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l1 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l2 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&cpu_l3 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gmac0 {
-	clock_in_out = "output";
-	phy-handle = <&rgmii_phy>;
-	phy-mode = "rgmii-rxid";
-	pinctrl-0 = <&gmac0_miim
-		     &gmac0_tx_bus2
-		     &gmac0_rx_bus2
-		     &gmac0_rgmii_clk
-		     &gmac0_rgmii_bus>;
-	pinctrl-names = "default";
-	rx_delay = <0x00>;
-	tx_delay = <0x43>;
-	status = "okay";
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0m2_xfer>;
-	status = "okay";
-
-	vdd_cpu_big0_s0: regulator@42 {
-		compatible = "rockchip,rk8602";
-		reg = <0x42>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu_big0_s0";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <550000>;
-		regulator-max-microvolt = <1050000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	vdd_cpu_big1_s0: regulator@43 {
-		compatible = "rockchip,rk8603", "rockchip,rk8602";
-		reg = <0x43>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu_big1_s0";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <550000>;
-		regulator-max-microvolt = <1050000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-};
-
-&i2c2 {
-	status = "okay";
-
-	hym8563: rtc@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
-		#clock-cells = <0>;
-		clock-output-names = "hym8563";
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&hym8563_int>;
-		wakeup-source;
-	};
-};
-
-&mdio0 {
-	rgmii_phy: ethernet-phy@1 {
-		/* RTL8211F */
-		compatible = "ethernet-phy-id001c.c916";
-		reg = <0x1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&rtl8211f_rst>;
-		reset-assert-us = <20000>;
-		reset-deassert-us = <100000>;
-		reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pinctrl {
-	rtl8211f {
-		rtl8211f_rst: rtl8211f-rst {
-			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-	};
-
-	hym8563 {
-		hym8563_int: hym8563-int {
-			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		vcc5v0_host_en: vcc5v0-host-en {
-			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pwm2 {
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcc_1v8_s0>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
-	no-sdio;
-	no-sd;
-	non-removable;
-	status = "okay";
-};
-
-&spi2 {
-	assigned-clocks = <&cru CLK_SPI2>;
-	assigned-clock-rates = <200000000>;
-	num-cs = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-	status = "okay";
-
-	pmic@0 {
-		compatible = "rockchip,rk806";
-		reg = <0x0>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-		spi-max-frequency = <1000000>;
-		system-power-controller;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc5v0_sys>;
-		vcc6-supply = <&vcc5v0_sys>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc5v0_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-		vcc10-supply = <&vcc5v0_sys>;
-		vcc11-supply = <&vcc_2v0_pldo_s3>;
-		vcc12-supply = <&vcc5v0_sys>;
-		vcc13-supply = <&vcc_1v1_nldo_s3>;
-		vcc14-supply = <&vcc_1v1_nldo_s3>;
-		vcca-supply = <&vcc5v0_sys>;
-
-		rk806_dvs1_null: dvs1-null-pins {
-			pins = "gpio_pwrctrl1";
-			function = "pin_fun0";
-		};
-
-		rk806_dvs2_null: dvs2-null-pins {
-			pins = "gpio_pwrctrl2";
-			function = "pin_fun0";
-		};
-
-		rk806_dvs3_null: dvs3-null-pins {
-			pins = "gpio_pwrctrl3";
-			function = "pin_fun0";
-		};
-
-		regulators {
-			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
-				regulator-name = "vdd_gpu_s0";
-				regulator-boot-on;
-				regulator-enable-ramp-delay = <400>;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
-				regulator-name = "vdd_cpu_lit_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_log_s0: dcdc-reg3 {
-				regulator-name = "vdd_log_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <675000>;
-				regulator-max-microvolt = <750000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <750000>;
-				};
-			};
-
-			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
-				regulator-name = "vdd_vdenc_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-init-microvolt = <750000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_ddr_s0: dcdc-reg5 {
-				regulator-name = "vdd_ddr_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <675000>;
-				regulator-max-microvolt = <900000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <850000>;
-				};
-			};
-
-			vdd2_ddr_s3: dcdc-reg6 {
-				regulator-name = "vdd2_ddr_s3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_2v0_pldo_s3: dcdc-reg7 {
-				regulator-name = "vdd_2v0_pldo_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2000000>;
-				regulator-max-microvolt = <2000000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2000000>;
-				};
-			};
-
-			vcc_3v3_s3: dcdc-reg8 {
-				regulator-name = "vcc_3v3_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vddq_ddr_s0: dcdc-reg9 {
-				regulator-name = "vddq_ddr_s0";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8_s3: dcdc-reg10 {
-				regulator-name = "vcc_1v8_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			avcc_1v8_s0: pldo-reg1 {
-				regulator-name = "avcc_1v8_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8_s0: pldo-reg2 {
-				regulator-name = "vcc_1v8_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			avdd_1v2_s0: pldo-reg3 {
-				regulator-name = "avdd_1v2_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3_s0: pldo-reg4 {
-				regulator-name = "vcc_3v3_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd_s0: pldo-reg5 {
-				regulator-name = "vccio_sd_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			pldo6_s3: pldo-reg6 {
-				regulator-name = "pldo6_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd_0v75_s3: nldo-reg1 {
-				regulator-name = "vdd_0v75_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <750000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <750000>;
-				};
-			};
-
-			vdd_ddr_pll_s0: nldo-reg2 {
-				regulator-name = "vdd_ddr_pll_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <850000>;
-				};
-			};
-
-			avdd_0v75_s0: nldo-reg3 {
-				regulator-name = "avdd_0v75_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <837500>;
-				regulator-max-microvolt = <837500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_0v85_s0: nldo-reg4 {
-				regulator-name = "vdd_0v85_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_0v75_s0: nldo-reg5 {
-				regulator-name = "vdd_0v75_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <750000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-&u2phy2 {
-	status = "okay";
-};
-
-&u2phy2_host {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&u2phy3 {
-	status = "okay";
-};
-
-&u2phy3_host {
-	phy-supply = <&vcc5v0_host>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-0 = <&uart2m0_xfer>;
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi
deleted file mode 100644
index 5c645437b50..00000000000
--- a/arch/arm/dts/rockchip-pinconf.dtsi
+++ /dev/null
@@ -1,344 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- */
-
-&pinctrl {
-	/omit-if-no-ref/
-	pcfg_pull_up: pcfg-pull-up {
-		bias-pull-up;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down: pcfg-pull-down {
-		bias-pull-down;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none: pcfg-pull-none {
-		bias-disable;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
-		bias-disable;
-		drive-strength = <0>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
-		bias-disable;
-		drive-strength = <1>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
-		bias-disable;
-		drive-strength = <2>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
-		bias-disable;
-		drive-strength = <3>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
-		bias-disable;
-		drive-strength = <4>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
-		bias-disable;
-		drive-strength = <5>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
-		bias-disable;
-		drive-strength = <6>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
-		bias-disable;
-		drive-strength = <7>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
-		bias-disable;
-		drive-strength = <8>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
-		bias-disable;
-		drive-strength = <9>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
-		bias-disable;
-		drive-strength = <10>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
-		bias-disable;
-		drive-strength = <11>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
-		bias-disable;
-		drive-strength = <12>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
-		bias-disable;
-		drive-strength = <13>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
-		bias-disable;
-		drive-strength = <14>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
-		bias-disable;
-		drive-strength = <15>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
-		bias-pull-up;
-		drive-strength = <0>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
-		bias-pull-up;
-		drive-strength = <1>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
-		bias-pull-up;
-		drive-strength = <2>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
-		bias-pull-up;
-		drive-strength = <3>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
-		bias-pull-up;
-		drive-strength = <4>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
-		bias-pull-up;
-		drive-strength = <5>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
-		bias-pull-up;
-		drive-strength = <6>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
-		bias-pull-up;
-		drive-strength = <7>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
-		bias-pull-up;
-		drive-strength = <8>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
-		bias-pull-up;
-		drive-strength = <9>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
-		bias-pull-up;
-		drive-strength = <10>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
-		bias-pull-up;
-		drive-strength = <11>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
-		bias-pull-up;
-		drive-strength = <12>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
-		bias-pull-up;
-		drive-strength = <13>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
-		bias-pull-up;
-		drive-strength = <14>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
-		bias-pull-up;
-		drive-strength = <15>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
-		bias-pull-down;
-		drive-strength = <0>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
-		bias-pull-down;
-		drive-strength = <1>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
-		bias-pull-down;
-		drive-strength = <2>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
-		bias-pull-down;
-		drive-strength = <3>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
-		bias-pull-down;
-		drive-strength = <4>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
-		bias-pull-down;
-		drive-strength = <5>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
-		bias-pull-down;
-		drive-strength = <6>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
-		bias-pull-down;
-		drive-strength = <7>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
-		bias-pull-down;
-		drive-strength = <8>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
-		bias-pull-down;
-		drive-strength = <9>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
-		bias-pull-down;
-		drive-strength = <10>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
-		bias-pull-down;
-		drive-strength = <11>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
-		bias-pull-down;
-		drive-strength = <12>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
-		bias-pull-down;
-		drive-strength = <13>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
-		bias-pull-down;
-		drive-strength = <14>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
-		bias-pull-down;
-		drive-strength = <15>;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_up_smt: pcfg-pull-up-smt {
-		bias-pull-up;
-		input-schmitt-enable;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_down_smt: pcfg-pull-down-smt {
-		bias-pull-down;
-		input-schmitt-enable;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_smt: pcfg-pull-none-smt {
-		bias-disable;
-		input-schmitt-enable;
-	};
-
-	/omit-if-no-ref/
-	pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
-		bias-disable;
-		drive-strength = <0>;
-		input-schmitt-enable;
-	};
-
-	/omit-if-no-ref/
-	pcfg_output_high: pcfg-output-high {
-		output-high;
-	};
-
-	/omit-if-no-ref/
-	pcfg_output_low: pcfg-output-low {
-		output-low;
-	};
-};
diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
index 2d7e9711015..e77189eef6c 100644
--- a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
@@ -16,4 +16,7 @@ U_BOOT_DRIVER(syscon_rk3308) = {
 	.name = "rk3308_syscon",
 	.id = UCLASS_SYSCON,
 	.of_match = rk3308_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind = dm_scan_fdt_dev,
+#endif
 };
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index 014ebf9f0ba..899cf909fbb 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -32,6 +32,16 @@ config TARGET_QUARTZ64_RK3566
 	help
 	  Pine64 Quartz64 single board computer with a RK3566 SoC.
 
+config TARGET_RADXA_ZERO_3_RK3566
+	bool "Radxa ZERO 3W/3E"
+	help
+	  Radxa ZERO 3W/3E single board computers with a RK3566 SoC.
+
+config TARGET_ORANGEPI_3B_RK3566
+	bool "Xunlong Orange Pi 3B"
+	help
+	  Xunlong Orange Pi 3B single board computer with a RK3566 SoC.
+
 endchoice
 
 config ROCKCHIP_BOOT_MODE_REG
@@ -54,5 +64,7 @@ source "board/anbernic/rgxx3_rk3566/Kconfig"
 source "board/hardkernel/odroid_m1/Kconfig"
 source "board/pine64/quartz64_rk3566/Kconfig"
 source "board/powkiddy/x55/Kconfig"
+source "board/radxa/zero3-rk3566/Kconfig"
+source "board/xunlong/orangepi-3b-rk3566/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index e751d64e1a1..a76a470cc98 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -6,6 +6,29 @@ config TARGET_EVB_RK3588
 	help
 	  RK3588 EVB is a evaluation board for Rockchp RK3588.
 
+config TARGET_CM3588_NAS_RK3588
+	bool "FriendlyElec CM3588 NAS"
+	select BOARD_LATE_INIT
+	help
+	  The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based
+	  on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board.
+
+	  Hardware features:
+	  - Rockchip RK3588 SoC
+	  - 4GB/8GB/16GB LPDDR4x RAM
+	  - 0GB/64GB HS400 eMMC
+	  - MicroSD card slot
+	  - 1x RTL8125B 2.5G Ethernet
+	  - 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs
+	  - 2x USB 3.0 (USB 3.1 Gen1) Type-A, 1x USB 2.0 Type-A
+	  - 1x USB 3.0 Type-C with DP AltMode support
+	  - 2x HDMI 2.1 out, 1x HDMI in
+	  - MIPI-CSI Connector, MIPI-DSI Connector
+	  - 40-pin GPIO header
+	  - 4 buttons: power, reset, recovery, MASK, user button
+	  - 3.5mm Headphone out, 2.0mm PH-2A Mic in
+	  - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
+
 config TARGET_JAGUAR_RK3588
 	bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)"
 	select BOARD_LATE_INIT
@@ -185,6 +208,34 @@ config TARGET_ROCK5B_RK3588
 	  USB PD over USB Type-C
 	  Size: 100mm x 72mm (Pico-ITX form factor)
 
+config TARGET_ROCK_5_ITX_RK3588
+	bool "Radxa ROCK-5-ITX RK3588 board"
+	select BOARD_LATE_INIT
+	help
+	  Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board
+	  Computer) by Radxa in the ITX formfactor.
+
+	  There are variants depending on the DRAM size : from 4G up to 32G.
+
+	  Specification:
+
+	  Rockchip Rk3588 SoC
+	  4x ARM Cortex-A76, 4x ARM Cortex-A55
+	  4/8/16/24/32GB memory LPDDR5
+	  Mali G610MC4 GPU
+	  2x MIPI CSI 2 multiple lanes connector
+	  eMMC
+	  uSD slot (up to 128GB)
+	  M.2 M-key and M.2 E-key connector
+	  4x SATA
+	  2x USB 2.0 + 4x USB 3.0 Type-A, 2x USB 2.0 Panel, 1x USB 3.0 Type-C
+	  2x HDMI 2.1 output, 1x HDMI input
+	  DP via Type-C
+	  2x DSI via PCB connector
+	  2x 2.5 Gbps Ethernet port
+	  Front-panel connectors for audio and case-power, -leds
+	  Powered by either 12V, ATX power-supply or PoE
+
 config TARGET_SIGE7_RK3588
 	bool "ArmSoM Sige7 RK3588 board"
 	select BOARD_LATE_INIT
@@ -311,6 +362,7 @@ config TEXT_BASE
 
 source "board/armsom/sige7-rk3588/Kconfig"
 source "board/edgeble/neural-compute-module-6/Kconfig"
+source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
 source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
 source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
 source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
@@ -319,6 +371,7 @@ source "board/pine64/quartzpro64-rk3588/Kconfig"
 source "board/turing/turing-rk1-rk3588/Kconfig"
 source "board/radxa/rock5a-rk3588s/Kconfig"
 source "board/radxa/rock5b-rk3588/Kconfig"
+source "board/radxa/rock-5-itx-rk3588/Kconfig"
 source "board/rockchip/evb_rk3588/Kconfig"
 source "board/rockchip/toybrick_rk3588/Kconfig"
 source "board/theobroma-systems/jaguar_rk3588/Kconfig"