Merge branch 'next'

Merge the outstanding changes from the 'next' branch to master.

130 files changed, 1706 insertions, 3993 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 625d2e995d2..4965a6d05db 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -68,10 +68,10 @@ config INIT_SP_RELATIVE
 	  SYS_INIT_SP_BSS_OFFSET.
 
 config SYS_INIT_SP_BSS_OFFSET
-	int "Early stack offset from the .bss base address"
+	hex "Early stack offset from the .bss base address"
 	depends on ARM64
 	depends on INIT_SP_RELATIVE
-	default 524288
+	default 0x80000
 	help
 	  This option's value is the offset added to &_bss_start in order to
 	  calculate the stack pointer. This offset should be large enough so
@@ -1418,6 +1418,8 @@ config ARCH_VEXPRESS64
 	select MTD_NOR_FLASH if MTD
 	select FLASH_CFI_DRIVER if MTD
 	select ENV_IS_IN_FLASH if MTD
+	select SYSRESET
+	select SYSRESET_PSCI if ARM_PSCI_FW
 	imply DISTRO_DEFAULTS
 
 config TARGET_CORSTONE1000
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 318a71f24b1..e3415cfd1d1 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,6 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC)))
 obj-y += s5p-common/
 endif
 
-obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
diff --git a/arch/arm/cpu/armv7/bcm235xx/Makefile b/arch/arm/cpu/armv7/bcm235xx/Makefile
deleted file mode 100644
index 3d09126cabe..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Broadcom Corporation.
-
-obj-y	+= clk-core.o
-obj-y	+= clk-bcm235xx.o
-obj-y	+= clk-sdio.o
-obj-y	+= clk-bsc.o
-obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
-obj-y	+= clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
deleted file mode 100644
index 7f73f893458..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
+++ /dev/null
@@ -1,567 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-/*
- *
- * bcm235xx-specific clock tables
- *
- */
-
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sysmap.h>
-#include <asm/kona-common/clk.h>
-#include "clk-core.h"
-
-#define CLOCK_1K		1000
-#define CLOCK_1M		(CLOCK_1K * 1000)
-
-/* declare a reference clock */
-#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
-static struct refclk clk_name = { \
-	.clk	=	{ \
-		.name	=	#clk_name, \
-		.parent =	clk_parent, \
-		.rate	=	clk_rate, \
-		.div	=	clk_div, \
-		.ops	=	&ref_clk_ops, \
-	}, \
-}
-
-/*
- * Reference clocks
- */
-
-/* Declare a list of reference clocks */
-DECLARE_REF_CLK(ref_crystal,	0,		26  * CLOCK_1M,	1);
-DECLARE_REF_CLK(var_96m,	0,		96  * CLOCK_1M,	1);
-DECLARE_REF_CLK(ref_96m,	0,		96  * CLOCK_1M,	1);
-DECLARE_REF_CLK(ref_312m,	0,		312 * CLOCK_1M,	0);
-DECLARE_REF_CLK(ref_104m,	&ref_312m.clk,	104 * CLOCK_1M,	3);
-DECLARE_REF_CLK(ref_52m,	&ref_104m.clk,	52  * CLOCK_1M,	2);
-DECLARE_REF_CLK(ref_13m,	&ref_52m.clk,	13  * CLOCK_1M,	4);
-DECLARE_REF_CLK(var_312m,	0,		312 * CLOCK_1M,	0);
-DECLARE_REF_CLK(var_104m,	&var_312m.clk,	104 * CLOCK_1M,	3);
-DECLARE_REF_CLK(var_52m,	&var_104m.clk,	52  * CLOCK_1M,	2);
-DECLARE_REF_CLK(var_13m,	&var_52m.clk,	13  * CLOCK_1M,	4);
-
-struct refclk_lkup {
-	struct refclk *procclk;
-	const char *name;
-};
-
-/* Lookup table for string to clk tranlation */
-#define MKSTR(x) {&x, #x}
-static struct refclk_lkup refclk_str_tbl[] = {
-	MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
-	MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
-	MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
-	MKSTR(var_52m), MKSTR(var_13m),
-};
-
-int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
-
-/* convert ref clock string to clock structure pointer */
-struct refclk *refclk_str_to_clk(const char *name)
-{
-	int i;
-	struct refclk_lkup *tblp = refclk_str_tbl;
-	for (i = 0; i < refclk_entries; i++, tblp++) {
-		if (!(strcmp(name, tblp->name)))
-			return tblp->procclk;
-	}
-	return NULL;
-}
-
-/* frequency tables indexed by freq_id */
-unsigned long master_axi_freq_tbl[8] = {
-	26 * CLOCK_1M,
-	52 * CLOCK_1M,
-	104 * CLOCK_1M,
-	156 * CLOCK_1M,
-	156 * CLOCK_1M,
-	208 * CLOCK_1M,
-	312 * CLOCK_1M,
-	312 * CLOCK_1M
-};
-
-unsigned long master_ahb_freq_tbl[8] = {
-	26 * CLOCK_1M,
-	52 * CLOCK_1M,
-	52 * CLOCK_1M,
-	52 * CLOCK_1M,
-	78 * CLOCK_1M,
-	104 * CLOCK_1M,
-	104 * CLOCK_1M,
-	156 * CLOCK_1M
-};
-
-unsigned long slave_axi_freq_tbl[8] = {
-	26 * CLOCK_1M,
-	52 * CLOCK_1M,
-	78 * CLOCK_1M,
-	104 * CLOCK_1M,
-	156 * CLOCK_1M,
-	156 * CLOCK_1M
-};
-
-unsigned long slave_apb_freq_tbl[8] = {
-	26 * CLOCK_1M,
-	26 * CLOCK_1M,
-	39 * CLOCK_1M,
-	52 * CLOCK_1M,
-	52 * CLOCK_1M,
-	78 * CLOCK_1M
-};
-
-unsigned long esub_freq_tbl[8] = {
-	78 * CLOCK_1M,
-	156 * CLOCK_1M,
-	156 * CLOCK_1M,
-	156 * CLOCK_1M,
-	208 * CLOCK_1M,
-	208 * CLOCK_1M,
-	208 * CLOCK_1M
-};
-
-static struct bus_clk_data bsc1_apb_data = {
-	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
-};
-
-static struct bus_clk_data bsc2_apb_data = {
-	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
-};
-
-static struct bus_clk_data bsc3_apb_data = {
-	.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
-};
-
-/* * Master CCU clocks */
-static struct peri_clk_data sdio1_data = {
-	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_52m",
-				 "ref_52m",
-				 "var_96m",
-				 "ref_96m"),
-	.sel		= SELECTOR(0x0a28, 0, 3),
-	.div		= DIVIDER(0x0a28, 4, 14),
-	.trig		= TRIGGER(0x0afc, 9),
-};
-
-static struct peri_clk_data sdio2_data = {
-	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_52m",
-				 "ref_52m",
-				 "var_96m",
-				 "ref_96m"),
-	.sel		= SELECTOR(0x0a2c, 0, 3),
-	.div		= DIVIDER(0x0a2c, 4, 14),
-	.trig		= TRIGGER(0x0afc, 10),
-};
-
-static struct peri_clk_data sdio3_data = {
-	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_52m",
-				 "ref_52m",
-				 "var_96m",
-				 "ref_96m"),
-	.sel		= SELECTOR(0x0a34, 0, 3),
-	.div		= DIVIDER(0x0a34, 4, 14),
-	.trig		= TRIGGER(0x0afc, 12),
-};
-
-static struct peri_clk_data sdio4_data = {
-	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_52m",
-				 "ref_52m",
-				 "var_96m",
-				 "ref_96m"),
-	.sel		= SELECTOR(0x0a30, 0, 3),
-	.div		= DIVIDER(0x0a30, 4, 14),
-	.trig		= TRIGGER(0x0afc, 11),
-};
-
-static struct peri_clk_data sdio1_sleep_data = {
-	.clocks		= CLOCKS("ref_32k"),
-	.gate		= SW_ONLY_GATE(0x0358, 20, 4),
-};
-
-static struct peri_clk_data sdio2_sleep_data = {
-	.clocks		= CLOCKS("ref_32k"),
-	.gate		= SW_ONLY_GATE(0x035c, 20, 4),
-};
-
-static struct peri_clk_data sdio3_sleep_data = {
-	.clocks		= CLOCKS("ref_32k"),
-	.gate		= SW_ONLY_GATE(0x0364, 20, 4),
-};
-
-static struct peri_clk_data sdio4_sleep_data = {
-	.clocks		= CLOCKS("ref_32k"),
-	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
-};
-
-static struct bus_clk_data usb_otg_ahb_data = {
-	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
-};
-
-static struct bus_clk_data sdio1_ahb_data = {
-	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
-};
-
-static struct bus_clk_data sdio2_ahb_data = {
-	.gate		= HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
-};
-
-static struct bus_clk_data sdio3_ahb_data = {
-	.gate		= HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
-};
-
-static struct bus_clk_data sdio4_ahb_data = {
-	.gate		= HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
-};
-
-/* * Slave CCU clocks */
-static struct peri_clk_data bsc1_data = {
-	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_104m",
-				 "ref_104m",
-				 "var_13m",
-				 "ref_13m"),
-	.sel		= SELECTOR(0x0a64, 0, 3),
-	.trig		= TRIGGER(0x0afc, 23),
-};
-
-static struct peri_clk_data bsc2_data = {
-	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_104m",
-				 "ref_104m",
-				 "var_13m",
-				 "ref_13m"),
-	.sel		= SELECTOR(0x0a68, 0, 3),
-	.trig		= TRIGGER(0x0afc, 24),
-};
-
-static struct peri_clk_data bsc3_data = {
-	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
-	.clocks		= CLOCKS("ref_crystal",
-				 "var_104m",
-				 "ref_104m",
-				 "var_13m",
-				 "ref_13m"),
-	.sel		= SELECTOR(0x0a84, 0, 3),
-	.trig		= TRIGGER(0x0b00, 2),
-};
-
-/*
- * CCU clocks
- */
-
-static struct ccu_clock kpm_ccu_clk = {
-	.clk = {
-		.name = "kpm_ccu_clk",
-		.ops = &ccu_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.num_policy_masks = 1,
-	.policy_freq_offset = 0x00000008,
-	.freq_bit_shift = 8,
-	.policy_ctl_offset = 0x0000000c,
-	.policy0_mask_offset = 0x00000010,
-	.policy1_mask_offset = 0x00000014,
-	.policy2_mask_offset = 0x00000018,
-	.policy3_mask_offset = 0x0000001c,
-	.lvm_en_offset = 0x00000034,
-	.freq_id = 2,
-	.freq_tbl = master_axi_freq_tbl,
-};
-
-static struct ccu_clock kps_ccu_clk = {
-	.clk = {
-		.name = "kps_ccu_clk",
-		.ops = &ccu_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-	},
-	.num_policy_masks = 1,
-	.policy_freq_offset = 0x00000008,
-	.freq_bit_shift = 8,
-	.policy_ctl_offset = 0x0000000c,
-	.policy0_mask_offset = 0x00000010,
-	.policy1_mask_offset = 0x00000014,
-	.policy2_mask_offset = 0x00000018,
-	.policy3_mask_offset = 0x0000001c,
-	.lvm_en_offset = 0x00000034,
-	.freq_id = 2,
-	.freq_tbl = slave_axi_freq_tbl,
-};
-
-#ifdef CONFIG_BCM_SF2_ETH
-static struct ccu_clock esub_ccu_clk = {
-	.clk = {
-		.name = "esub_ccu_clk",
-		.ops = &ccu_clk_ops,
-		.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
-	},
-	.num_policy_masks = 1,
-	.policy_freq_offset = 0x00000008,
-	.freq_bit_shift = 8,
-	.policy_ctl_offset = 0x0000000c,
-	.policy0_mask_offset = 0x00000010,
-	.policy1_mask_offset = 0x00000014,
-	.policy2_mask_offset = 0x00000018,
-	.policy3_mask_offset = 0x0000001c,
-	.lvm_en_offset = 0x00000034,
-	.freq_id = 2,
-	.freq_tbl = esub_freq_tbl,
-};
-#endif
-
-/*
- * Bus clocks
- */
-
-/* KPM bus clocks */
-static struct bus_clock usb_otg_ahb_clk = {
-	.clk = {
-		.name = "usb_otg_ahb_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.freq_tbl = master_ahb_freq_tbl,
-	.data = &usb_otg_ahb_data,
-};
-
-static struct bus_clock sdio1_ahb_clk = {
-	.clk = {
-		.name = "sdio1_ahb_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.freq_tbl = master_ahb_freq_tbl,
-	.data = &sdio1_ahb_data,
-};
-
-static struct bus_clock sdio2_ahb_clk = {
-	.clk = {
-		.name = "sdio2_ahb_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.freq_tbl = master_ahb_freq_tbl,
-	.data = &sdio2_ahb_data,
-};
-
-static struct bus_clock sdio3_ahb_clk = {
-	.clk = {
-		.name = "sdio3_ahb_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.freq_tbl = master_ahb_freq_tbl,
-	.data = &sdio3_ahb_data,
-};
-
-static struct bus_clock sdio4_ahb_clk = {
-	.clk = {
-		.name = "sdio4_ahb_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.freq_tbl = master_ahb_freq_tbl,
-	.data = &sdio4_ahb_data,
-};
-
-static struct bus_clock bsc1_apb_clk = {
-	.clk = {
-		.name = "bsc1_apb_clk",
-		.parent = &kps_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-	},
-	.freq_tbl = slave_apb_freq_tbl,
-	.data = &bsc1_apb_data,
-};
-
-static struct bus_clock bsc2_apb_clk = {
-	.clk = {
-		.name = "bsc2_apb_clk",
-		.parent = &kps_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-		},
-	.freq_tbl = slave_apb_freq_tbl,
-	.data = &bsc2_apb_data,
-};
-
-static struct bus_clock bsc3_apb_clk = {
-	.clk = {
-		.name = "bsc3_apb_clk",
-		.parent = &kps_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-		},
-	.freq_tbl = slave_apb_freq_tbl,
-	.data = &bsc3_apb_data,
-};
-
-/* KPM peripheral */
-static struct peri_clock sdio1_clk = {
-	.clk = {
-		.name = "sdio1_clk",
-		.parent = &ref_52m.clk,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio1_data,
-};
-
-static struct peri_clock sdio2_clk = {
-	.clk = {
-		.name = "sdio2_clk",
-		.parent = &ref_52m.clk,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio2_data,
-};
-
-static struct peri_clock sdio3_clk = {
-	.clk = {
-		.name = "sdio3_clk",
-		.parent = &ref_52m.clk,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio3_data,
-};
-
-static struct peri_clock sdio4_clk = {
-	.clk = {
-		.name = "sdio4_clk",
-		.parent = &ref_52m.clk,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio4_data,
-};
-
-static struct peri_clock sdio1_sleep_clk = {
-	.clk = {
-		.name = "sdio1_sleep_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio1_sleep_data,
-};
-
-static struct peri_clock sdio2_sleep_clk = {
-	.clk = {
-		.name = "sdio2_sleep_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio2_sleep_data,
-};
-
-static struct peri_clock sdio3_sleep_clk = {
-	.clk = {
-		.name = "sdio3_sleep_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio3_sleep_data,
-};
-
-static struct peri_clock sdio4_sleep_clk = {
-	.clk = {
-		.name = "sdio4_sleep_clk",
-		.parent = &kpm_ccu_clk.clk,
-		.ops = &bus_clk_ops,
-		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
-	},
-	.data = &sdio4_sleep_data,
-};
-
-/* KPS peripheral clock */
-static struct peri_clock bsc1_clk = {
-	.clk = {
-		.name = "bsc1_clk",
-		.parent = &ref_13m.clk,
-		.rate = 13 * CLOCK_1M,
-		.div = 1,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-	},
-	.data = &bsc1_data,
-};
-
-static struct peri_clock bsc2_clk = {
-	.clk = {
-		.name = "bsc2_clk",
-		.parent = &ref_13m.clk,
-		.rate = 13 * CLOCK_1M,
-		.div = 1,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-	},
-	.data = &bsc2_data,
-};
-
-static struct peri_clock bsc3_clk = {
-	.clk = {
-		.name = "bsc3_clk",
-		.parent = &ref_13m.clk,
-		.rate = 13 * CLOCK_1M,
-		.div = 1,
-		.ops = &peri_clk_ops,
-		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
-	},
-	.data = &bsc3_data,
-};
-
-/* public table for registering clocks */
-struct clk_lookup arch_clk_tbl[] = {
-	/* Peripheral clocks */
-	CLK_LK(sdio1),
-	CLK_LK(sdio2),
-	CLK_LK(sdio3),
-	CLK_LK(sdio4),
-	CLK_LK(sdio1_sleep),
-	CLK_LK(sdio2_sleep),
-	CLK_LK(sdio3_sleep),
-	CLK_LK(sdio4_sleep),
-	CLK_LK(bsc1),
-	CLK_LK(bsc2),
-	CLK_LK(bsc3),
-	/* Bus clocks */
-	CLK_LK(usb_otg_ahb),
-	CLK_LK(sdio1_ahb),
-	CLK_LK(sdio2_ahb),
-	CLK_LK(sdio3_ahb),
-	CLK_LK(sdio4_ahb),
-	CLK_LK(bsc1_apb),
-	CLK_LK(bsc2_apb),
-	CLK_LK(bsc3_apb),
-#ifdef CONFIG_BCM_SF2_ETH
-	CLK_LK(esub_ccu),
-#endif
-};
-
-/* public array size */
-unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
deleted file mode 100644
index 55dcc2fd78c..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sysmap.h>
-#include <asm/kona-common/clk.h>
-#include "clk-core.h"
-
-/* Enable appropriate clocks for a BSC/I2C port */
-int clk_bsc_enable(void *base)
-{
-	int ret;
-	char *bscstr, *apbstr;
-
-	switch ((u32) base) {
-	case PMU_BSC_BASE_ADDR:
-		/* PMU clock is always enabled */
-		return 0;
-	case BSC1_BASE_ADDR:
-		bscstr = "bsc1_clk";
-		apbstr = "bsc1_apb_clk";
-		break;
-	case BSC2_BASE_ADDR:
-		bscstr = "bsc2_clk";
-		apbstr = "bsc2_apb_clk";
-		break;
-	case BSC3_BASE_ADDR:
-		bscstr = "bsc3_clk";
-		apbstr = "bsc3_apb_clk";
-		break;
-	default:
-		printf("%s: base 0x%p not found\n", __func__, base);
-		return -EINVAL;
-	}
-
-	/* Note that the bus clock must be enabled first */
-
-	ret = clk_get_and_enable(apbstr);
-	if (ret)
-		return ret;
-
-	ret = clk_get_and_enable(bscstr);
-	if (ret)
-		return ret;
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
deleted file mode 100644
index fa8af1b6941..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c
+++ /dev/null
@@ -1,512 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-/*
- *
- * bcm235xx architecture clock framework
- *
- */
-
-#include <log.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <bitfield.h>
-#include <asm/arch/sysmap.h>
-#include <asm/kona-common/clk.h>
-#include "clk-core.h"
-
-#define CLK_WR_ACCESS_PASSWORD	0x00a5a501
-#define WR_ACCESS_OFFSET	0	/* common to all clock blocks */
-#define POLICY_CTL_GO		1	/* Load and refresh policy masks */
-#define POLICY_CTL_GO_ATL	4	/* Active Load */
-
-/* Helper function */
-int clk_get_and_enable(char *clkstr)
-{
-	int ret = 0;
-	struct clk *c;
-
-	debug("%s: %s\n", __func__, clkstr);
-
-	c = clk_get(clkstr);
-	if (c) {
-		ret = clk_enable(c);
-		if (ret)
-			return ret;
-	} else {
-		printf("%s: Couldn't find %s\n", __func__, clkstr);
-		return -EINVAL;
-	}
-	return ret;
-}
-
-/*
- * Poll a register in a CCU's address space, returning when the
- * specified bit in that register's value is set (or clear). Delay
- * a microsecond after each read of the register. Returns true if
- * successful, or false if we gave up trying.
- *
- * Caller must ensure the CCU lock is held.
- */
-#define CLK_GATE_DELAY_USEC 2000
-static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
-{
-	unsigned int tries;
-	u32 bit_mask = 1 << bit;
-
-	for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
-		u32 val;
-		bool bit_val;
-
-		val = readl(base + offset);
-		bit_val = (val & bit_mask) ? 1 : 0;
-		if (bit_val == want)
-			return 0;	/* success */
-		udelay(1);
-	}
-
-	debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
-	      __func__, base + offset, bit, want);
-
-	return -ETIMEDOUT;
-}
-
-/* Enable a peripheral clock */
-static int peri_clk_enable(struct clk *c, int enable)
-{
-	int ret = 0;
-	u32 reg;
-	struct peri_clock *peri_clk = to_peri_clk(c);
-	struct peri_clk_data *cd = peri_clk->data;
-	struct bcm_clk_gate *gate = &cd->gate;
-	void *base = (void *)c->ccu_clk_mgr_base;
-
-	debug("%s: %s\n", __func__, c->name);
-
-	clk_get_rate(c);	/* Make sure rate and sel are filled in */
-
-	/* enable access */
-	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
-
-	if (enable) {
-		debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
-		      __func__, c->name, c->rate, c->div, c->sel,
-		      c->parent->rate);
-
-		/*
-		 * clkgate - only software controllable gates are
-		 * supported by u-boot which includes all clocks
-		 * that matter. This avoids bringing in a lot of extra
-		 * complexity as done in the kernel framework.
-		 */
-		if (gate_exists(gate)) {
-			reg = readl(base + cd->gate.offset);
-			reg |= (1 << cd->gate.en_bit);
-			writel(reg, base + cd->gate.offset);
-		}
-
-		/* div and pll select */
-		if (divider_exists(&cd->div)) {
-			reg = readl(base + cd->div.offset);
-			bitfield_replace(reg, cd->div.shift, cd->div.width,
-					 c->div - 1);
-			writel(reg, base + cd->div.offset);
-		}
-
-		/* frequency selector */
-		if (selector_exists(&cd->sel)) {
-			reg = readl(base + cd->sel.offset);
-			bitfield_replace(reg, cd->sel.shift, cd->sel.width,
-					 c->sel);
-			writel(reg, base + cd->sel.offset);
-		}
-
-		/* trigger */
-		if (trigger_exists(&cd->trig)) {
-			writel((1 << cd->trig.bit), base + cd->trig.offset);
-
-			/* wait for trigger status bit to go to 0 */
-			ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
-			if (ret)
-				return ret;
-		}
-
-		/* wait for running (status_bit = 1) */
-		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
-		if (ret)
-			return ret;
-	} else {
-		debug("%s disable clock %s\n", __func__, c->name);
-
-		/* clkgate */
-		reg = readl(base + cd->gate.offset);
-		reg &= ~(1 << cd->gate.en_bit);
-		writel(reg, base + cd->gate.offset);
-
-		/* wait for stop (status_bit = 0) */
-		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
-	}
-
-	/* disable access */
-	writel(0, base + WR_ACCESS_OFFSET);
-
-	return ret;
-}
-
-/* Set the rate of a peripheral clock */
-static int peri_clk_set_rate(struct clk *c, unsigned long rate)
-{
-	int ret = 0;
-	int i;
-	unsigned long diff;
-	unsigned long new_rate = 0, div = 1;
-	struct peri_clock *peri_clk = to_peri_clk(c);
-	struct peri_clk_data *cd = peri_clk->data;
-	const char **clock;
-
-	debug("%s: %s\n", __func__, c->name);
-	diff = rate;
-
-	i = 0;
-	for (clock = cd->clocks; *clock; clock++, i++) {
-		struct refclk *ref = refclk_str_to_clk(*clock);
-		if (!ref) {
-			printf("%s: Lookup of %s failed\n", __func__, *clock);
-			return -EINVAL;
-		}
-
-		/* round to the new rate */
-		div = ref->clk.rate / rate;
-		if (div == 0)
-			div = 1;
-
-		new_rate = ref->clk.rate / div;
-
-		/* get the min diff */
-		if (abs(new_rate - rate) < diff) {
-			diff = abs(new_rate - rate);
-			c->sel = i;
-			c->parent = &ref->clk;
-			c->rate = new_rate;
-			c->div = div;
-		}
-	}
-
-	debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
-	      c->name, c->rate, c->div, c->sel, c->parent->rate);
-	return ret;
-}
-
-/* Get the rate of a peripheral clock */
-static unsigned long peri_clk_get_rate(struct clk *c)
-{
-	struct peri_clock *peri_clk = to_peri_clk(c);
-	struct peri_clk_data *cd = peri_clk->data;
-	void *base = (void *)c->ccu_clk_mgr_base;
-	int div = 1;
-	const char **clock;
-	struct refclk *ref;
-	u32 reg;
-
-	debug("%s: %s\n", __func__, c->name);
-	if (selector_exists(&cd->sel)) {
-		reg = readl(base + cd->sel.offset);
-		c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
-	} else {
-		/*
-		 * For peri clocks that don't have a selector, the single
-		 * reference clock will always exist at index 0.
-		 */
-		c->sel = 0;
-	}
-
-	if (divider_exists(&cd->div)) {
-		reg = readl(base + cd->div.offset);
-		div = bitfield_extract(reg, cd->div.shift, cd->div.width);
-		div += 1;
-	}
-
-	clock = cd->clocks;
-	ref = refclk_str_to_clk(clock[c->sel]);
-	if (!ref) {
-		printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
-		return 0;
-	}
-
-	c->parent = &ref->clk;
-	c->div = div;
-	c->rate = c->parent->rate / c->div;
-	debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
-	      c->parent->rate, div, c->sel, c->rate);
-
-	return c->rate;
-}
-
-/* Peripheral clock operations */
-struct clk_ops peri_clk_ops = {
-	.enable = peri_clk_enable,
-	.set_rate = peri_clk_set_rate,
-	.get_rate = peri_clk_get_rate,
-};
-
-/* Enable a CCU clock */
-static int ccu_clk_enable(struct clk *c, int enable)
-{
-	struct ccu_clock *ccu_clk = to_ccu_clk(c);
-	void *base = (void *)c->ccu_clk_mgr_base;
-	int ret = 0;
-	u32 reg;
-
-	debug("%s: %s\n", __func__, c->name);
-	if (!enable)
-		return -EINVAL;	/* CCU clock cannot shutdown */
-
-	/* enable access */
-	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
-
-	/* config enable for policy engine */
-	writel(1, base + ccu_clk->lvm_en_offset);
-
-	/* wait for bit to go to 0 */
-	ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
-	if (ret)
-		return ret;
-
-	/* freq ID */
-	if (!ccu_clk->freq_bit_shift)
-		ccu_clk->freq_bit_shift = 8;
-
-	/* Set frequency id for each of the 4 policies */
-	reg = ccu_clk->freq_id |
-	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
-	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
-	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
-	writel(reg, base + ccu_clk->policy_freq_offset);
-
-	/* enable all clock mask */
-	writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
-	writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
-	writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
-	writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
-
-	if (ccu_clk->num_policy_masks == 2) {
-		writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
-		writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
-		writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
-		writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
-	}
-
-	/* start policy engine */
-	reg = readl(base + ccu_clk->policy_ctl_offset);
-	reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
-	writel(reg, base + ccu_clk->policy_ctl_offset);
-
-	/* wait till started */
-	ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
-	if (ret)
-		return ret;
-
-	/* disable access */
-	writel(0, base + WR_ACCESS_OFFSET);
-
-	return ret;
-}
-
-/* Get the CCU clock rate */
-static unsigned long ccu_clk_get_rate(struct clk *c)
-{
-	struct ccu_clock *ccu_clk = to_ccu_clk(c);
-	debug("%s: %s\n", __func__, c->name);
-	c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
-	return c->rate;
-}
-
-/* CCU clock operations */
-struct clk_ops ccu_clk_ops = {
-	.enable = ccu_clk_enable,
-	.get_rate = ccu_clk_get_rate,
-};
-
-/* Enable a bus clock */
-static int bus_clk_enable(struct clk *c, int enable)
-{
-	struct bus_clock *bus_clk = to_bus_clk(c);
-	struct bus_clk_data *cd = bus_clk->data;
-	void *base = (void *)c->ccu_clk_mgr_base;
-	int ret = 0;
-	u32 reg;
-
-	debug("%s: %s\n", __func__, c->name);
-	/* enable access */
-	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
-
-	/* enable gating */
-	reg = readl(base + cd->gate.offset);
-	if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
-		debug("%s already %s\n", c->name,
-		      enable ? "enabled" : "disabled");
-	else {
-		int want = (enable) ? 1 : 0;
-		reg |= (1 << cd->gate.hw_sw_sel_bit);
-
-		if (enable)
-			reg |= (1 << cd->gate.en_bit);
-		else
-			reg &= ~(1 << cd->gate.en_bit);
-
-		writel(reg, base + cd->gate.offset);
-		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
-			       want);
-		if (ret)
-			return ret;
-	}
-
-	/* disable access */
-	writel(0, base + WR_ACCESS_OFFSET);
-
-	return ret;
-}
-
-/* Get the rate of a bus clock */
-static unsigned long bus_clk_get_rate(struct clk *c)
-{
-	struct bus_clock *bus_clk = to_bus_clk(c);
-	struct ccu_clock *ccu_clk;
-
-	debug("%s: %s\n", __func__, c->name);
-	ccu_clk = to_ccu_clk(c->parent);
-
-	c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
-	c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
-	return c->rate;
-}
-
-/* Bus clock operations */
-struct clk_ops bus_clk_ops = {
-	.enable = bus_clk_enable,
-	.get_rate = bus_clk_get_rate,
-};
-
-/* Enable a reference clock */
-static int ref_clk_enable(struct clk *c, int enable)
-{
-	debug("%s: %s\n", __func__, c->name);
-	return 0;
-}
-
-/* Reference clock operations */
-struct clk_ops ref_clk_ops = {
-	.enable = ref_clk_enable,
-};
-
-/*
- * clk.h implementation follows
- */
-
-/* Initialize the clock framework */
-int clk_init(void)
-{
-	debug("%s:\n", __func__);
-	return 0;
-}
-
-/* Get a clock handle, give a name string */
-struct clk *clk_get(const char *con_id)
-{
-	int i;
-	struct clk_lookup *clk_tblp;
-
-	debug("%s: %s\n", __func__, con_id);
-
-	clk_tblp = arch_clk_tbl;
-	for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
-		if (clk_tblp->con_id) {
-			if (!con_id || strcmp(clk_tblp->con_id, con_id))
-				continue;
-			return clk_tblp->clk;
-		}
-	}
-	return NULL;
-}
-
-/* Enable a clock */
-int clk_enable(struct clk *c)
-{
-	int ret = 0;
-
-	debug("%s: %s\n", __func__, c->name);
-	if (!c->ops || !c->ops->enable)
-		return -1;
-
-	/* enable parent clock first */
-	if (c->parent)
-		ret = clk_enable(c->parent);
-
-	if (ret)
-		return ret;
-
-	if (!c->use_cnt)
-		ret = c->ops->enable(c, 1);
-	c->use_cnt++;
-
-	return ret;
-}
-
-/* Disable a clock */
-void clk_disable(struct clk *c)
-{
-	debug("%s: %s\n", __func__, c->name);
-	if (!c->ops || !c->ops->enable)
-		return;
-
-	if (c->use_cnt > 0) {
-		c->use_cnt--;
-		if (c->use_cnt == 0)
-			c->ops->enable(c, 0);
-	}
-
-	/* disable parent */
-	if (c->parent)
-		clk_disable(c->parent);
-}
-
-/* Get the clock rate */
-unsigned long clk_get_rate(struct clk *c)
-{
-	unsigned long rate;
-
-	if (!c || !c->ops || !c->ops->get_rate)
-		return 0;
-	debug("%s: %s\n", __func__, c->name);
-
-	rate = c->ops->get_rate(c);
-	debug("%s: rate = %ld\n", __func__, rate);
-	return rate;
-}
-
-/* Set the clock rate */
-int clk_set_rate(struct clk *c, unsigned long rate)
-{
-	int ret;
-
-	if (!c || !c->ops || !c->ops->set_rate)
-		return -EINVAL;
-	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
-
-	if (c->use_cnt)
-		return -EINVAL;
-
-	ret = c->ops->set_rate(c, rate);
-
-	return ret;
-}
-
-/* Not required for this arch */
-/*
-long clk_round_rate(struct clk *clk, unsigned long rate);
-int clk_set_parent(struct clk *clk, struct clk *parent);
-struct clk *clk_get_parent(struct clk *clk);
-*/
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.h b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
deleted file mode 100644
index ace384dea78..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-core.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#include <linux/stddef.h>
-#include <linux/stringify.h>
-
-#ifdef CONFIG_CLK_DEBUG
-#undef writel
-#undef readl
-static inline void writel(u32 val, void *addr)
-{
-	printf("Write [0x%p] = 0x%08x\n", addr, val);
-	*(u32 *)addr = val;
-}
-
-static inline u32 readl(void *addr)
-{
-	u32 val = *(u32 *)addr;
-	printf("Read  [0x%p] = 0x%08x\n", addr, val);
-	return val;
-}
-#endif
-
-struct clk;
-
-struct clk_lookup {
-	const char *dev_id;
-	const char *con_id;
-	struct clk *clk;
-};
-
-extern struct clk_lookup arch_clk_tbl[];
-extern unsigned int arch_clk_tbl_array_size;
-
-/**
- * struct clk_ops - standard clock operations
- * @enable: enable/disable clock, see clk_enable() and clk_disable()
- * @set_rate: set the clock rate, see clk_set_rate().
- * @get_rate: get the clock rate, see clk_get_rate().
- * @round_rate: round a given clock rate, see clk_round_rate().
- * @set_parent: set the clock's parent, see clk_set_parent().
- *
- * Group the common clock implementations together so that we
- * don't have to keep setting the same fiels again. We leave
- * enable in struct clk.
- *
- */
-struct clk_ops {
-	int (*enable)(struct clk *c, int enable);
-	int (*set_rate)(struct clk *c, unsigned long rate);
-	unsigned long (*get_rate)(struct clk *c);
-	unsigned long (*round_rate)(struct clk *c, unsigned long rate);
-	int (*set_parent)(struct clk *c, struct clk *parent);
-};
-
-struct clk {
-	struct clk *parent;
-	const char *name;
-	int use_cnt;
-	unsigned long rate;	/* in HZ */
-
-	/* programmable divider. 0 means fixed ratio to parent clock */
-	unsigned long div;
-
-	struct clk_src *src;
-	struct clk_ops *ops;
-
-	unsigned long ccu_clk_mgr_base;
-	int sel;
-};
-
-struct refclk *refclk_str_to_clk(const char *name);
-
-/* The common clock framework uses u8 to represent a parent index */
-#define PARENT_COUNT_MAX	((u32)U8_MAX)
-
-#define BAD_CLK_INDEX		U8_MAX	/* Can't ever be valid */
-#define BAD_CLK_NAME		((const char *)-1)
-
-#define BAD_SCALED_DIV_VALUE	U64_MAX
-
-/*
- * Utility macros for object flag management. If possible, flags
- * should be defined such that 0 is the desired default value.
- */
-#define FLAG(type, flag)		BCM_CLK_ ## type ## _FLAGS_ ## flag
-#define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
-#define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
-#define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
-#define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
-
-/* Clock field state tests */
-
-#define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)
-#define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)
-#define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)
-#define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)
-#define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)
-#define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)
-
-#define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)
-
-#define divider_exists(div)		FLAG_TEST(div, DIV, EXISTS)
-#define divider_is_fixed(div)		FLAG_TEST(div, DIV, FIXED)
-#define divider_has_fraction(div)	(!divider_is_fixed(div) && \
-						(div)->frac_width > 0)
-
-#define selector_exists(sel)		((sel)->width != 0)
-#define trigger_exists(trig)		FLAG_TEST(trig, TRIG, EXISTS)
-
-/* Clock type, used to tell common block what it's part of */
-enum bcm_clk_type {
-	bcm_clk_none,		/* undefined clock type */
-	bcm_clk_bus,
-	bcm_clk_core,
-	bcm_clk_peri
-};
-
-/*
- * Gating control and status is managed by a 32-bit gate register.
- *
- * There are several types of gating available:
- * - (no gate)
- *     A clock with no gate is assumed to be always enabled.
- * - hardware-only gating (auto-gating)
- *     Enabling or disabling clocks with this type of gate is
- *     managed automatically by the hardware. Such clocks can be
- *     considered by the software to be enabled. The current status
- *     of auto-gated clocks can be read from the gate status bit.
- * - software-only gating
- *     Auto-gating is not available for this type of clock.
- *     Instead, software manages whether it's enabled by setting or
- *     clearing the enable bit. The current gate status of a gate
- *     under software control can be read from the gate status bit.
- *     To ensure a change to the gating status is complete, the
- *     status bit can be polled to verify that the gate has entered
- *     the desired state.
- * - selectable hardware or software gating
- *     Gating for this type of clock can be configured to be either
- *     under software or hardware control. Which type is in use is
- *     determined by the hw_sw_sel bit of the gate register.
- */
-struct bcm_clk_gate {
-	u32 offset;		/* gate register offset */
-	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
-	u32 en_bit;		/* 0: disable; 1: enable */
-	u32 hw_sw_sel_bit;	/* 0: hardware gating; 1: software gating */
-	u32 flags;		/* BCM_CLK_GATE_FLAGS_* below */
-};
-
-/*
- * Gate flags:
- *   HW         means this gate can be auto-gated
- *   SW         means the state of this gate can be software controlled
- *   NO_DISABLE means this gate is (only) enabled if under software control
- *   SW_MANAGED means the status of this gate is under software control
- *   ENABLED    means this software-managed gate is *supposed* to be enabled
- */
-#define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
-#define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
-#define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
-#define BCM_CLK_GATE_FLAGS_NO_DISABLE	((u32)1 << 3)	/* HW or enabled */
-#define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
-#define BCM_CLK_GATE_FLAGS_ENABLED	((u32)1 << 5)	/* If SW_MANAGED */
-
-/*
- * Gate initialization macros.
- *
- * Any gate initially under software control will be enabled.
- */
-
-/* A hardware/software gate initially under software control */
-#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
-	{								\
-		.offset = (_offset),					\
-		.status_bit = (_status_bit),				\
-		.en_bit = (_en_bit),					\
-		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
-		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
-			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
-			FLAG(GATE, EXISTS),				\
-	}
-
-/* A hardware/software gate initially under hardware control */
-#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
-	{								\
-		.offset = (_offset),					\
-		.status_bit = (_status_bit),				\
-		.en_bit = (_en_bit),					\
-		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
-		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
-			FLAG(GATE, EXISTS),				\
-	}
-
-/* A hardware-or-enabled gate (enabled if not under hardware control) */
-#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
-	{								\
-		.offset = (_offset),					\
-		.status_bit = (_status_bit),				\
-		.en_bit = (_en_bit),					\
-		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
-		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
-			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
-	}
-
-/* A software-only gate */
-#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)			\
-	{								\
-		.offset = (_offset),					\
-		.status_bit = (_status_bit),				\
-		.en_bit = (_en_bit),					\
-		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
-			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
-	}
-
-/* A hardware-only gate */
-#define HW_ONLY_GATE(_offset, _status_bit)				\
-	{								\
-		.offset = (_offset),					\
-		.status_bit = (_status_bit),				\
-		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
-	}
-
-/*
- * Each clock can have zero, one, or two dividers which change the
- * output rate of the clock. Each divider can be either fixed or
- * variable. If there are two dividers, they are the "pre-divider"
- * and the "regular" or "downstream" divider. If there is only one,
- * there is no pre-divider.
- *
- * A fixed divider is any non-zero (positive) value, and it
- * indicates how the input rate is affected by the divider.
- *
- * The value of a variable divider is maintained in a sub-field of a
- * 32-bit divider register. The position of the field in the
- * register is defined by its offset and width. The value recorded
- * in this field is always 1 less than the value it represents.
- *
- * In addition, a variable divider can indicate that some subset
- * of its bits represent a "fractional" part of the divider. Such
- * bits comprise the low-order portion of the divider field, and can
- * be viewed as representing the portion of the divider that lies to
- * the right of the decimal point. Most variable dividers have zero
- * fractional bits. Variable dividers with non-zero fraction width
- * still record a value 1 less than the value they represent; the
- * added 1 does *not* affect the low-order bit in this case, it
- * affects the bits above the fractional part only. (Often in this
- * code a divider field value is distinguished from the value it
- * represents by referring to the latter as a "divisor".)
- *
- * In order to avoid dealing with fractions, divider arithmetic is
- * performed using "scaled" values. A scaled value is one that's
- * been left-shifted by the fractional width of a divider. Dividing
- * a scaled value by a scaled divisor produces the desired quotient
- * without loss of precision and without any other special handling
- * for fractions.
- *
- * The recorded value of a variable divider can be modified. To
- * modify either divider (or both), a clock must be enabled (i.e.,
- * using its gate). In addition, a trigger register (described
- * below) must be used to commit the change, and polled to verify
- * the change is complete.
- */
-struct bcm_clk_div {
-	union {
-		struct {	/* variable divider */
-			u32 offset;	/* divider register offset */
-			u32 shift;	/* field shift */
-			u32 width;	/* field width */
-			u32 frac_width;	/* field fraction width */
-
-			u64 scaled_div;	/* scaled divider value */
-		};
-		u32 fixed;	/* non-zero fixed divider value */
-	};
-	u32 flags;		/* BCM_CLK_DIV_FLAGS_* below */
-};
-
-/*
- * Divider flags:
- *   EXISTS means this divider exists
- *   FIXED means it is a fixed-rate divider
- */
-#define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
-#define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
-
-/* Divider initialization macros */
-
-/* A fixed (non-zero) divider */
-#define FIXED_DIVIDER(_value)						\
-	{								\
-		.fixed = (_value),					\
-		.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),		\
-	}
-
-/* A divider with an integral divisor */
-#define DIVIDER(_offset, _shift, _width)				\
-	{								\
-		.offset = (_offset),					\
-		.shift = (_shift),					\
-		.width = (_width),					\
-		.scaled_div = BAD_SCALED_DIV_VALUE,			\
-		.flags = FLAG(DIV, EXISTS),				\
-	}
-
-/* A divider whose divisor has an integer and fractional part */
-#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)		\
-	{								\
-		.offset = (_offset),					\
-		.shift = (_shift),					\
-		.width = (_width),					\
-		.frac_width = (_frac_width),				\
-		.scaled_div = BAD_SCALED_DIV_VALUE,			\
-		.flags = FLAG(DIV, EXISTS),				\
-	}
-
-/*
- * Clocks may have multiple "parent" clocks. If there is more than
- * one, a selector must be specified to define which of the parent
- * clocks is currently in use. The selected clock is indicated in a
- * sub-field of a 32-bit selector register. The range of
- * representable selector values typically exceeds the number of
- * available parent clocks. Occasionally the reset value of a
- * selector field is explicitly set to a (specific) value that does
- * not correspond to a defined input clock.
- *
- * We register all known parent clocks with the common clock code
- * using a packed array (i.e., no empty slots) of (parent) clock
- * names, and refer to them later using indexes into that array.
- * We maintain an array of selector values indexed by common clock
- * index values in order to map between these common clock indexes
- * and the selector values used by the hardware.
- *
- * Like dividers, a selector can be modified, but to do so a clock
- * must be enabled, and a trigger must be used to commit the change.
- */
-struct bcm_clk_sel {
-	u32 offset;		/* selector register offset */
-	u32 shift;		/* field shift */
-	u32 width;		/* field width */
-
-	u32 parent_count;	/* number of entries in parent_sel[] */
-	u32 *parent_sel;	/* array of parent selector values */
-	u8 clk_index;		/* current selected index in parent_sel[] */
-};
-
-/* Selector initialization macro */
-#define SELECTOR(_offset, _shift, _width)				\
-	{								\
-		.offset = (_offset),					\
-		.shift = (_shift),					\
-		.width = (_width),					\
-		.clk_index = BAD_CLK_INDEX,				\
-	}
-
-/*
- * Making changes to a variable divider or a selector for a clock
- * requires the use of a trigger. A trigger is defined by a single
- * bit within a register. To signal a change, a 1 is written into
- * that bit. To determine when the change has been completed, that
- * trigger bit is polled; the read value will be 1 while the change
- * is in progress, and 0 when it is complete.
- *
- * Occasionally a clock will have more than one trigger. In this
- * case, the "pre-trigger" will be used when changing a clock's
- * selector and/or its pre-divider.
- */
-struct bcm_clk_trig {
-	u32 offset;		/* trigger register offset */
-	u32 bit;		/* trigger bit */
-	u32 flags;		/* BCM_CLK_TRIG_FLAGS_* below */
-};
-
-/*
- * Trigger flags:
- *   EXISTS means this trigger exists
- */
-#define BCM_CLK_TRIG_FLAGS_EXISTS	((u32)1 << 0)	/* Trigger is valid */
-
-/* Trigger initialization macro */
-#define TRIGGER(_offset, _bit)						\
-	{								\
-		.offset = (_offset),					\
-		.bit = (_bit),						\
-		.flags = FLAG(TRIG, EXISTS),				\
-	}
-
-struct bus_clk_data {
-	struct bcm_clk_gate gate;
-};
-
-struct core_clk_data {
-	struct bcm_clk_gate gate;
-};
-
-struct peri_clk_data {
-	struct bcm_clk_gate gate;
-	struct bcm_clk_trig pre_trig;
-	struct bcm_clk_div pre_div;
-	struct bcm_clk_trig trig;
-	struct bcm_clk_div div;
-	struct bcm_clk_sel sel;
-	const char *clocks[];	/* must be last; use CLOCKS() to declare */
-};
-#define CLOCKS(...)	{ __VA_ARGS__, NULL, }
-#define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
-
-struct refclk {
-	struct clk clk;
-};
-
-struct peri_clock {
-	struct clk clk;
-	struct peri_clk_data *data;
-};
-
-struct ccu_clock {
-	struct clk clk;
-
-	int num_policy_masks;
-	unsigned long policy_freq_offset;
-	int freq_bit_shift;	/* 8 for most CCUs */
-	unsigned long policy_ctl_offset;
-	unsigned long policy0_mask_offset;
-	unsigned long policy1_mask_offset;
-	unsigned long policy2_mask_offset;
-	unsigned long policy3_mask_offset;
-	unsigned long policy0_mask2_offset;
-	unsigned long policy1_mask2_offset;
-	unsigned long policy2_mask2_offset;
-	unsigned long policy3_mask2_offset;
-	unsigned long lvm_en_offset;
-
-	int freq_id;
-	unsigned long *freq_tbl;
-};
-
-struct bus_clock {
-	struct clk clk;
-	struct bus_clk_data *data;
-	unsigned long *freq_tbl;
-};
-
-struct ref_clock {
-	struct clk clk;
-};
-
-static inline int is_same_clock(struct clk *a, struct clk *b)
-{
-	return a == b;
-}
-
-#define to_clk(p) (&((p)->clk))
-#define name_to_clk(name) (&((name##_clk).clk))
-/* declare a struct clk_lookup */
-#define CLK_LK(name) \
-{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
-
-static inline struct refclk *to_refclk(struct clk *clock)
-{
-	return container_of(clock, struct refclk, clk);
-}
-
-static inline struct peri_clock *to_peri_clk(struct clk *clock)
-{
-	return container_of(clock, struct peri_clock, clk);
-}
-
-static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
-{
-	return container_of(clock, struct ccu_clock, clk);
-}
-
-static inline struct bus_clock *to_bus_clk(struct clk *clock)
-{
-	return container_of(clock, struct bus_clock, clk);
-}
-
-static inline struct ref_clock *to_ref_clk(struct clk *clock)
-{
-	return container_of(clock, struct ref_clock, clk);
-}
-
-extern struct clk_ops peri_clk_ops;
-extern struct clk_ops ccu_clk_ops;
-extern struct clk_ops bus_clk_ops;
-extern struct clk_ops ref_clk_ops;
-
-int clk_get_and_enable(char *clkstr);
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
deleted file mode 100644
index 5f7cc4a102d..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/arch/sysmap.h>
-#include <asm/kona-common/clk.h>
-#include "clk-core.h"
-
-#define WR_ACCESS_ADDR			ESUB_CLK_BASE_ADDR
-#define WR_ACCESS_PASSWORD				0xA5A500
-
-#define PLLE_POST_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C00)
-
-#define PLLE_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C58)
-#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK		0x00010000
-#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK	0x00000001
-
-#define PLL_LOCK_ADDR			(ESUB_CLK_BASE_ADDR + 0x00000C38)
-#define PLL_LOCK_PLL_LOCK_PLLE_MASK			0x00000001
-
-#define ESW_SYS_DIV_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000A04)
-#define ESW_SYS_DIV_PLL_SELECT_MASK			0x00000300
-#define ESW_SYS_DIV_DIV_MASK				0x0000001C
-#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT		0x00000100
-#define ESW_SYS_DIV_DIV_SELECT				0x4
-#define ESW_SYS_DIV_TRIGGER_MASK			0x00000001
-
-#define ESUB_AXI_DIV_DEBUG_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000E04)
-#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK		0x0000001C
-#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK	0x00000040
-#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT	0x0
-#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK			0x00000001
-
-#define PLL_MAX_RETRY	100
-
-/* Enable appropriate clocks for Ethernet */
-int clk_eth_enable(void)
-{
-	int rc = -1;
-	int retry_count = 0;
-	rc = clk_get_and_enable("esub_ccu_clk");
-
-	/* Enable Access to CCU registers */
-	writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
-
-	writel(readl(PLLE_POST_RESETB_ADDR) &
-	       ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
-	       PLLE_POST_RESETB_ADDR);
-
-	/* Take PLL out of reset and put into normal mode */
-	writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
-	       PLLE_RESETB_ADDR);
-
-	/* Wait for PLL lock */
-	rc = -1;
-	while (retry_count < PLL_MAX_RETRY) {
-		udelay(100);
-		if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
-			rc = 0;
-			break;
-		}
-		retry_count++;
-	}
-
-	if (rc == -1) {
-		printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
-		       __func__);
-		return -1;
-	}
-
-	writel(readl(PLLE_POST_RESETB_ADDR) |
-	       PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
-	       PLLE_POST_RESETB_ADDR);
-
-	/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
-	writel((readl(ESW_SYS_DIV_ADDR) &
-		~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
-	       ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
-	       ESW_SYS_DIV_ADDR);
-
-	writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
-	       ESW_SYS_DIV_ADDR);
-
-	/* Wait for trigger complete */
-	rc = -1;
-	retry_count = 0;
-	while (retry_count < PLL_MAX_RETRY) {
-		udelay(100);
-		if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
-			rc = 0;
-			break;
-		}
-		retry_count++;
-	}
-
-	if (rc == -1) {
-		printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
-		       __func__);
-		return -1;
-	}
-
-	/* switch Esub AXI clock to 208MHz */
-	writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
-		~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
-		  ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
-		  ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
-	       ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
-	       ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
-	       ESUB_AXI_DIV_DEBUG_ADDR);
-
-	writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
-	       ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
-	       ESUB_AXI_DIV_DEBUG_ADDR);
-
-	/* Wait for trigger complete */
-	rc = -1;
-	retry_count = 0;
-	while (retry_count < PLL_MAX_RETRY) {
-		udelay(100);
-		if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
-		      ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
-			rc = 0;
-			break;
-		}
-		retry_count++;
-	}
-
-	if (rc == -1) {
-		printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
-		       __func__);
-		return -1;
-	}
-
-	/* Disable Access to CCU registers */
-	writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
-
-	return rc;
-}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
deleted file mode 100644
index f3ff29bebe8..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/sysmap.h>
-#include <asm/kona-common/clk.h>
-#include "clk-core.h"
-
-/* Enable appropriate clocks for an SDIO port */
-int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
-{
-	int ret;
-	struct clk *c;
-
-	char *clkstr;
-	char *slpstr;
-	char *ahbstr;
-
-	switch ((u32) base) {
-	case CONFIG_SYS_SDIO_BASE0:
-		clkstr = CONFIG_SYS_SDIO0 "_clk";
-		ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
-		slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
-		break;
-	case CONFIG_SYS_SDIO_BASE1:
-		clkstr = CONFIG_SYS_SDIO1 "_clk";
-		ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
-		slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
-		break;
-	case CONFIG_SYS_SDIO_BASE2:
-		clkstr = CONFIG_SYS_SDIO2 "_clk";
-		ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
-		slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
-		break;
-	case CONFIG_SYS_SDIO_BASE3:
-		clkstr = CONFIG_SYS_SDIO3 "_clk";
-		ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
-		slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
-		break;
-	default:
-		printf("%s: base 0x%p not found\n", __func__, base);
-		return -EINVAL;
-	}
-
-	ret = clk_get_and_enable(ahbstr);
-	if (ret)
-		return ret;
-
-	ret = clk_get_and_enable(slpstr);
-	if (ret)
-		return ret;
-
-	c = clk_get(clkstr);
-	if (c) {
-		ret = clk_set_rate(c, rate);
-		if (ret)
-			return ret;
-
-		ret = clk_enable(c);
-		if (ret)
-			return ret;
-	} else {
-		printf("%s: Couldn't find %s\n", __func__, clkstr);
-		return -EINVAL;
-	}
-	*actual_ratep = rate;
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
deleted file mode 100644
index 87918059408..00000000000
--- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#include <linux/errno.h>
-#include <asm/arch/sysmap.h>
-#include "clk-core.h"
-
-/* Enable appropriate clocks for the USB OTG port */
-int clk_usb_otg_enable(void *base)
-{
-	char *ahbstr;
-
-	switch ((u32) base) {
-	case HSOTG_BASE_ADDR:
-		ahbstr = "usb_otg_ahb_clk";
-		break;
-	default:
-		printf("%s: base 0x%p not found\n", __func__, base);
-		return -EINVAL;
-	}
-
-	return clk_get_and_enable(ahbstr);
-}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 1c1e33bec24..a7899857658 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -1134,11 +1134,6 @@ int icache_status(void)
 	return (get_sctlr() & CR_I) != 0;
 }
 
-int mmu_status(void)
-{
-	return (get_sctlr() & CR_M) != 0;
-}
-
 void invalidate_icache_all(void)
 {
 	__asm_invalidate_icache_all();
@@ -1160,17 +1155,17 @@ int icache_status(void)
 	return 0;
 }
 
-int mmu_status(void)
-{
-	return 0;
-}
-
 void invalidate_icache_all(void)
 {
 }
 
 #endif	/* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
+int mmu_status(void)
+{
+	return (get_sctlr() & CR_M) != 0;
+}
+
 /*
  * Enable dCache & iCache, whether cache is actually enabled
  * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c8cf3a5a1d..b69eb7cbb94 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,9 +835,7 @@ dtb-$(CONFIG_MX6UL) += \
 	imx6ul-liteboard.dtb \
 	imx6ul-phytec-segin-ff-rdk-nand.dtb \
 	imx6ul-pico-hobbit.dtb \
-	imx6ul-pico-pi.dtb \
-	imx6ul-kontron-bl.dtb \
-	imx6ull-kontron-bl.dtb
+	imx6ul-pico-pi.dtb
 
 dtb-$(CONFIG_MX6ULL) += \
 	imx6ull-14x14-evk.dtb \
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 88e9c0ed2bb..38b168950df 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -102,9 +102,9 @@
 	status = "okay";
 
 	max8997-pmic@66 {
-		compatible = "maxim,max8997";
+		compatible = "maxim,max8997-pmic";
 		reg = <0x66 0 0>;
-		voltage-regulators {
+		regulators {
 			valive_reg: LDO2 {
 			     regulator-name = "VALIVE_1.1V_C210";
 			     regulator-min-microvolt = <1100000>;
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index c87b92be609..cfa99b62828 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -77,7 +77,7 @@
 	max8998-pmic@66 {
 		compatible = "maxim,max8998";
 		reg = <0x66 0 0>;
-		voltage-regulators {
+		regulators {
 			ldo2_reg: LDO2 {
 				regulator-name = "VALIVE_1.2V";
 				regulator-min-microvolt = <1200000>;
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
index ef25cf77447..e147fcb8643 100644
--- a/arch/arm/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -40,7 +40,7 @@
 		s2mps11_pmic@66 {
 			compatible = "samsung,s2mps11-pmic";
 			reg = <0x66>;
-			voltage-regulators {
+			regulators {
 				ldo1_reg: LDO1 {
 					regulator-name = "vdd_ldo1";
 					regulator-min-microvolt = <1000000>;
diff --git a/arch/arm/dts/imx6ul-kontron-bl-43.dts b/arch/arm/dts/imx6ul-kontron-bl-43.dts
deleted file mode 100644
index 0c643706a15..00000000000
--- a/arch/arm/dts/imx6ul-kontron-bl-43.dts
+++ /dev/null
@@ -1,103 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <[email protected]>
- */
-
-#include "imx6ul-kontron-bl.dts"
-
-/ {
-	model = "Kontron BL i.MX6UL 43 (N631X S 43)";
-	compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
-		     "kontron,sl-imx6ul", "fsl,imx6ul";
-
-	backlight {
-		compatible = "pwm-backlight";
-		pwms = <&pwm7 0 5000000>;
-		brightness-levels = <0 4 8 16 32 64 128 255>;
-		default-brightness-level = <6>;
-		status = "okay";
-	};
-};
-
-&i2c4 {
-	touchscreen@5d {
-		compatible = "goodix,gt928";
-		reg = <0x5d>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_cap_touch>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
-		irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&lcdif {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
-	/* Leave status disabled because of missing display panel node */
-};
-
-&pwm7 {
-	#pwm-cells = <2>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm7>;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_cap_touch: captouchgrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0 /* Touch Interrupt */
-			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x1b0b0 /* Touch Reset */
-			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x1b0b0 /* Touch Wake */
-		>;
-	};
-
-	pinctrl_lcdif_ctrl: lcdifctrlgrp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
-			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
-			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
-			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
-			MX6UL_PAD_LCD_RESET__LCDIF_RESET	0x79
-		>;
-	};
-
-	pinctrl_lcdif_dat: lcdifdatgrp {
-		fsl,pins = <
-			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
-			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
-			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
-			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
-			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
-			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
-			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
-			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
-			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
-			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
-			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
-			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
-			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
-			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
-			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
-			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
-			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
-			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
-			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x79
-			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x79
-			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x79
-			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x79
-			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x79
-			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x79
-		>;
-	};
-
-	pinctrl_pwm7: pwm7grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_VSYNC__PWM7_OUT		0x110b0
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi
index 39cc6d05d3f..042bda7462a 100644
--- a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi
@@ -30,9 +30,6 @@
  * in Linux we can't assign the shared reset GPIO to the PHYs, as this
  * would cause Linux to reset both PHYs every time one of them gets
  * reinitialized.
- *
- * Also we disable the second ethernet as it currently doesn't work with
- * the devicetree setup in U-Boot.
  */
 
 &fec1 {
@@ -53,11 +50,16 @@
 			clocks = <&clks IMX6UL_CLK_ENET_REF>;
 			clock-names = "rmii-ref";
 		};
+
+		ethphy2: ethernet-phy@2 {
+			reg = <2>;
+			micrel,led-mode = <0>;
+			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+			clock-names = "rmii-ref";
+		};
 	};
 };
 
 &fec2 {
-	status = "disabled";
-	/delete-property/ phy-handle;
 	/delete-node/ mdio;
 };
diff --git a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common.dtsi
deleted file mode 100644
index a6cf0f21c66..00000000000
--- a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi
+++ /dev/null
@@ -1,406 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <[email protected]>
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_leds>;
-
-		led1 {
-			label = "debug-led1";
-			gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-			linux,default-trigger = "heartbeat";
-		};
-
-		led2 {
-			label = "debug-led2";
-			gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-
-		led3 {
-			label = "debug-led3";
-			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-	};
-
-	pwm-beeper {
-		compatible = "pwm-beeper";
-		pwms = <&pwm8 0 5000>;
-	};
-
-	reg_3v3: regulator-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "5v";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "usb_otg1_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_vref_adc: regulator-vref-adc {
-		compatible = "regulator-fixed";
-		regulator-name = "vref-adc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-&adc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_adc1>;
-	num-channels = <3>;
-	vref-supply = <&reg_vref_adc>;
-	status = "okay";
-};
-
-&can2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	status = "okay";
-};
-
-&ecspi1 {
-	cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	status = "okay";
-
-	eeprom@0 {
-		compatible = "anvo,anv32e61w", "atmel,at25";
-		reg = <0>;
-		spi-max-frequency = <20000000>;
-		spi-cpha;
-		spi-cpol;
-		pagesize = <1>;
-		size = <8192>;
-		address-width = <16>;
-	};
-};
-
-&fec1 {
-	pinctrl-0 = <&pinctrl_enet1>;
-	/delete-node/ mdio;
-};
-
-&fec2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy2>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy1: ethernet-phy@1 {
-			reg = <1>;
-			micrel,led-mode = <0>;
-			clocks = <&clks IMX6UL_CLK_ENET_REF>;
-			clock-names = "rmii-ref";
-		};
-
-		ethphy2: ethernet-phy@2 {
-			reg = <2>;
-			micrel,led-mode = <0>;
-			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
-			clock-names = "rmii-ref";
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-};
-
-&i2c4 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c4>;
-	status = "okay";
-
-	rtc@32 {
-		compatible = "epson,rx8900";
-		reg = <0x32>;
-	};
-};
-
-&pwm8 {
-	#pwm-cells = <2>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm8>;
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	linux,rs485-enabled-at-boot-time;
-	rs485-rx-during-tx;
-	rs485-rts-active-low;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "okay";
-};
-
-&usbotg1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg1>;
-	dr_mode = "otg";
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	over-current-active-low;
-	vbus-supply = <&reg_usb_otg1_vbus>;
-	status = "okay";
-};
-
-&usbotg2 {
-	dr_mode = "host";
-	disable-over-current;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-	keep-power-in-suspend;
-	wakeup-source;
-	vmmc-supply = <&reg_3v3>;
-	voltage-ranges = <3300 3300>;
-	no-1-8-v;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	non-removable;
-	keep-power-in-suspend;
-	wakeup-source;
-	vmmc-supply = <&reg_3v3>;
-	voltage-ranges = <3300 3300>;
-	no-1-8-v;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
-
-	pinctrl_adc1: adc1grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
-			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
-			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0xb0
-		>;
-	};
-
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_DATA07__ECSPI1_MISO	0x100b1
-			MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI	0x100b1
-			MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK	0x100b1
-			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x100b1	/* ECSPI1-CS1 */
-		>;
-	};
-
-	pinctrl_enet2: enet2grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
-			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
-			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b009
-		>;
-	};
-
-	pinctrl_enet2_mdio: enet2mdiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
-			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2grp{
-		fsl,pins = <
-			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
-			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
-		>;
-	};
-
-	pinctrl_gpio: gpiogrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0	/* DOUT1 */
-			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* DIN1 */
-			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x1b0b0	/* DOUT2 */
-			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0	/* DIN2 */
-		>;
-	};
-
-	pinctrl_gpio_leds: gpioledsgrp {
-		fsl,pins = <
-			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x1b0b0	/* LED H14 */
-			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x1b0b0	/* LED H15 */
-			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* LED H16 */
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
-			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
-		>;
-	};
-
-	pinctrl_i2c4: i2c4grp {
-		fsl,pins = <
-			MX6UL_PAD_UART2_TX_DATA__I2C4_SCL	0x4001f8b0
-			MX6UL_PAD_UART2_RX_DATA__I2C4_SDA	0x4001f8b0
-		>;
-	};
-
-	pinctrl_pwm8: pwm8grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_HSYNC__PWM8_OUT		0x110b0
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
-			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_DATA04__UART2_DCE_TX	0x1b0b1
-			MX6UL_PAD_NAND_DATA05__UART2_DCE_RX	0x1b0b1
-			MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS	0x1b0b1
-			/*
-			 * mux unused RTS to make sure it doesn't cause
-			 * any interrupts when it is undefined
-			 */
-			MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
-			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
-			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b1
-			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
-		>;
-	};
-
-	pinctrl_uart4: uart4grp {
-		fsl,pins = <
-			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
-			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x1b0b1
-		>;
-	};
-
-	pinctrl_usbotg1: usbotg1 {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x1b0b0
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
-			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
-			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
-			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
-			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
-			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x100b1	/* SD1_CD */
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx6ul-kontron-bl.dts b/arch/arm/dts/imx6ul-kontron-bl.dts
deleted file mode 100644
index dadf6d3d5f5..00000000000
--- a/arch/arm/dts/imx6ul-kontron-bl.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <[email protected]>
- */
-
-/dts-v1/;
-
-#include "imx6ul-kontron-sl.dtsi"
-#include "imx6ul-kontron-bl-common.dtsi"
-
-/ {
-	model = "Kontron BL i.MX6UL (N631X S)";
-	compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
-};
diff --git a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/dts/imx6ul-kontron-sl-common.dtsi
deleted file mode 100644
index dcf88f61034..00000000000
--- a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <[email protected]>
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	chosen {
-		stdout-path = &uart4;
-	};
-
-	memory@80000000 {
-		reg = <0x80000000 0x10000000>;
-		device_type = "memory";
-	};
-};
-
-&ecspi2 {
-	cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi2>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-	};
-};
-
-&fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy1>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy1: ethernet-phy@1 {
-			reg = <1>;
-			micrel,led-mode = <0>;
-			clocks = <&clks IMX6UL_CLK_ENET_REF>;
-			clock-names = "rmii-ref";
-		};
-	};
-};
-
-&fec2 {
-	phy-mode = "rmii";
-	status = "disabled";
-};
-
-&qspi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_qspi>;
-	status = "okay";
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		spi-max-frequency = <104000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		reg = <0>;
-	};
-};
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	fsl,ext-reset-output;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_reset_out>;
-
-	pinctrl_ecspi2: ecspi2grp {
-		fsl,pins = <
-			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO      0x100b1
-			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI      0x100b1
-			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK      0x100b1
-			MX6UL_PAD_CSI_DATA01__GPIO4_IO22       0x100b1
-		>;
-	};
-
-	pinctrl_enet1: enet1grp {
-		fsl,pins = <
-			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
-			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
-			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
-			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
-			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
-			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
-			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b009
-		>;
-	};
-
-	pinctrl_enet1_mdio: enet1mdiogrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
-			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
-		>;
-	};
-
-	pinctrl_qspi: qspigrp {
-		fsl,pins = <
-			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
-			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
-			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
-			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
-			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
-			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
-		>;
-	};
-
-	pinctrl_reset_out: rstoutgrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x1b0b0
-		>;
-	};
-
-	pinctrl_wdog: wdoggrp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY    0x18b0
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx6ul-kontron-sl.dtsi b/arch/arm/dts/imx6ul-kontron-sl.dtsi
deleted file mode 100644
index 0580d043e5a..00000000000
--- a/arch/arm/dts/imx6ul-kontron-sl.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <[email protected]>
- */
-
-#include "imx6ul.dtsi"
-#include "imx6ul-kontron-sl-common.dtsi"
-
-/ {
-	model = "Kontron SL i.MX6UL (N631X SOM)";
-	compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
-};
diff --git a/arch/arm/dts/imx6ull-kontron-bl.dts b/arch/arm/dts/imx6ull-kontron-bl.dts
deleted file mode 100644
index fa016465cdb..00000000000
--- a/arch/arm/dts/imx6ull-kontron-bl.dts
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2019 Kontron Electronics GmbH
- */
-
-/dts-v1/;
-
-#include "imx6ull-kontron-sl.dtsi"
-#include "imx6ul-kontron-bl-common.dtsi"
-
-/ {
-	model = "Kontron BL i.MX6ULL (N641X S)";
-	compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
-};
diff --git a/arch/arm/dts/imx6ull-kontron-sl.dtsi b/arch/arm/dts/imx6ull-kontron-sl.dtsi
deleted file mode 100644
index 93f10eb3494..00000000000
--- a/arch/arm/dts/imx6ull-kontron-sl.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- */
-
-#include "imx6ull.dtsi"
-#include "imx6ul-kontron-sl-common.dtsi"
-
-/ {
-	model = "Kontron SL i.MX6ULL (N641X SOM)";
-	compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
-};
diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
index 8066f7fb649..6b40106e3bd 100644
--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts
@@ -344,7 +344,6 @@
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
 		/*
 		 * i.MX 8M Plus Data Sheet for Consumer Products
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index f2d99d05854..c1ca3805737 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -245,7 +245,6 @@
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
 		/*
 		 * i.MX 8M Plus Data Sheet for Consumer Products
diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
new file mode 100644
index 00000000000..1320f1540ed
--- /dev/null
+++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		bootph-pre-ram;
+	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc2", "mmc1", "ethernet";
+
+		efi {
+			compatible = "u-boot,distro-efi";
+		};
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
+};
+
+&reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart4 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&gpio5 {
+	bootph-pre-ram;
+};
+
+&uart4 {
+	bootph-pre-ram;
+};
+
+&i2c1 {
+	bootph-pre-ram;
+};
+
+&pmic {
+	bootph-pre-ram;
+};
+
+/* USB1 Type-C */
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	fsl,over-current-active-low;
+	fsl,power-active-low;
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+/* USB2 4-port USB3.0 HUB */
+&usb3_phy1 {
+	vbus-supply = <&reg_vdd_5v0>;
+	status = "okay";
+};
+
+&usb3_1 {
+	fsl,permanently-attached;
+	fsl,disable-port-power-control;
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+};
+
+&usdhc3 {
+	bootph-pre-ram;
+};
+
+&wdog1 {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
index 0c3ca2961c9..0c8d0ba9693 100644
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -69,6 +69,16 @@
 	bootph-some-ram;
 };
 
+&pinctrl_lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
 &pinctrl_reg_usdhc2_vmmc {
 	bootph-pre-ram;
 };
@@ -83,6 +93,16 @@
 	bootph-some-ram;
 };
 
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
 &pinctrl_usdhc2_cd {
 	bootph-pre-ram;
 	bootph-some-ram;
@@ -128,31 +148,9 @@
 	bootph-some-ram;
 };
 
-/*
- * Remove once USB support is added to imx93-phyboard-segin.dts upstream.
- */
-&usbotg1 {
-	disable-over-current;
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usbotg2 {
-	disable-over-current;
-	dr_mode = "host";
-	status = "okay";
-};
-
 &usdhc1 {
 	bootph-pre-ram;
 	bootph-some-ram;
-	/*
-	 * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
-	 */
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 };
 
 &usdhc2 {
@@ -174,6 +172,21 @@
 &lpi2c3 {
 	bootph-pre-ram;
 	bootph-some-ram;
+
+	pmic@25 {
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+		};
+	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
 };
 
 &s4muap {
@@ -209,165 +222,3 @@
 	bootph-all;
 	bootph-pre-ram;
 };
-
-/*
- * The two nodes below won't be needed once nxp,pca9451a
- * support is added to the Linux kernel.
- */
-&iomuxc {
-	pinctrl_lpi2c3: lpi2c3grp {
-		bootph-pre-ram;
-		fsl,pins = <
-			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
-			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
-		>;
-	};
-
-	pinctrl_pmic: pmicgrp {
-		bootph-pre-ram;
-		fsl,pins = <
-			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x31e
-		>;
-	};
-
-	/*
-	 * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
-	 * are added to imx93-phycore-som.dtsi
-	 */
-	/* need to config the SION for data and cmd pad, refer to ERR052021 */
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		bootph-pre-ram;
-		bootph-some-ram;
-		fsl,pins = <
-			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
-			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
-			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
-		>;
-	};
-
-	/* need to config the SION for data and cmd pad, refer to ERR052021 */
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		bootph-pre-ram;
-		bootph-some-ram;
-		fsl,pins = <
-			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
-			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
-			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
-		>;
-	};
-};
-
-&lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-	clock-frequency = <400000>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_lpi2c3>;
-	pinctrl-1 = <&pinctrl_lpi2c3>;
-	status = "okay";
-
-	pmic@25 {
-		bootph-pre-ram;
-		bootph-some-ram;
-		compatible = "nxp,pca9451a";
-		reg = <0x25>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic>;
-		interrupt-parent = <&gpio4>;
-		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
-		regulators {
-			bootph-pre-ram;
-			bootph-some-ram;
-			buck1: BUCK1 {
-				regulator-name = "VDD_SOC";
-				regulator-min-microvolt = <610000>;
-				regulator-max-microvolt = <950000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <3125>;
-			};
-
-			buck2: BUCK2 {
-				regulator-name = "VDDQ_0V6";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <600000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck4: BUCK4 {
-				regulator-name = "VDD_3V3_BUCK";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck5: BUCK5 {
-				regulator-name = "VDD_1V8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck6: BUCK6 {
-				regulator-name = "VDD_1V1";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo1: LDO1 {
-				regulator-name = "PMIC_SNVS_1V8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo4: LDO4 {
-				regulator-name = "VDD_0V8";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo5: LDO5 {
-				regulator-name = "NVCC_SD2";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-
-	eeprom@50 {
-		bootph-pre-ram;
-		bootph-some-ram;
-		compatible = "atmel,24c32";
-		reg = <0x50>;
-		pagesize = <32>;
-		vcc-supply = <&buck4>;
-	};
-};
diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi
new file mode 100644
index 00000000000..5496385dc4d
--- /dev/null
+++ b/arch/arm/dts/imx943-evk-u-boot.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx943-u-boot.dtsi"
+
+&lpuart1 {
+	bootph-pre-ram;
+};
+
+&reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+};
+
+&wdog3 {
+	status = "disabled";
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi
new file mode 100644
index 00000000000..9c4882f7d79
--- /dev/null
+++ b/arch/arm/dts/imx943-u-boot.dtsi
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+/ {
+	binman {
+		multiple-images;
+
+		m33-oei-ddrfw {
+			pad-byte = <0x00>;
+			align-size = <0x8>;
+			filename = "m33-oei-ddrfw.bin";
+
+			oei-m33-ddr {
+				align-size = <0x4>;
+				filename = "oei-m33-ddr.bin";
+				type = "blob-ext";
+			};
+
+			imx-lpddr {
+				type = "nxp-header-ddrfw";
+
+				imx-lpddr-imem {
+					filename = "lpddr5_imem_v202409.bin";
+					type = "blob-ext";
+				};
+
+				imx-lpddr-dmem {
+					filename = "lpddr5_dmem_v202409.bin";
+					type = "blob-ext";
+				};
+			};
+
+			imx-lpddr-qb {
+				type = "nxp-header-ddrfw";
+
+				imx-lpddr-imem-qb {
+					filename = "lpddr5_imem_qb_v202409.bin";
+					type = "blob-ext";
+				};
+
+				imx-lpddr-dmem-qb {
+					filename = "lpddr5_dmem_qb_v202409.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+
+		imx-boot {
+			filename = "flash.bin";
+			pad-byte = <0x00>;
+
+			spl {
+				type = "nxp-imx9image";
+				cfg-path = "spl/u-boot-spl.cfgout";
+				args;
+
+				cntr-version = <2>;
+				boot-from = "sd";
+				soc-type = "IMX9";
+				append = "mx943a0-ahab-container.img";
+				container;
+				dummy-ddr;
+				image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
+				hold = <0x10000>;
+				image1 = "m33", "m33_image.bin", "0x1ffc0000";
+				image2 = "a55", "spl/u-boot-spl.bin", "0x20480000";
+				dummy-v2x = <0x8b000000>;
+			};
+
+			u-boot {
+				type = "nxp-imx9image";
+				cfg-path = "u-boot-container.cfgout";
+				args;
+
+				cntr-version = <2>;
+				boot-from = "sd";
+				soc-type = "IMX9";
+				container;
+				image0 = "a55", "bl31.bin", "0x8a200000";
+				image1 = "a55", "u-boot.bin", "0x90200000";
+			};
+		};
+	};
+};
+
+&cpu0 {
+	clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
+	/delete-property/ power-domains;
+};
+
+&cpu1 {
+	clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
+	/delete-property/ power-domains;
+};
+
+&cpu2 {
+	clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
+	/delete-property/ power-domains;
+};
+
+&cpu3 {
+	clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>;
+	/delete-property/ power-domains;
+};
+
+&aips1 {
+	bootph-all;
+};
+
+&aips2 {
+	bootph-all;
+};
+
+&aips3 {
+	bootph-all;
+};
+
+&clk_ext1 {
+	bootph-all;
+};
+
+&dummy {
+	bootph-all;
+};
+
+&{/firmware} {
+	bootph-all;
+};
+
+&{/firmware/scmi} {
+	bootph-all;
+};
+
+&{/firmware/scmi/protocol@11} {
+	bootph-all;
+};
+
+&{/firmware/scmi/protocol@13} {
+	bootph-all;
+};
+
+&{/firmware/scmi/protocol@14} {
+	bootph-all;
+};
+
+&{/firmware/scmi/protocol@19} {
+	bootph-all;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&gpio5 {
+	bootph-pre-ram;
+};
+
+&gpio6 {
+	bootph-pre-ram;
+};
+
+&gpio7 {
+	bootph-pre-ram;
+};
+
+&mu2 {
+	bootph-all;
+};
+
+&osc_24m {
+	bootph-all;
+};
+
+&scmi_buf0 {
+	bootph-all;
+};
+
+&scmi_buf1 {
+	bootph-all;
+};
+
+&{/soc} {
+	bootph-all;
+
+	elemu1: mailbox@47530000 {
+		compatible = "fsl,imx93-mu-s4";
+		reg = <0x0 0x47530000 0x0 0x10000>;
+		bootph-all;
+		status = "okay";
+	};
+
+	elemu3: mailbox@47550000 {
+		compatible = "fsl,imx93-mu-s4";
+		reg = <0x0 0x47550000 0x0 0x10000>;
+		bootph-all;
+		status = "okay";
+	};
+};
+
+&sram0 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
index 2d1f02baa5f..8b59831b7ca 100644
--- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
@@ -5,6 +5,13 @@
 
 #include "imx95-u-boot.dtsi"
 
+/ {
+	aliases {
+		pci0 = &netc_bus0;
+		pci1 = &netc_bus1;
+	};
+};
+
 &lpuart1 {
 	bootph-pre-ram;
 };
diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
index de74398fdfe..591cb317508 100644
--- a/arch/arm/dts/imx95-u-boot.dtsi
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -202,6 +202,22 @@
 	bootph-all;
 };
 
+&pcie0 {
+	assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+					 <&scmi_clk IMX95_CLK_HSIOPLL>,
+					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+	assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+				 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+};
+
+&pcie1 {
+	assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+					 <&scmi_clk IMX95_CLK_HSIOPLL>,
+					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+	assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+				 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+};
+
 &{/soc} {
 	bootph-all;
 };
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index ee273563e83..3a1a8b06dc6 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -95,6 +95,22 @@
 	bootph-all;
 };
 
+&main_rti1 {
+	status = "disabled";
+};
+
+&main_rti2 {
+	status = "disabled";
+};
+
+&main_rti3 {
+	status = "disabled";
+};
+
+&main_rti15 {
+	status = "disabled";
+};
+
 &main_uart0 {
 	bootph-all;
 };
diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
index 73255a18e9b..8afd844460a 100644
--- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -156,6 +156,22 @@
 	bootph-all;
 };
 
+&main_rti1 {
+	status = "disabled";
+};
+
+&main_rti2 {
+	status = "disabled";
+};
+
+&main_rti3 {
+	status = "disabled";
+};
+
+&main_rti4 {
+	status = "disabled";
+};
+
 &main_uart0 {
 	bootph-all;
 };
diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
index c68a48678a2..56547cbd28a 100644
--- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
@@ -156,6 +156,10 @@
 	bootph-all;
 };
 
+&main_rti1 {
+	status = "disabled";
+};
+
 &sdhci0 {
 	bootph-all;
 };
diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts
index 17e6b5af7a2..ad149a34437 100644
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -139,7 +139,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
@@ -162,7 +161,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi2_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
index e01ae4c3dc7..ab6f84a3ece 100644
--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -173,7 +173,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts
index d4bbb23204a..0d628a2e715 100644
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -178,7 +178,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts
index 11823e05bda..632f8b9446d 100644
--- a/arch/arm/dts/mt7986a-sd-rfb.dts
+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
@@ -138,7 +138,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts
index 0a731fe87fd..44524345468 100644
--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -165,7 +165,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts
index e5fb4d73e70..d5c4273047a 100644
--- a/arch/arm/dts/mt7986b-sd-rfb.dts
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
@@ -134,7 +134,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_flash_pins>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi
index 54cf72b3bf8..dc3f70aad64 100644
--- a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi
@@ -42,7 +42,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi
index f1ed51e21c4..fa02ff59f6a 100644
--- a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi
@@ -28,7 +28,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
@@ -52,7 +51,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi
index b07e6da41e2..cf1114e7d99 100644
--- a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi
@@ -40,7 +40,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts
index 1694ef8d9c3..6176ef923b2 100644
--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -181,7 +181,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
@@ -204,7 +203,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts
index 63e923137c2..e29a9764187 100644
--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -108,7 +108,6 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "okay";
-	must_tx;
 	enhance_timing;
 	dma_ext;
 	ipm_design;
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
index db7517cc9ba..6866005336f 100644
--- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -62,6 +62,11 @@
 			reg = <0x0 0xf0801000 0x0 0x1000>;
 		};
 
+		timer0: timer@f0801068 {
+			compatible = "nuvoton,npcm845-timer";
+			reg = <0x0 0xf0801068 0x0 0x8>;
+		};
+
 		sdhci0: sdhci@f0842000 {
 			compatible = "nuvoton,npcm845-sdhci";
 			reg = <0x0 0xf0842000 0x0 0x100>;
@@ -136,7 +141,7 @@
 
 			host_intf: host_intf@9f000 {
 				compatible = "nuvoton,npcm845-host-intf";
-				reg = <0x9f000 0x1000>;
+				reg = <0x9f000 0x1000>, <0x7000 0x40>;
 				type = "espi";
 				ioaddr = <0x4e>;
 				channel-support = <0xf>;
@@ -157,14 +162,6 @@
 				status = "disabled";
 			};
 
-			timer0: timer@8000 {
-				compatible = "nuvoton,npcm845-timer";
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				reg = <0x8000 0x1C>;
-				clocks = <&clk NPCM8XX_CLK_REFCLK>;
-				clock-names = "refclk";
-			};
-
 			serial0: serial@0 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x0 0x1000>;
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index bc047d4b443..6f933355d9e 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -1056,5 +1056,9 @@
 			groups = "jtag2";
 			function = "jtag2";
 		};
+		vcdhs_pins: vcdhs-pins {
+			groups = "vcdhs";
+			function = "vcdhs";
+		};
 	};
 };
diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
index 90e3405040a..6c15a87ffb0 100644
--- a/arch/arm/dts/s5pc1xx-goni.dts
+++ b/arch/arm/dts/s5pc1xx-goni.dts
@@ -45,7 +45,7 @@
 			compatible = "maxim,max8998";
 			reg = <0x66 0 0>;
 
-			voltage-regulators {
+			regulators {
 				ldo2_reg: LDO2 {
 					regulator-compatible = "LDO2";
 					regulator-name = "VALIVE_1.1V";
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 402f0bec173..d51a9e2ff7f 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -209,7 +209,7 @@
 					/* DMIUSMCTCR */
 					<0x00000300 0x00000001 0x00000003>,
 					<0x00000300 0x00000003 0x00000003>,
-					<0x00000308 0x00000004 0x0000001F>;
+					<0x00000308 0x0000000C 0x0000001F>;
 				bootph-all;
 			};
 
@@ -220,7 +220,7 @@
 					/* DMIUSMCTCR */
 					<0x00000300 0x00000001 0x00000003>,
 					<0x00000300 0x00000003 0x00000003>,
-					<0x00000308 0x00000004 0x0000001F>;
+					<0x00000308 0x0000000C 0x0000001F>;
 				bootph-all;
 			};
 		};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
index 2ab143e38f8..886cc89fdb6 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -87,6 +87,10 @@
 	disable-over-current;
 };
 
+&usb31 {
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
index eb82d663204..ea80d1bed15 100644
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -232,6 +232,18 @@
 			status = "disabled";
 		};
 
+		nand: nand@ffb90000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "altr,socfpga-denali-nand";
+			reg = <0xffb90000 0x10000>,
+			      <0xffb80000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+			interrupts = <0 97 4>;
+			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
+			status = "disabled";
+		};
+
 		ocram: sram@ffe00000 {
 			compatible = "mmio-sram";
 			reg = <0xffe00000 0x100000>;
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
index e6d8fe6a907..864f4093ef8 100644
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -137,3 +137,7 @@
 &usb0 {
 	status = "okay";
 };
+
+&watchdog0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
index 9a566e18d3f..7bbb3e00351 100644
--- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
@@ -12,6 +12,47 @@
 	};
 };
 
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "fsbla1";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@40000 {
+			label = "fsbla2";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@80000 {
+			label = "metadata1";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@C0000 {
+			label = "metadata2";
+			reg = <0x000C0000 0x00040000>;
+		};
+		partition@100000 {
+			label = "fip-a";
+			reg = <0x00100000 0x00400000>;
+		};
+		partition@500000 {
+			label = "fip-b";
+			reg = <0x00500000 0x00400000>;
+		};
+		partition@900000 {
+			label = "u-boot-env";
+			reg = <0x00900000 0x00080000>;
+		};
+		partition@980000 {
+			label = "nor-user";
+			reg = <0x00980000 0x03680000>;
+		};
+	};
+};
+
 &usart2 {
 	bootph-all;
 };
diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h
deleted file mode 100644
index 8cde42b89bb..00000000000
--- a/arch/arm/include/asm/arch-bcm235xx/boot0.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Broadcom Corporation.
- */
-
-/* BOOT0 header information */
-_start:
-	ARM_VECTORS
-	.word	0xbabeface
-	.word	_end - _start
diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h
deleted file mode 100644
index 82c12bb70c2..00000000000
--- a/arch/arm/include/asm/arch-bcm235xx/gpio.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#ifndef __ARCH_BCM235XX_GPIO_H
-#define __ARCH_BCM235XX_GPIO_H
-
-/*
- * Empty file - cmd_gpio.c requires this. The implementation
- * is in drivers/gpio/kona_gpio.c instead of inlined here.
- */
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
deleted file mode 100644
index ff6debc677c..00000000000
--- a/arch/arm/include/asm/arch-bcm235xx/sysmap.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Broadcom Corporation.
- */
-
-#ifndef __ARCH_BCM235XX_SYSMAP_H
-
-#define BSC1_BASE_ADDR		0x3e016000
-#define BSC2_BASE_ADDR		0x3e017000
-#define BSC3_BASE_ADDR		0x3e018000
-#define GPIO2_BASE_ADDR		0x35003000
-#define HSOTG_BASE_ADDR		0x3f120000
-#define HSOTG_CTRL_BASE_ADDR	0x3f130000
-#define KONA_MST_CLK_BASE_ADDR	0x3f001000
-#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
-#define PMU_BSC_BASE_ADDR	0x3500d000
-#define SDIO1_BASE_ADDR		0x3f180000
-#define SDIO2_BASE_ADDR		0x3f190000
-#define SDIO3_BASE_ADDR		0x3f1a0000
-#define SDIO4_BASE_ADDR		0x3f1b0000
-#define TIMER_BASE_ADDR		0x3e00d000
-
-#define HSOTG_DCTL_OFFSET					0x00000804
-#define    HSOTG_DCTL_SFTDISCON_MASK				0x00000002
-
-#define HSOTG_CTRL_PHY_P1CTL_OFFSET				0x00000008
-#define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK			0x00000002
-#define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK		0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 1f669c72d00..1af9778f8ce 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -78,6 +78,8 @@
 
 #define MXC_CPU_IMX95		0x1C1 /* dummy ID */
 
+#define MXC_CPU_IMX94		0x1C2 /* dummy ID */
+
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
 #define MXC_SOC_IMX8M		0x80
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 5127fe8f286..e641ed299c0 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -17,14 +17,23 @@
 
 #define ANATOP_BASE_ADDR    0x44480000UL
 
+#ifdef CONFIG_IMX94
+#define WDG3_BASE_ADDR      0x49220000UL
+#define WDG4_BASE_ADDR      0x49230000UL
+#else
 #define WDG3_BASE_ADDR      0x42490000UL
 #define WDG4_BASE_ADDR      0x424a0000UL
+#endif
 #define WDG5_BASE_ADDR      0x424b0000UL
 
 #define GPIO2_BASE_ADDR	    0x43810000UL
 #define GPIO3_BASE_ADDR	    0x43820000UL
 #define GPIO4_BASE_ADDR	    0x43840000UL
 #define GPIO5_BASE_ADDR	    0x43850000UL
+#ifdef CONFIG_IMX94
+#define GPIO6_BASE_ADDR	    0x43860000UL
+#define GPIO7_BASE_ADDR	    0x43870000UL
+#endif
 
 #define FSB_BASE_ADDR       0x47510000UL
 
@@ -48,7 +57,7 @@
 #define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
 #define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
 
-#define IMG_CONTAINER_BASE             (0x80000000UL)
+#define IMG_CONTAINER_BASE             CFG_SYS_SDRAM_BASE
 
 #define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK        GENMASK(3, 1)
 #define BCTRL_GPR_ENET_QOS_INTF_SEL_MII          (0x0 << 1)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 455aa95339e..dead7a99a66 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -21,6 +21,7 @@ int m33_prepare(void);
 int low_drive_freq_update(void *blob);
 
 enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
+int get_reset_reason(bool sys, bool lm);
 
 #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
 
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
index e906fdf1bf1..d8f0e16dadd 100644
--- a/arch/arm/include/asm/armv8/cpu.h
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -11,6 +11,7 @@
 #define MIDR_PARTNUM_CORTEX_A73		0xD09
 #define MIDR_PARTNUM_CORTEX_A75		0xD0A
 #define MIDR_PARTNUM_CORTEX_A76		0xD0B
+#define MIDR_PARTNUM_CORTEX_A720	0xD81
 #define MIDR_PARTNUM_SHIFT		0x4
 #define MIDR_PARTNUM_MASK		(0xFFF << MIDR_PARTNUM_SHIFT)
 
@@ -40,3 +41,4 @@ is_cortex_a(72)
 is_cortex_a(73)
 is_cortex_a(75)
 is_cortex_a(76)
+is_cortex_a(720)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 85ec0e6937e..cebed7397d4 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -386,12 +386,14 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
 		count--;
 	}
 
-	if (mmu_status()) {
-		while (count >= 8) {
-			*(u64 *)to = __raw_readq(from);
-			from += 8;
-			to += 8;
-			count -= 8;
+	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+		if (mmu_status()) {
+			while (count >= 8) {
+				*(u64 *)to = __raw_readq(from);
+				from += 8;
+				to += 8;
+				count -= 8;
+			}
 		}
 	}
 
@@ -416,12 +418,14 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
 		count--;
 	}
 
-	if (mmu_status()) {
-		while (count >= 8) {
-			__raw_writeq(*(u64 *)from, to);
-			from += 8;
-			to += 8;
-			count -= 8;
+	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+		if (mmu_status()) {
+			while (count >= 8) {
+				__raw_writeq(*(u64 *)from, to);
+				from += 8;
+				to += 8;
+				count -= 8;
+			}
 		}
 	}
 
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 0780f99b49a..46da7a1eff5 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -97,6 +97,7 @@ struct bd_info;
 #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
 #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
 
+#define is_imx94() (is_cpu_type(MXC_CPU_IMX94))
 #define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
 
 #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index ca4cec61f22..b874aa252c6 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -57,6 +57,7 @@ static void announce_and_cleanup(int fake)
 #ifdef CONFIG_BOOTSTAGE_FDT
 	bootstage_fdt_add_report();
 #endif
+	bootstage_stash_default();
 #ifdef CONFIG_BOOTSTAGE_REPORT
 	bootstage_report();
 #endif
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index f3f279f2c39..3e7627aa389 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -158,8 +158,10 @@ relocation_return:
 /*
  * Clear BSS section
  */
-	ldr	x0, =__bss_start		/* this is auto-relocated! */
-	ldr	x1, =__bss_end			/* this is auto-relocated! */
+	adrp	x0, __bss_start
+	add	x0, x0, #:lo12:__bss_start
+	adrp	x1, __bss_end
+	add	x1, x1, #:lo12:__bss_end
 clear_loop:
 	str	xzr, [x0], #8
 	cmp	x0, x1
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index c43a63f1819..6c7d1fb5629 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -46,8 +46,7 @@ void __weak board_init_f(ulong dummy)
 }
 
 /*
- * This function jumps to an image with argument. Normally an FDT or ATAGS
- * image.
+ * This function jumps to an image with argument, usually an FDT.
  */
 #if CONFIG_IS_ENABLED(OS_BOOT)
 #ifdef CONFIG_ARM64
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fa2cdaba144..1efe690e876 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -223,7 +223,7 @@ endif
 
 ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
 
-ifneq ($(and $(CONFIG_IMX95),$(CONFIG_BINMAN)),)
+ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),)
 SPL: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 else
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 647daeb6562..38e671e3935 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -411,6 +411,54 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
 	return CMD_RET_SUCCESS;
 }
 
+#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94)
+#define FSB_LC_OFFSET 0x414
+#define LC_OEM_OPEN 0x10
+static void display_life_cycle(u32 lc)
+{
+	printf("Lifecycle: 0x%08X, ", lc);
+	switch (lc) {
+	case 0x1:
+		printf("BLANK\n\n");
+		break;
+	case 0x2:
+		printf("FAB Default\n\n");
+		break;
+	case 0x4:
+		printf("FAB\n\n");
+		break;
+	case 0x8:
+		printf("NXP Provisioned\n\n");
+		break;
+	case 0x10:
+		printf("OEM Open\n\n");
+		break;
+	case 0x20:
+		printf("OEM secure world closed\n\n");
+		break;
+	case 0x40:
+		printf("OEM closed\n\n");
+		break;
+	case 0x80:
+		printf("OEM Locked\n\n");
+		break;
+	case 0x100:
+		printf("Field Return OEM\n\n");
+		break;
+	case 0x200:
+		printf("Field Return NXP\n\n");
+		break;
+	case 0x400:
+		printf("BRICKED\n\n");
+		break;
+	default:
+		printf("Unknown\n\n");
+		break;
+	}
+}
+#else
+#define FSB_LC_OFFSET 0x41c
+#define LC_OEM_OPEN 0x8
 static void display_life_cycle(u32 lc)
 {
 	printf("Lifecycle: 0x%08X, ", lc);
@@ -447,6 +495,7 @@ static void display_life_cycle(u32 lc)
 		break;
 	}
 }
+#endif
 
 static int confirm_close(void)
 {
@@ -474,10 +523,10 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (!confirm_close())
 		return -EACCES;
 
-	lc = readl(FSB_BASE_ADDR + 0x41c);
+	lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET);
 	lc &= 0x3ff;
 
-	if (lc != 0x8) {
+	if (lc != LC_OEM_OPEN) {
 		puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n");
 		display_life_cycle(lc);
 		return -EPERM;
@@ -540,7 +589,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const
 	u32 cnt = AHAB_MAX_EVENTS;
 	int ret;
 
-	lc = readl(FSB_BASE_ADDR + 0x41c);
+	lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET);
 	lc &= 0x3ff;
 
 	display_life_cycle(lc);
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 3a9e6dcf225..78f2488cf6d 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type)
 
 	debug("seco container size 0x%x\n", value_container[0]);
 
-	if (is_imx95()) {
+	if (is_imx95() || is_imx94()) {
 		offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
 
 		value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw);
@@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type)
 	value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL);
 	if (value_container[2] < 0) {
 		debug("Parse scu container image failed %d, only seco container\n", value_container[2]);
-		if (is_imx95())
+		if (is_imx95() || is_imx94())
 			return value_container[1] + offset[1]; /* return seco + v2x container total size */
 		else
 			return value_container[0] + offset[0]; /* return seco container total size */
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 324e010bb2c..f13baa871cc 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -401,6 +401,29 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 	return 0;
 }
 
+static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	u32 info;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	info = simple_strtoul(argv[1], NULL, 16);
+	printf("Commit index is 0x%x\n", info);
+
+	ret = sc_seco_commit(-1, &info);
+	if (ret) {
+		printf("Error in AHAB commit\n");
+		return ret;
+	}
+
+	printf("AHAB commit succeeded.\n");
+
+	return CMD_RET_SUCCESS;
+}
+
 U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
 	   "autenticate OS container via AHAB",
 	   "addr\n"
@@ -416,3 +439,9 @@ U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
 	   "Change AHAB lifecycle to OEM closed",
 	   ""
 );
+
+U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit,
+	   "commit into the fuses any new SRK revocation information that have been found\n"
+	   "into the NXP (SECO FW) and OEM containers. For SRK revocation use 0x10 for the value.",
+	   ""
+);
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 74416a78847..e7bc154b805 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -345,6 +345,15 @@ config TARGET_PHYCORE_IMX8MP
 	select IMX8M_LPDDR4
 	imply OF_UPSTREAM
 
+config TARGET_IMX8MP_LIBRA_FPSC
+	bool "PHYTEC Libra i.MX 8M Plus FPSC"
+	select IMX8MP
+	select SUPPORT_SPL
+	select IMX8M_LPDDR4
+	imply OF_UPSTREAM
+	help
+	  Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC.
+
 config TARGET_IMX8MM_CL_IOT_GATE
 	bool "CompuLab iot-gate-imx8"
 	select IMX8MM
@@ -409,6 +418,7 @@ source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/msc/sm2s_imx8mp/Kconfig"
 source "board/mntre/imx8mq_reform2/Kconfig"
+source "board/phytec/imx8mp-libra-fpsc/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/polyhex/imx8mp_debix_model_a/Kconfig"
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index b6acbb20ff0..48f458fa55c 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -38,6 +38,15 @@ config IMX95
 	select SPL_IMX_CONTAINER_USE_TRAMPOLINE
 	select IMX_PQC_SUPPORT if !IMX95_A0
 
+config IMX94
+	bool
+	select ARMV8_SPL_EXCEPTION_VECTORS
+	select DM_MAILBOX
+	select IMX9
+	select IMX_PQC_SUPPORT
+	select SCMI_FIRMWARE
+	select SPL_IMX_CONTAINER_USE_TRAMPOLINE
+
 config SYS_SOC
 	default "imx9"
 
@@ -97,6 +106,13 @@ config TARGET_IMX95_19X19_EVK
 	imply BOOTSTD_FULL
 	imply OF_UPSTREAM
 
+config TARGET_IMX943_EVK
+	bool "imx943_evk"
+	select IMX94
+	imply BOOTSTD_BOOTCOMMAND
+	imply BOOTSTD_FULL
+	imply OF_UPSTREAM
+
 endchoice
 
 source "board/freescale/imx91_evk/Kconfig"
@@ -105,6 +121,7 @@ source "board/freescale/imx93_frdm/Kconfig"
 source "board/freescale/imx93_qsb/Kconfig"
 source "board/phytec/phycore_imx93/Kconfig"
 source "board/variscite/imx93_var_som/Kconfig"
+source "board/freescale/imx94_evk/Kconfig"
 source "board/freescale/imx95_evk/Kconfig"
 
 endif
diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile
index 4534db08d28..b98744e1ecb 100644
--- a/arch/arm/mach-imx/imx9/scmi/Makefile
+++ b/arch/arm/mach-imx/imx9/scmi/Makefile
@@ -2,5 +2,8 @@
 #
 # Copyright 2025 NXP
 
+# Add include path for NXP device tree header files from Linux.
+ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/
+
 obj-y += soc.o
 obj-y += clock_scmi.o clock.o
diff --git a/arch/arm/mach-imx/imx9/scmi/clock.c b/arch/arm/mach-imx/imx9/scmi/clock.c
index 6e6541eaa31..951d47bd9d7 100644
--- a/arch/arm/mach-imx/imx9/scmi/clock.c
+++ b/arch/arm/mach-imx/imx9/scmi/clock.c
@@ -6,16 +6,17 @@
 #include <asm/arch/clock.h>
 #include <dm/uclass.h>
 #include <scmi_agent.h>
-#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h"
+#include <scmi_nxp_protocols.h>
+#include "common.h"
 
 u32 get_arm_core_clk(void)
 {
 	u32 val;
 
-	val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0);
+	val = imx_clk_scmi_get_rate(SCMI_CLK(SEL_A55C0));
 	if (val)
 		return val;
-	return imx_clk_scmi_get_rate(IMX95_CLK_A55);
+	return imx_clk_scmi_get_rate(SCMI_CLK(A55));
 }
 
 void init_uart_clk(u32 index)
@@ -24,13 +25,13 @@ void init_uart_clk(u32 index)
 
 	switch (index) {
 	case 0:
-		clock_id = IMX95_CLK_LPUART1;
+		clock_id = SCMI_CLK(LPUART1);
 		break;
 	case 1:
-		clock_id = IMX95_CLK_LPUART2;
+		clock_id = SCMI_CLK(LPUART2);
 		break;
 	case 2:
-		clock_id = IMX95_CLK_LPUART3;
+		clock_id = SCMI_CLK(LPUART3);
 		break;
 	default:
 		return;
@@ -38,7 +39,7 @@ void init_uart_clk(u32 index)
 
 	/* 24MHz */
 	imx_clk_scmi_enable(clock_id, false);
-	imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M);
+	imx_clk_scmi_set_parent(clock_id, SCMI_CLK(24M));
 	imx_clk_scmi_set_rate(clock_id, 24000000);
 	imx_clk_scmi_enable(clock_id, true);
 }
@@ -49,19 +50,19 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_ARM_CLK:
 		return get_arm_core_clk();
 	case MXC_IPG_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP);
+		return imx_clk_scmi_get_rate(SCMI_CLK(BUSWAKEUP));
 	case MXC_CSPI_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1);
+		return imx_clk_scmi_get_rate(SCMI_CLK(LPSPI1));
 	case MXC_ESDHC_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1);
+		return imx_clk_scmi_get_rate(SCMI_CLK(USDHC1));
 	case MXC_ESDHC2_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2);
+		return imx_clk_scmi_get_rate(SCMI_CLK(USDHC2));
 	case MXC_ESDHC3_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3);
+		return imx_clk_scmi_get_rate(SCMI_CLK(USDHC3));
 	case MXC_UART_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1);
+		return imx_clk_scmi_get_rate(SCMI_CLK(LPUART1));
 	case MXC_FLEXSPI_CLK:
-		return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1);
+		return imx_clk_scmi_get_rate(SCMI_CLK(FLEXSPI1));
 	default:
 		return -1;
 	};
diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h
new file mode 100644
index 00000000000..dd4675402c7
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/common.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef _SCMI_CLOCK_COMMON_H_
+#define _SCMI_CLOCK_COMMON_H_
+
+#ifdef CONFIG_IMX94
+#define IMX_PLAT 94
+#include <imx94-clock.h>
+#include <imx94-power.h>
+
+#define IMX94_CLK_FLEXSPI1 IMX94_CLK_XSPI1
+#endif
+
+#ifdef CONFIG_IMX95
+#define IMX_PLAT 95
+#include <imx95-clock.h>
+#include <imx95-power.h>
+
+#define IMX95_PD_M70 IMX95_PD_M7
+#endif
+
+#define IMX_PLAT_STR__(plat) # plat
+#define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT)
+#define IMX_PLAT_STR IMX_PLAT_STR_(IMX_PLAT)
+
+#define SCMI_CLK__(plat, clk) IMX ## plat ## _CLK_ ## clk
+#define SCMI_CLK_(plat, clk) SCMI_CLK__(plat, clk)
+#define SCMI_CLK(clk) SCMI_CLK_(IMX_PLAT, clk)
+
+#define SCMI_PD__(plat, pd) IMX ## plat ## _PD_ ## pd
+#define SCMI_PD_(plat, pd) SCMI_PD__(plat, pd)
+#define SCMI_PD(pd) SCMI_PD_(IMX_PLAT, pd)
+
+#define SCMI_CPU__(plat) MXC_CPU_IMX ## plat
+#define SCMI_CPU_(plat) SCMI_CPU__(plat)
+#define SCMI_CPU SCMI_CPU_(IMX_PLAT)
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index f973652d0cb..dbaa19a9e6e 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -17,8 +17,11 @@
 #include <env_internal.h>
 #include <fuse.h>
 #include <imx_thermal.h>
+#include <linux/bitfield.h>
 #include <linux/iopoll.h>
 #include <scmi_agent.h>
+#include <scmi_nxp_protocols.h>
+#include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -174,7 +177,7 @@ u32 get_cpu_rev(void)
 {
 	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
 
-	return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev);
+	return (SCMI_CPU << 12) | (CHIP_REV_1_0 + rev);
 }
 
 #define UNLOCK_WORD 0xD928C520
@@ -254,6 +257,30 @@ static struct mm_region imx9_mem_map[] = {
 			 PTE_BLOCK_OUTER_SHARE
 	}, {
 #endif
+		/* PCIE2 ECAM */
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* PCIE1 Outbound */
+		.virt = 0x900000000UL,
+		.phys = 0x900000000UL,
+		.size = 0x100000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* PCIE2 Outbound */
+		.virt = 0xA00000000UL,
+		.phys = 0xA00000000UL,
+		.size = 0x100000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
 		/* empty entry to split table entry 5 if needed when TEEs are used */
 		0,
 	}, {
@@ -435,12 +462,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	u32 val[2] = {};
 	int ret, num_of_macs;
+	u32 bank = 40;
+
+	if (is_imx94())
+		bank = 66;
 
-	ret = fuse_read(40, 5, &val[0]);
+	ret = fuse_read(bank, 5, &val[0]);
 	if (ret)
 		goto err;
 
-	ret = fuse_read(40, 6, &val[1]);
+	ret = fuse_read(bank, 6, &val[1]);
 	if (ret)
 		goto err;
 
@@ -456,10 +487,32 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 	mac[3] = (val[0] >> 24) & 0xff;
 	mac[4] = val[1] & 0xff;
 	mac[5] = (val[1] >> 8) & 0xff;
-	if (dev_id == 1)
-		mac[5] = mac[5] + 3;
-	if (dev_id == 2)
-		mac[5] = mac[5] + 6;
+
+	if (is_imx94()) {
+		/*
+		 * i.MX94 uses the following mac address offset list:
+		 * | No.    | Module      | Mac address user          |
+		 * |--------|-------------|---------------------------|
+		 * | 0 ~ 1  | ethercat    | port0/port1               |
+		 * | 2      | netc switch | internal enetc3 mac/swp0  |
+		 * | 3 ~ 6  |             | enetc3 vf1~3/swp1         |
+		 * | 7      | enetc mac   | enetc0 pf                 |
+		 * | 8      |             | enetc1 pf                 |
+		 * | 9      |             | enetc2 pf                 |
+		 * | 10     | netc switch | swp2                      |
+		 */
+		if (dev_id == 0)
+			mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */
+		if (dev_id == 1)
+			mac[5] = mac[5] + 8; /* enetc1 */
+		if (dev_id == 2)
+			mac[5] = mac[5] + 9; /* enetc2 */
+	} else {
+		if (dev_id == 1)
+			mac[5] = mac[5] + 3;
+		if (dev_id == 2)
+			mac[5] = mac[5] + 6;
+	}
 
 	debug("%s: MAC%d: %pM\n", __func__, dev_id, mac);
 	return;
@@ -468,11 +521,149 @@ err:
 	printf("%s: fuse read err: %d\n", __func__, ret);
 }
 
+static char *rst_string[32] = {
+	"cm33_lockup",
+	"cm33_swreq",
+	"cm7_lockup",
+	"cm7_swreq",
+	"fccu",
+	"jtag_sw",
+	"ele",
+	"tempsense",
+	"wdog1",
+	"wdog2",
+	"wdog3",
+	"wdog4",
+	"wdog5",
+	"jtag",
+	"cm33_exc",
+	"bbm",
+	"sw",
+	"sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused",
+	"unused", "unused", "unused", "unused", "unused", "unused",
+	"unused", "unused",
+	"por"
+};
+
+static char *rst_string_imx94[32] = {
+	"cm33_lockup",
+	"cm33_swreq",
+	"cm70_lockup",
+	"cm70_swreq",
+	"fccu",
+	"jtag_sw",
+	"ele",
+	"tempsense",
+	"wdog1",
+	"wdog2",
+	"wdog3",
+	"wdog4",
+	"wdog5",
+	"jtag",
+	"wdog6",
+	"wdog7",
+	"wdog8",
+	"wo_netc", "cm33s_lockup", "cm33s_swreq", "cm71_lockup", "cm71_swreq", "cm33_exc",
+	"bbm", "sw", "sm_err", "fusa_sreco", "pmic", "unused",
+	"unused", "unused",
+	"por"
+};
+
+int get_reset_reason(bool sys, bool lm)
+{
+	struct scmi_imx_misc_reset_reason_in in = {
+		.flags = MISC_REASON_FLAG_SYSTEM,
+	};
+
+	struct scmi_imx_misc_reset_reason_out out = { 0 };
+	struct scmi_msg msg = {
+		.protocol_id = SCMI_PROTOCOL_ID_IMX_MISC,
+		.message_id = SCMI_IMX_MISC_RESET_REASON,
+		.in_msg = (u8 *)&in,
+		.in_msg_sz = sizeof(in),
+		.out_msg = (u8 *)&out,
+		.out_msg_sz = sizeof(out),
+	};
+	int ret;
+
+	struct udevice *dev;
+	char **rst;
+
+	if (is_imx94())
+		rst = rst_string_imx94;
+	else
+		rst = rst_string;
+
+	ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+	if (ret)
+		return ret;
+
+	if (sys) {
+		ret = devm_scmi_process_msg(dev, &msg);
+		if (out.status) {
+			printf("%s:%d for SYS\n", __func__, out.status);
+			return ret;
+		}
+
+		if (out.bootflags & MISC_BOOT_FLAG_VLD) {
+			printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n",
+			       rst[out.bootflags & MISC_BOOT_FLAG_REASON],
+			       out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
+			       FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
+			       out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
+			       FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
+			       );
+		}
+		if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
+			printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n",
+			       rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON],
+			       out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
+			       FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1,
+			       out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
+			       FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1
+			       );
+		}
+	}
+
+	if (lm) {
+		in.flags = 0;
+		memset(&out, 0, sizeof(struct scmi_imx_misc_reset_reason_out));
+
+		ret = devm_scmi_process_msg(dev, &msg);
+		if (out.status) {
+			printf("%s:%d for LM\n", __func__, out.status);
+			return ret;
+		}
+
+		if (out.bootflags & MISC_BOOT_FLAG_VLD) {
+			printf("LM Boot reason: %s, origin: %ld, errid: %ld\n",
+			       rst[out.bootflags & MISC_BOOT_FLAG_REASON],
+			       out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
+			       FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
+			       out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
+			       FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
+			       );
+		}
+
+		if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
+			printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n",
+			       rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON],
+			       out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
+			       FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1,
+			       out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
+			       FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1
+			       );
+		}
+	}
+
+	return 0;
+}
+
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case MXC_CPU_IMX95:
-		return "95";/* iMX95 FULL */
+	case SCMI_CPU:
+		return IMX_PLAT_STR;
 	default:
 		return "??";
 	}
@@ -553,6 +744,10 @@ int arch_cpu_init(void)
 		gpio_reset(GPIO3_BASE_ADDR);
 		gpio_reset(GPIO4_BASE_ADDR);
 		gpio_reset(GPIO5_BASE_ADDR);
+#ifdef CONFIG_IMX94
+		gpio_reset(GPIO6_BASE_ADDR);
+		gpio_reset(GPIO7_BASE_ADDR);
+#endif
 	}
 
 	return 0;
diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c
index 00173e6836b..48d578e7d6f 100644
--- a/arch/arm/mach-k3/am62ax/am62a7_init.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
@@ -218,6 +218,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 	u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
 			    MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
 
+	if (bootindex != K3_PRIMARY_BOOTMODE) {
+		pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n");
+		return MMCSD_MODE_FS;
+	}
+
 	switch (bootmode) {
 	case BOOT_DEVICE_EMMC:
 		if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c
index 44a2d445d24..aebd5200b0d 100644
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -264,6 +264,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 	u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
 			    MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
 
+	if (bootindex != K3_PRIMARY_BOOTMODE) {
+		pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n");
+		return MMCSD_MODE_FS;
+	}
+
 	switch (bootmode) {
 	case BOOT_DEVICE_EMMC:
 		if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
index a422919fab1..14f93ac998f 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -294,15 +294,6 @@ void board_init_f(ulong dummy)
 	}
 	spl_enable_cache();
 
-	if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
-	    spl_boot_device() == BOOT_DEVICE_ETHERNET) {
-		struct udevice *cpswdev;
-
-		if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
-						&cpswdev))
-			printf("Failed to probe am65_cpsw_nuss driver\n");
-	}
-
 	fixup_a53_cpu_freq_by_speed_grade();
 }
 
@@ -314,6 +305,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 	u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
 			    MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
 
+	if (bootindex != K3_PRIMARY_BOOTMODE) {
+		pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n");
+		return MMCSD_MODE_FS;
+	}
+
 	switch (bootmode) {
 	case BOOT_DEVICE_EMMC:
 		if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c
index 41812b7dbf7..219798315db 100644
--- a/arch/arm/mach-k3/am64x/am642_init.c
+++ b/arch/arm/mach-k3/am64x/am642_init.c
@@ -263,13 +263,6 @@ void board_init_f(ulong dummy)
 	if (ret)
 		panic("DRAM init failed: %d\n", ret);
 #endif
-	if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
-	    spl_boot_device() == BOOT_DEVICE_ETHERNET) {
-		struct udevice *cpswdev;
-
-		if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev))
-			printf("Failed to probe am65_cpsw_nuss driver\n");
-	}
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c
index ce8ae941be6..bf8e1a5cb44 100644
--- a/arch/arm/mach-k3/am64x/boot.c
+++ b/arch/arm/mach-k3/am64x/boot.c
@@ -103,3 +103,39 @@ u32 get_boot_device(void)
 
 	return bootmedia;
 }
+
+const char *get_reset_reason(void)
+{
+	u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC);
+
+	/* After reading reset source register, software must clear it */
+	if (reset_reason)
+		writel(reset_reason, CTRLMMR_MCU_RST_SRC);
+
+	if (reset_reason == 0 ||
+	    (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN |
+			    RST_SRC_SW_MAIN_POR_FROM_MCU)))
+		return "POR";
+
+	if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR))
+		return "ESM";
+
+	if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN |
+			    RST_SRC_SW_MAIN_WARM_FROM_MCU  |
+			    RST_SRC_SW_MCU_WARM_RST))
+		return "RST";
+
+	if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST))
+		return "DMSC";
+
+	if (reset_reason & RST_SRC_DEBUG_RST)
+		return "JTAG";
+
+	if (reset_reason & RST_SRC_THERMAL_RST)
+		return "THERMAL";
+
+	if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN))
+		return "PIN";
+
+	return "UNKNOWN";
+}
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index f8c53b286eb..5483ac9906c 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -322,17 +322,6 @@ void spl_board_prepare_for_linux(void)
 
 int misc_init_r(void)
 {
-	if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) {
-		struct udevice *dev;
-		int ret;
-
-		ret = uclass_get_device_by_driver(UCLASS_MISC,
-						  DM_DRIVER_GET(am65_cpsw_nuss),
-						  &dev);
-		if (ret)
-			printf("Failed to probe am65_cpsw_nuss driver\n");
-	}
-
 	if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) {
 		struct udevice *dev;
 		int ret;
diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c
index 2777354c6ab..1e6786f6c20 100644
--- a/arch/arm/mach-k3/common_fdt.c
+++ b/arch/arm/mach-k3/common_fdt.c
@@ -140,7 +140,9 @@ int fdt_fixup_reserved(void *blob, const char *name,
 			return -EINVAL;
 		if (!strncmp(node_name, name, strlen(name))) {
 			/* Read out old size first */
-			addr = fdtdec_get_addr_size(blob, subnode, "reg", &size);
+			addr = fdtdec_get_addr_size_auto_parent(
+				blob, nodeoffset, subnode, "reg", 0, &size,
+				false);
 			if (addr == FDT_ADDR_T_NONE)
 				return -EINVAL;
 			new_size = size;
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index 105b42986de..2717da07690 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -46,6 +46,24 @@
 /* Use Last 2K as Scratch pad */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x7019f800
 
+/* Reset Reason Detection */
+#define CTRLMMR_MCU_RST_SRC			(MCU_CTRL_MMR0_BASE + 0x18178)
+
+/* Reset causes by bit mapping */
+#define RST_SRC_SAFETY_ERR			BIT(31)
+#define RST_SRC_MAIN_ESM_ERR			BIT(30)
+#define RST_SRC_SW_MAIN_POR_FROM_MAIN		BIT(25)
+#define RST_SRC_SW_MAIN_POR_FROM_MCU		BIT(24)
+#define RST_SRC_SW_MAIN_WARM_FROM_MAIN		BIT(21)
+#define RST_SRC_SW_MAIN_WARM_FROM_MCU		BIT(20)
+#define RST_SRC_SW_MCU_WARM_RST			BIT(16)
+#define RST_SRC_SMS_WARM_RST			BIT(13)
+#define RST_SRC_SMS_COLD_RST			BIT(12)
+#define RST_SRC_DEBUG_RST			BIT(8)
+#define RST_SRC_THERMAL_RST			BIT(4)
+#define RST_SRC_MAIN_RESET_PIN			BIT(2)
+#define RST_SRC_MCU_RESET_PIN			BIT(0)
+
 #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
 
 #define AM64X_DEV_RTI8			127
diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h
index d8fae2c8b45..47a61281d94 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h
@@ -12,6 +12,7 @@
 #define BOOT_DEVICE_OSPI		0x01
 #define BOOT_DEVICE_QSPI		0x02
 #define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_CPGMAC		0x04
 #define BOOT_DEVICE_ETHERNET		0x04
 #define BOOT_DEVICE_I2C			0x06
 #define BOOT_DEVICE_UART		0x07
diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h
index d481a46c675..3814dc95d01 100644
--- a/arch/arm/mach-k3/include/mach/j784s4_spl.h
+++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h
@@ -44,4 +44,6 @@
 #define K3_PRIMARY_BOOTMODE		0x0
 #define K3_BACKUP_BOOTMODE		0x1
 
+#define BOOT_DEVICE_CPGMAC              0x04
+
 #endif
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c
index bc62d1d0d08..b552a2be74d 100644
--- a/arch/arm/mach-k3/r5/am62px/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <[email protected]>.
  *
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout1_clk10",
 };
 
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+	"postdiv4_16ff_main_2_hsdivout5_clk",
+	"postdiv4_16ff_main_0_hsdivout6_clk",
+	"board_0_cp_gemac_cpts0_rft_clk_out",
+	NULL,
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
 static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
 	"postdiv4_16ff_main_0_hsdivout5_clk",
 	"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
 	"board_0_cp_gemac_cpts0_rft_clk_out",
 	"hsdiv4_16fft_main_1_hsdivout3_clk",
 	"postdiv4_16ff_main_2_hsdivout6_clk",
-	NULL,
-	NULL,
+	"cpsw_3guss_am67_main_0_cpts_genf0",
+	"cpsw_3guss_am67_main_0_cpts_genf1",
 	NULL,
 	NULL,
 	NULL,
@@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
 	CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
 	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
 	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = {
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+	DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
 	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
 	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
 	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
 	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
 	DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
 	DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
@@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
 	DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+	DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
 	DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c
index 3cc211ea202..63e6beb4d57 100644
--- a/arch/arm/mach-k3/r5/am62px/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62px/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <[email protected]>.
  *
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
 	[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
 	[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
 	[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
-	[9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
-	[10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
-	[11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
-	[12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
-	[13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+	[9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
+	[10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
+	[11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]),
+	[12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+	[13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+	[14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(36, &soc_lpsc_list[8]),
 	PSC_DEV(102, &soc_lpsc_list[8]),
 	PSC_DEV(146, &soc_lpsc_list[8]),
-	PSC_DEV(166, &soc_lpsc_list[9]),
-	PSC_DEV(135, &soc_lpsc_list[10]),
-	PSC_DEV(170, &soc_lpsc_list[11]),
-	PSC_DEV(177, &soc_lpsc_list[12]),
-	PSC_DEV(55, &soc_lpsc_list[13]),
+	PSC_DEV(13, &soc_lpsc_list[9]),
+	PSC_DEV(166, &soc_lpsc_list[10]),
+	PSC_DEV(135, &soc_lpsc_list[11]),
+	PSC_DEV(170, &soc_lpsc_list[12]),
+	PSC_DEV(177, &soc_lpsc_list[13]),
+	PSC_DEV(55, &soc_lpsc_list[14]),
 };
 
 const struct ti_k3_pd_platdata am62px_pd_platdata = {
diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
index 0c5c321c1eb..0130c9c4b86 100644
--- a/arch/arm/mach-k3/r5/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Dave Gerlach <[email protected]>.
  *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
 	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
 };
 
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+	"j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+	"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv3_16fft_main_0_hsdivout6_clk",
+	"board_0_mcu_cpts0_rft_clk_out",
+	"board_0_cpts0_rft_clk_out",
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
 static const char * const mcu_usart_clksel_out0_parents[] = {
 	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
 	"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
 	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
 	CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+	CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+	CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
 	CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 	CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
@@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 	DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 	DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"),
+	DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"),
+	DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"),
+	DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(29, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"),
+	DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"),
+	DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 	DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
 	DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
 	DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
@@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 	DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
+	DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
 	DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
 	DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
 	DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
@@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 	DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
 	DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+	DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
 	DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
 	DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
@@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata j721s2_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 105,
+	.clk_list_cnt = ARRAY_SIZE(clk_list),
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 124,
+	.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
 };
diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
index df70c5e5d7c..b78550707c5 100644
--- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Dave Gerlach <[email protected]>.
  *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 };
 
 static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(29, &soc_lpsc_list[0]),
 	PSC_DEV(35, &soc_lpsc_list[0]),
 	PSC_DEV(108, &soc_lpsc_list[0]),
 	PSC_DEV(109, &soc_lpsc_list[0]),
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
index b4f27af333d..238d57d0aa0 100644
--- a/arch/arm/mach-k3/r5/j722s/clk-data.c
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <[email protected]>.
  *
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout1_clk",
 };
 
-static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
-	"postdiv4_16ff_main_0_hsdivout5_clk",
-	"hsdiv4_16fft_main_2_hsdivout2_clk",
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+	"postdiv4_16ff_main_2_hsdivout5_clk",
+	"postdiv4_16ff_main_0_hsdivout6_clk",
+	"board_0_cp_gemac_cpts0_rft_clk_out",
+	NULL,
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
 };
 
 static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
@@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
 	"board_0_cp_gemac_cpts0_rft_clk_out",
 	"hsdiv4_16fft_main_1_hsdivout3_clk",
 	"postdiv4_16ff_main_2_hsdivout6_clk",
-	NULL,
-	NULL,
+	"cpsw_3guss_am67_main_0_cpts_genf0",
+	"cpsw_3guss_am67_main_0_cpts_genf1",
 	NULL,
 	NULL,
 	NULL,
@@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
 	CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
 	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
 	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
-	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
+	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
 	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
@@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+	DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
 	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
 	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
 	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
 	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
-	DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-	DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
-	DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
-	DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
 	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
 	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
 	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
@@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
 	DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+	DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
 	DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
index 59176c98999..d6832266884 100644
--- a/arch/arm/mach-k3/r5/j722s/dev-data.c
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <[email protected]>.
  *
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
 
 static struct ti_lpsc soc_lpsc_list[] = {
 	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
-	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
-	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
-	[3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
+	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+	[3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
 	[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
-	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
 	[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
 	[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
 };
@@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(61, &soc_lpsc_list[0]),
 	PSC_DEV(178, &soc_lpsc_list[1]),
 	PSC_DEV(179, &soc_lpsc_list[2]),
-	PSC_DEV(57, &soc_lpsc_list[3]),
-	PSC_DEV(58, &soc_lpsc_list[4]),
-	PSC_DEV(161, &soc_lpsc_list[5]),
-	PSC_DEV(75, &soc_lpsc_list[6]),
-	PSC_DEV(36, &soc_lpsc_list[7]),
-	PSC_DEV(102, &soc_lpsc_list[7]),
-	PSC_DEV(146, &soc_lpsc_list[7]),
+	PSC_DEV(58, &soc_lpsc_list[3]),
+	PSC_DEV(161, &soc_lpsc_list[4]),
+	PSC_DEV(75, &soc_lpsc_list[5]),
+	PSC_DEV(36, &soc_lpsc_list[6]),
+	PSC_DEV(102, &soc_lpsc_list[6]),
+	PSC_DEV(146, &soc_lpsc_list[6]),
+	PSC_DEV(13, &soc_lpsc_list[7]),
 	PSC_DEV(166, &soc_lpsc_list[8]),
 	PSC_DEV(135, &soc_lpsc_list[9]),
 	PSC_DEV(170, &soc_lpsc_list[10]),
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 97d969271ec..24780eb6562 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = {
 	"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
 };
 
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv3_16fft_main_0_hsdivout6_clk",
+	"board_0_mcu_cpts0_rft_clk_out",
+	"board_0_cpts0_rft_clk_out",
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
 static const char * const mcu_usart_clksel_out0_parents[] = {
 	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
 	"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = {
 	"board_0_hfosc1_clk_out",
 };
 
+static const char * const mcu_clkout_mux_out0_parents[] = {
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+};
+
 static const char * const usb0_refclk_sel_out0_parents[] = {
 	"gluelogic_hfosc0_clkout",
 	"board_0_hfosc1_clk_out",
@@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = {
 	"board_0_mmc1_clk_out",
 };
 
-static const char * const mcu_clkout_mux_out0_parents[] = {
-	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
-	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
-};
-
 static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
 	"main_pll_hfosc_sel_out0",
 	"hsdiv4_16fft_main_0_hsdivout0_clk",
@@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
 	CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
 	CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+	CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
 	CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 	CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 	CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
@@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
 	DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"),
+	DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"),
+	DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"),
+	DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(63, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"),
+	DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"),
 	DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
 	DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
 	DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
 	DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+	DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
 	DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 	DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 	DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 	DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+	DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
 	DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c
index b32b4ba9588..19901821225 100644
--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c
@@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 };
 
 static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(63, &soc_lpsc_list[0]),
 	PSC_DEV(35, &soc_lpsc_list[0]),
 	PSC_DEV(160, &soc_lpsc_list[0]),
 	PSC_DEV(161, &soc_lpsc_list[0]),
diff --git a/arch/arm/mach-k3/schema.yaml b/arch/arm/mach-k3/schema.yaml
index c8dd2e79e7d..8c4691f24ed 100644
--- a/arch/arm/mach-k3/schema.yaml
+++ b/arch/arm/mach-k3/schema.yaml
@@ -344,7 +344,7 @@ properties:
             resasg_entries:
                 type: array
                 minItems: 0
-                maxItems: 468
+                maxItems: 586
                 items:
                     type: object
                     properties:
@@ -420,7 +420,7 @@ properties:
             resasg_entries:
                 type: array
                 minItems: 0
-                maxItems: 468
+                maxItems: 586
                 items:
                     type: object
                     properties:
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 3dce9b30898..1bfd120adc4 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -242,30 +242,38 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen)
 
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
+	const char *bootrom_ofpath = board_spl_was_booted_from();
 	void *blob = spl_image_fdt_addr(spl_image);
 	char boot_ofpath[512];
 	int chosen, ret;
 
-	/*
-	 * Inject the ofpath of the device the full U-Boot (or Linux in
-	 * Falcon-mode) was booted from into the FDT, if a FDT has been
-	 * loaded at the same time.
-	 */
 	if (!blob)
 		return;
 
-	ret = spl_decode_boot_device(spl_image->boot_device, boot_ofpath, sizeof(boot_ofpath));
-	if (ret) {
-		pr_err("%s: could not map boot_device to ofpath: %d\n", __func__, ret);
-		return;
-	}
-
 	chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
 	if (chosen < 0) {
 		pr_err("%s: could not find/create '/chosen'\n", __func__);
 		return;
 	}
-	fdt_setprop_string(blob, chosen,
-			   "u-boot,spl-boot-device", boot_ofpath);
+
+	/*
+	 * Inject the ofpath of the device the full U-Boot (or Linux in
+	 * Falcon-mode) was booted from into the FDT.
+	 */
+	ret = spl_decode_boot_device(spl_image->boot_device, boot_ofpath, sizeof(boot_ofpath));
+	if (ret)
+		pr_err("%s: could not map boot_device to ofpath: %d\n", __func__, ret);
+	else
+		fdt_setprop_string(blob, chosen,
+				   "u-boot,spl-boot-device", boot_ofpath);
+
+	/*
+	 * Inject the ofpath of the device the BootROM loaded the very first
+	 * stage from into the FDT.
+	 */
+	if (!bootrom_ofpath)
+		pr_err("%s: could not map BootROM boot device to ofpath\n", __func__);
+	else
+		fdt_setprop_string(blob, chosen, "bootsource", bootrom_ofpath);
 }
 #endif
diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk
index e7e4c9a1181..266d2e3a777 100644
--- a/arch/arm/mach-sc5xx/config.mk
+++ b/arch/arm/mach-sc5xx/config.mk
@@ -12,5 +12,7 @@ ifdef CONFIG_XPL_BUILD
 INPUTS-y += $(obj)/u-boot-spl.ldr
 endif
 
+INPUTS-y += u-boot.ldr
+
 LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE)
 LDR_FLAGS += --use-vmas
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 9ef82cf46c0..b8f2f73e283 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -98,6 +98,8 @@
 #define SOC64_HANDOFF_IOCTL_LEN			96
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #define SOC64_HANDOFF_FPGA_LEN			42
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_FPGA_LEN			44
 #else
 #define SOC64_HANDOFF_FPGA_LEN			40
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 2099c51b682..1a461de4819 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -398,10 +398,8 @@ int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
 int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
 int mbox_init(void);
 
-#ifdef CONFIG_CADENCE_QSPI
 int mbox_qspi_close(void);
 int mbox_qspi_open(void);
-#endif
 
 int mbox_reset_cold(void);
 int mbox_hps_stage_notify(u32 execution_stage);
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 054a28d845d..f768a3a55cb 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
 #define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
 #define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
+#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0	0x1F0
 #define SYSMGR_SOC64_MPFE_CONFIG		0x228
 #define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
 #define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
@@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void);
 #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK	BIT(0)
 #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK	BIT(0)
 #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
+
+/*
+ * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0
+ * Bits[14:13] Port Overcurrent
+ * Bit[12] Reset Pulse Override
+ */
+#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR	GENMASK(14, 13)
+#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR	BIT(12)
+#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR	1
+/* BIT 1 actually reflects PIPE power present signal */
+#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1	2
 #else
 #define SYSMGR_SOC64_NAND_AXUSER		0x5c
 #define SYSMGR_SOC64_DMA_L3MASTER		0x74
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index c442af02888..7e0f3875b7c 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -214,10 +214,7 @@ int qspi_flash_software_reset(void)
 	/* Get the flash info */
 	ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
 				     CONFIG_SF_DEFAULT_CS,
-				     CONFIG_SF_DEFAULT_SPEED,
-				     CONFIG_SF_DEFAULT_MODE,
 				     &flash);
-
 	if (ret) {
 		debug("Failed to initialize SPI flash at ");
 		debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS,
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
index b212a94b321..a531030f5be 100644
--- a/arch/arm/mach-socfpga/smc_api.c
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -57,6 +57,7 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
 			 resp, ARRAY_SIZE(resp));
 
 	if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+		invalidate_dcache_range((uintptr_t)resp_buf, (uintptr_t)(resp_buf + *resp_buf_len));
 		if (!resp[0])
 			*resp_buf_len = resp[1];
 	}
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c
index 4b42158be9d..913f93c8f94 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -8,9 +8,29 @@
 #include <asm/arch/system_manager.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <linux/bitfield.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+/*
+ * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse
+ * generation and setting PORT_OVERCURRENT bit so that until we turn on the
+ * Vbus, it doesn't give false information about Vbus to the HPS controller.
+ */
+static void sysmgr_config_usb3(void)
+{
+	u32 reg_val = 0;
+
+	reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
+	reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR,
+				SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR);
+	reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR,
+				SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1);
+	writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
+}
+#endif
+
 /*
  * Configure all the pin muxes
  */
@@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void)
 {
 	populate_sysmgr_pinmux();
 	populate_sysmgr_fpgaintf_module();
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	sysmgr_config_usb3();
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-stm32mp/include/mach/rif.h b/arch/arm/mach-stm32mp/include/mach/rif.h
index 10b22108120..4f51313980d 100644
--- a/arch/arm/mach-stm32mp/include/mach/rif.h
+++ b/arch/arm/mach-stm32mp/include/mach/rif.h
@@ -8,19 +8,53 @@
 
 #include <linux/types.h>
 
+#if IS_ENABLED(CONFIG_STM32MP21X) || IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)
 /**
- * stm32_rifsc_check_access - Check RIF accesses for given device node
+ * stm32_rifsc_grant_access_by_id - Grant RIFSC access for a given peripheral using its ID
  *
- * @device_node		Node of the device for which the accesses are checked
+ * @device_node Node of the peripheral
+ * @id ID of the peripheral of which access should be granted
  */
-int stm32_rifsc_check_access(ofnode device_node);
+int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id);
 
 /**
- * stm32_rifsc_check_access - Check RIF accesses for given id
+ * stm32_rifsc_grant_access_by_id - Grant RIFSC access for a given peripheral using its node
  *
- * @device_node		Node of the device to get a reference on RIFSC
- * @id			ID of the resource to check
+ * @id node of the peripheral of which access should be granted
  */
-int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id);
+int stm32_rifsc_grant_access(ofnode device_node);
 
+/**
+ * stm32_rifsc_release_access_by_id - Release RIFSC access for a given peripheral using its ID
+ *
+ * @device_node Node of the peripheral
+ * @id ID of the peripheral of which access should be released
+ */
+void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id);
+
+/**
+ * stm32_rifsc_release_access_by_id - Release RIFSC access for a given peripheral using its node
+ *
+ * @id node of the peripheral of which access should be released
+ */
+void stm32_rifsc_release_access(ofnode device_node);
+#else
+static inline int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id)
+{
+	return -EACCES;
+}
+
+static inline int stm32_rifsc_grant_access(ofnode device_node)
+{
+	return -EACCES;
+}
+
+static inline void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id)
+{
+}
+
+static inline void stm32_rifsc_release_access(ofnode device_node)
+{
+}
+#endif
 #endif /* MACH_RIF_H*/
diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
index 50dececf77b..f8f67af4449 100644
--- a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
+++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c
@@ -61,42 +61,41 @@ struct stm32_rifsc_child_plat {
 	u32 domain_id;
 };
 
-static bool stm32_rif_is_semaphore_available(void *base, u32 id)
+static bool stm32_rif_is_semaphore_available(void *addr)
 {
-	void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
-
 	return !(readl(addr) & SEMCR_MUTEX);
 }
 
-static int stm32_rif_acquire_semaphore(void *base, u32 id)
+static int stm32_rifsc_acquire_semaphore(void *base, u32 id)
 {
 	void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
 
 	/* Check that the semaphore is available */
-	if (!stm32_rif_is_semaphore_available(base, id))
+	if (!stm32_rif_is_semaphore_available(addr) &&
+	    FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1))
 		return -EACCES;
 
 	setbits_le32(addr, SEMCR_MUTEX);
 
 	/* Check that CID1 has the semaphore */
-	if (stm32_rif_is_semaphore_available(base, id) ||
+	if (stm32_rif_is_semaphore_available(addr) ||
 	    FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1))
 		return -EACCES;
 
 	return 0;
 }
 
-static int stm32_rif_release_semaphore(void *base, u32 id)
+static int stm32_rifsc_release_semaphore(void *base, u32 id)
 {
 	void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
 
-	if (stm32_rif_is_semaphore_available(base, id))
+	if (stm32_rif_is_semaphore_available(addr))
 		return 0;
 
 	clrbits_le32(addr, SEMCR_MUTEX);
 
 	/* Ok if another compartment takes the semaphore before the check */
-	if (!stm32_rif_is_semaphore_available(base, id) &&
+	if (!stm32_rif_is_semaphore_available(addr) &&
 	    FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1))
 		return -EACCES;
 
@@ -105,11 +104,10 @@ static int stm32_rif_release_semaphore(void *base, u32 id)
 
 static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args)
 {
-	int ret;
+	int ret = ofnode_parse_phandle_with_args(node, "access-controllers",
+						 "#access-controller-cells", 0,
+						 0, args);
 
-	ret = ofnode_parse_phandle_with_args(node, "access-controllers",
-					     "#access-controller-cells", 0,
-					     0, args);
 	if (ret) {
 		log_debug("failed to parse access-controller (%d)\n", ret);
 		return ret;
@@ -170,8 +168,8 @@ static int rifsc_check_access(void *base, u32 id)
 			log_debug("Not in semaphore whitelist for peripheral %d\n", id);
 			return -EACCES;
 		}
-		if (!stm32_rif_is_semaphore_available(base, id) &&
-		    !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) {
+		if (!stm32_rif_is_semaphore_available(base + RIFSC_RISC_PER0_SEMCR(id)) &&
+		    !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & RIF_CID1)) {
 			log_debug("Semaphore unavailable for peripheral %d\n", id);
 			return -EACCES;
 		}
@@ -187,22 +185,44 @@ skip_cid_check:
 	return 0;
 }
 
-int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id)
+int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id)
 {
 	struct ofnode_phandle_args args;
+	u32 cid_reg_value;
+	void *rifsc_base;
 	int err;
 
-	if (id >= STM32MP25_RIFSC_ENTRIES)
-		return -EINVAL;
-
 	err = rifsc_parse_access_controller(device_node, &args);
 	if (err)
+		panic("Failed to parse access-controllers property\n");
+
+	rifsc_base = (void *)ofnode_get_addr(args.node);
+
+	err = rifsc_check_access(rifsc_base, id);
+	if (err)
 		return err;
 
-	return rifsc_check_access((void *)ofnode_get_addr(args.node), id);
+	cid_reg_value = readl(rifsc_base + RIFSC_RISC_PER0_CIDCFGR(id));
+
+	/*
+	 * If the peripheral is in semaphore mode, take the semaphore so that
+	 * the CID1 has the ownership.
+	 */
+	if (cid_reg_value & CIDCFGR_SEMEN &&
+	    (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
+		err = stm32_rifsc_acquire_semaphore(rifsc_base, id);
+		if (err) {
+			pr_err("Couldn't acquire RIF semaphore for peripheral %d (%d)\n",
+			       id, err);
+			return err;
+		}
+		pr_debug("Acquiring RIF semaphore for peripheral %d\n", id);
+	}
+
+	return 0;
 }
 
-int stm32_rifsc_check_access(ofnode device_node)
+int stm32_rifsc_grant_access(ofnode device_node)
 {
 	struct ofnode_phandle_args args;
 	int err;
@@ -211,58 +231,60 @@ int stm32_rifsc_check_access(ofnode device_node)
 	if (err)
 		return err;
 
-	return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]);
+	return stm32_rifsc_grant_access_by_id(device_node, args.args[0]);
+
 }
 
-static int stm32_rifsc_child_pre_probe(struct udevice *dev)
+void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id)
 {
-	struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
-	struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+	struct ofnode_phandle_args args;
 	u32 cid_reg_value;
+	void *rifsc_base;
 	int err;
-	u32 id = child_plat->domain_id;
 
-	cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
+	err = rifsc_parse_access_controller(device_node, &args);
+	if (err)
+		panic("Failed to parse access-controllers property\n");
 
-	/*
-	 * If the peripheral is in semaphore mode, take the semaphore so that
-	 * the CID1 has the ownership.
-	 */
+	rifsc_base = (void *)ofnode_get_addr(args.node);
+
+	cid_reg_value = readl(rifsc_base + RIFSC_RISC_PER0_CIDCFGR(id));
+
+	/* If the peripheral is in semaphore mode, release it if we have the ownership */
 	if (cid_reg_value & CIDCFGR_SEMEN &&
 	    (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
-		err = stm32_rif_acquire_semaphore(plat->base, id);
+		err = stm32_rifsc_release_semaphore(rifsc_base, id);
 		if (err) {
-			dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n",
-				id, err);
-			return err;
+			panic("Couldn't release RIF semaphore for peripheral %d (%d)\n", id, err);
 		}
-		dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id);
+		pr_debug("Releasing RIF semaphore for peripheral %d\n", id);
 	}
+}
 
-	return 0;
+void stm32_rifsc_release_access(ofnode device_node)
+{
+	struct ofnode_phandle_args args;
+	int err;
+
+	err = rifsc_parse_access_controller(device_node, &args);
+	if (err)
+		panic("Failed to parse access-controllers property\n");
+
+	stm32_rifsc_release_access_by_id(device_node, args.args[0]);
 }
 
-static int stm32_rifsc_child_post_remove(struct udevice *dev)
+static int stm32_rifsc_child_pre_probe(struct udevice *dev)
 {
-	struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
 	struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
-	u32 cid_reg_value;
-	int err;
-	u32 id = child_plat->domain_id;
 
-	cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
+	return stm32_rifsc_grant_access_by_id(dev_ofnode(dev), child_plat->domain_id);
+}
 
-	/*
-	 * If the peripheral is in semaphore mode, release the semaphore so that
-	 * there's no ownership.
-	 */
-	if (cid_reg_value & CIDCFGR_SEMEN &&
-	    (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
-		err = stm32_rif_release_semaphore(plat->base, id);
-		if (err)
-			dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n",
-				id, err);
-	}
+static int stm32_rifsc_child_post_remove(struct udevice *dev)
+{
+	struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
+
+	stm32_rifsc_release_access_by_id(dev_ofnode(dev), child_plat->domain_id);
 
 	return 0;
 }
diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c
index 3a24cbfff3b..a2bf52c5adc 100644
--- a/arch/powerpc/lib/spl.c
+++ b/arch/powerpc/lib/spl.c
@@ -9,8 +9,7 @@
 #include <linux/compiler.h>
 
 /*
- * This function jumps to an image with argument. Normally an FDT or ATAGS
- * image.
+ * This function jumps to an image with argument, usually an FDT.
  */
 #ifdef CONFIG_SPL_OS_BOOT
 void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 04eb0e6f23c..265b5320777 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -23,8 +23,8 @@ config TARGET_K230_CANMV
 config TARGET_LICHEERV_NANO
 	bool "Support LicheeRV Nano Board"
 
-config TARGET_MICROCHIP_ICICLE
-	bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_MICROCHIP_GENERIC
+	bool "Support Microchip PolarFire-SoC Boards"
 
 config TARGET_MILKV_DUO
 	bool "Support Milk-v Duo Board"
@@ -108,7 +108,7 @@ source "board/andestech/voyager/Kconfig"
 source "board/aspeed/ibex_ast2700/Kconfig"
 source "board/canaan/k230_canmv/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
-source "board/microchip/mpfs_icicle/Kconfig"
+source "board/microchip/mpfs_generic/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
@@ -343,10 +343,27 @@ endmenu
 
 config RISCV_ISA_A
 	bool "Standard extension for Atomic Instructions"
+	depends on RISCV_ISA_ZAAMO && RISCV_ISA_ZALRSC
 	default y
 	help
 	  Adds "A" to the ISA string passed to the compiler.
 
+config RISCV_ISA_ZAAMO
+	bool "Standard extension for Atomic Memory Operations"
+	default y
+	help
+	  Indicates the platform supports Zaamo extension for atomic memory
+	  operations. Hand-written Assembly routines won't use AMO
+	  instructions if set to n.
+
+config RISCV_ISA_ZALRSC
+	bool "Standard extension for LR/SC instructions"
+	default y
+	help
+	  Indicates the platform supports Zalrsc extension for load-reserved
+	  and store-conditional isntructions. Hand-written assembly routines
+	  won't use LR/SC instructions if set to n.
+
 config RISCV_ISA_ZICBOM
 	bool "Zicbom support"
 	depends on !SYS_DISABLE_DCACHE_OPS
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6f80f4a7108..fdda6da1df3 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -11,7 +11,12 @@ ifeq ($(CONFIG_ARCH_RV32I),y)
 	ARCH_BASE = rv32im
 	ABI_BASE = ilp32
 endif
-ifeq ($(CONFIG_RISCV_ISA_A),y)
+# GCC starts to recognize "Zaamo" and "Zalrsc" from version 15, which is quite
+# recent. We don't bother checking the exact compiler version, but pass "A"
+# extension for -march as long as one of "Zaamo" or "Zalrsc" is available.
+ifeq ($(findstring y,$(CONFIG_RISCV_ISA_A)	\
+		     $(CONFIG_RISCV_ISA_ZAAMO)	\
+		     $(CONFIG_RISCV_ISA_ZALRSC)),y)
 	ARCH_A = a
 endif
 ifeq ($(CONFIG_RISCV_ISA_F),y)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 7bafdfd390a..6324ff585d4 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -151,9 +151,16 @@ call_harts_early_init:
 	 */
 	la	t0, hart_lottery
 	li	t1, 1
+#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
 #else
+	lr.w	s2, (t0)
+	bnez	s2, wait_for_gd_init
+	sc.w	s2, t1, (t0)
+	bnez	s2, wait_for_gd_init
+#endif
+#else
 	/*
 	 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
 	 * encounters a pending IPI on boot it is liable to jump to whatever
@@ -177,7 +184,12 @@ call_harts_early_init:
 #if !CONFIG_IS_ENABLED(XIP)
 #ifdef CONFIG_AVAILABLE_HARTS
 	la	t0, available_harts_lock
+#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
 	amoswap.w.rl zero, zero, 0(t0)
+#else
+	fence	rw, w
+	sw	zero, 0(t0)
+#endif
 #endif
 
 wait_for_gd_init:
@@ -190,7 +202,14 @@ wait_for_gd_init:
 #ifdef CONFIG_AVAILABLE_HARTS
 	la	t0, available_harts_lock
 	li	t1, 1
-1:	amoswap.w.aq t1, t1, 0(t0)
+1:
+#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
+	amoswap.w.aq t1, t1, 0(t0)
+#else
+	lr.w.aq	t1, 0(t0)
+	bnez	t1, 1b
+	sc.w.rl t1, t1, 0(t0)
+#endif
 	bnez	t1, 1b
 
 	/* register available harts in the available_harts mask */
@@ -200,7 +219,12 @@ wait_for_gd_init:
 	or	t2, t2, t1
 	SREG	t2, GD_AVAILABLE_HARTS(gp)
 
+#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
 	amoswap.w.rl zero, zero, 0(t0)
+#else
+	fence	rw, w
+	sw	zero, 0(t0)
+#endif
 #endif
 
 	/*
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig
index c73462c04b8..a02f5f24906 100644
--- a/arch/riscv/cpu/th1520/Kconfig
+++ b/arch/riscv/cpu/th1520/Kconfig
@@ -21,3 +21,4 @@ config THEAD_TH1520
 	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
+	imply OF_UPSTREAM
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index a637727b76b..9b347fc3b50 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -12,7 +12,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi
deleted file mode 100644
index 049b0a7ce28..00000000000
--- a/arch/riscv/dts/jh7110-common-u-boot.dtsi
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-u-boot.dtsi"
-/ {
-	aliases {
-		spi0 = &qspi;
-	};
-
-	chosen {
-		bootph-pre-ram;
-	};
-
-	firmware {
-		spi0 = &qspi;
-		bootph-pre-ram;
-	};
-
-	memory@40000000 {
-		bootph-pre-ram;
-	};
-};
-
-&uart0 {
-	bootph-pre-ram;
-	reg-offset = <0>;
-	current-speed = <115200>;
-};
-
-&mmc0 {
-	bootph-pre-ram;
-};
-
-&mmc1 {
-	bootph-pre-ram;
-};
-
-&qspi {
-	bootph-pre-ram;
-
-	flash@0 {
-		bootph-pre-ram;
-		cdns,read-delay = <2>;
-		spi-max-frequency = <100000000>;
-	};
-};
-
-&syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
-			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
-			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
-			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
-	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
-				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
-				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
-				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
-	assigned-clock-rates = <0>, <0>, <0>, <0>;
-};
-
-&sysgpio {
-	bootph-pre-ram;
-};
-
-&mmc0_pins {
-	bootph-pre-ram;
-	rst-pins {
-		bootph-pre-ram;
-	};
-};
-
-&mmc1_pins {
-	bootph-pre-ram;
-	clk-pins {
-		bootph-pre-ram;
-	};
-
-	mmc-pins {
-		bootph-pre-ram;
-	};
-};
-
-&i2c5_pins {
-	bootph-pre-ram;
-	i2c-pins {
-		bootph-pre-ram;
-	};
-};
-
-&i2c5 {
-	bootph-pre-ram;
-	eeprom@50 {
-		bootph-pre-ram;
-		compatible = "atmel,24c04";
-		reg = <0x50>;
-		pagesize = <16>;
-	};
-};
diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
deleted file mode 100644
index ab882d07f6f..00000000000
--- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-common-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
deleted file mode 100644
index ab882d07f6f..00000000000
--- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-common-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
deleted file mode 100644
index ab882d07f6f..00000000000
--- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-common-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
deleted file mode 100644
index ab882d07f6f..00000000000
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2024 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-common-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
deleted file mode 100644
index 874074174ff..00000000000
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
-
-#include "jh7110-common-u-boot.dtsi"
-#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
index f8d13277d24..0e5dc3685b2 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi
@@ -3,36 +3,10 @@
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
  */
 
-#include <dt-bindings/reset/starfive,jh7110-crg.h>
-
-/ {
-	timer {
-		compatible = "riscv,timer";
-		interrupts-extended = <&cpu0_intc 5>,
-				      <&cpu1_intc 5>,
-				      <&cpu2_intc 5>,
-				      <&cpu3_intc 5>,
-				      <&cpu4_intc 5>;
-	};
+// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
+// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
 
-	soc {
-		bootph-pre-ram;
-
-		dmc: dmc@15700000 {
-			bootph-pre-ram;
-			compatible = "starfive,jh7110-dmc";
-			reg = <0x0 0x15700000 0x0 0x10000>,
-				<0x0 0x13000000 0x0 0x10000>;
-			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
-				<&syscrg JH7110_SYSRST_DDR_OSC>,
-				<&syscrg JH7110_SYSRST_DDR_APB>;
-			reset-names = "axi", "osc", "apb";
-			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
-			clock-names = "pll1_out";
-			clock-frequency = <2133>;
-		};
-	};
-};
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
 
 &clint {
 	bootph-pre-ram;
@@ -58,22 +32,10 @@
 	bootph-pre-ram;
 };
 
-&cpus {
-	bootph-pre-ram;
-};
-
 &osc {
 	bootph-pre-ram;
 };
 
-&gmac0_rgmii_rxin {
-	bootph-pre-ram;
-};
-
-&gmac0_rmii_refin {
-	bootph-pre-ram;
-};
-
 &gmac1_rgmii_rxin {
 	bootph-pre-ram;
 };
@@ -82,23 +44,43 @@
 	bootph-pre-ram;
 };
 
-&aoncrg {
-	bootph-pre-ram;
+/ {
+	soc {
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			bootph-pre-ram;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll";
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+	};
 };
 
-&pllclk {
+&syscrg {
 	bootph-pre-ram;
 };
 
-&syscrg {
-	assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
+&pllclk {
 	bootph-pre-ram;
 };
 
-&stgcrg {
-	bootph-pre-ram;
+// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
+
+/ {
+	soc {
+		memory-controller@15700000 {
+			clock-frequency = <2133>; /* FIXME: delete property and implement CCF */
+		};
+	};
 };
 
-&sys_syscon {
-	bootph-pre-ram;
+&syscrg {
+	assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
 };
+
+#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi
new file mode 100644
index 00000000000..bbfa3c499cf
--- /dev/null
+++ b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Yao Zi <[email protected]>
+ */
+
+#include "th1520-u-boot.dtsi"
+
+&{/memory@0} {
+	bootph-pre-ram;
+};
diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
deleted file mode 100644
index eecd3e9832a..00000000000
--- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi
+++ /dev/null
@@ -1,164 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2023 Jisheng Zhang <[email protected]>
- */
-
-/dts-v1/;
-
-#include "th1520.dtsi"
-
-/ {
-	model = "Sipeed Lichee Module 4A";
-	compatible = "sipeed,lichee-module-4a", "thead,th1520";
-
-	aliases {
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x00000000 0x2 0x00000000>;
-		bootph-pre-ram;
-	};
-};
-
-&osc {
-	clock-frequency = <24000000>;
-};
-
-&osc_32k {
-	clock-frequency = <32768>;
-};
-
-&emmc {
-	bus-width = <8>;
-	max-frequency = <198000000>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
-	non-removable;
-	no-sdio;
-	no-sd;
-	status = "okay";
-};
-
-&gmac0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>;
-	phy-handle = <&phy0>;
-	phy-mode = "rgmii-id";
-	status = "okay";
-};
-
-&gmac1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&gmac1_pins>;
-	phy-handle = <&phy1>;
-	phy-mode = "rgmii-id";
-	status = "okay";
-};
-
-&mdio0 {
-	phy0: ethernet-phy@1 {
-		reg = <1>;
-	};
-
-	phy1: ethernet-phy@2 {
-		reg = <2>;
-	};
-};
-
-&padctrl0_apsys {
-	gmac0_pins: gmac0-0 {
-		tx-pins {
-			pins = "GMAC0_TX_CLK",
-			       "GMAC0_TXEN",
-			       "GMAC0_TXD0",
-			       "GMAC0_TXD1",
-			       "GMAC0_TXD2",
-			       "GMAC0_TXD3";
-			function = "gmac0";
-			bias-disable;
-			drive-strength = <25>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		rx-pins {
-			pins = "GMAC0_RX_CLK",
-			       "GMAC0_RXDV",
-			       "GMAC0_RXD0",
-			       "GMAC0_RXD1",
-			       "GMAC0_RXD2",
-			       "GMAC0_RXD3";
-			function = "gmac0";
-			bias-disable;
-			drive-strength = <1>;
-			input-enable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-	};
-
-	gmac1_pins: gmac1-0 {
-		tx-pins {
-			pins = "GPIO2_18", /* GMAC1_TX_CLK */
-			       "GPIO2_20", /* GMAC1_TXEN */
-			       "GPIO2_21", /* GMAC1_TXD0 */
-			       "GPIO2_22", /* GMAC1_TXD1 */
-			       "GPIO2_23", /* GMAC1_TXD2 */
-			       "GPIO2_24"; /* GMAC1_TXD3 */
-			function = "gmac1";
-			bias-disable;
-			drive-strength = <25>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		rx-pins {
-			pins = "GPIO2_19", /* GMAC1_RX_CLK */
-			       "GPIO2_25", /* GMAC1_RXDV */
-			       "GPIO2_30", /* GMAC1_RXD0 */
-			       "GPIO2_31", /* GMAC1_RXD1 */
-			       "GPIO3_0",  /* GMAC1_RXD2 */
-			       "GPIO3_1";  /* GMAC1_RXD3 */
-			function = "gmac1";
-			bias-disable;
-			drive-strength = <1>;
-			input-enable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-	};
-
-	mdio0_pins: mdio0-0 {
-		mdc-pins {
-			pins = "GMAC0_MDC";
-			function = "gmac0";
-			bias-disable;
-			drive-strength = <13>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		mdio-pins {
-			pins = "GMAC0_MDIO";
-			function = "gmac0";
-			bias-disable;
-			drive-strength = <13>;
-			input-enable;
-			input-schmitt-enable;
-			slew-rate = <0>;
-		};
-	};
-};
-
-&sdio0 {
-	bus-width = <4>;
-	max-frequency = <198000000>;
-	status = "okay";
-};
diff --git a/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi
new file mode 100644
index 00000000000..06d4a70d1ea
--- /dev/null
+++ b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Yao Zi <[email protected]>
+ */
+
+#include "th1520-lichee-module-4a-u-boot.dtsi"
+#include "thead-th1520-binman.dtsi"
+
+&clk {
+	bootph-some-ram;
+};
+
+&padctrl0_apsys {
+	bootph-some-ram;
+};
+
+&uart0_pins {
+	bootph-some-ram;
+
+	tx-pins {
+		bootph-some-ram;
+	};
+
+	rx-pins {
+		bootph-some-ram;
+	};
+};
diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts
deleted file mode 100644
index 49af88b7adf..00000000000
--- a/arch/riscv/dts/th1520-lichee-pi-4a.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2023 Jisheng Zhang <[email protected]>
- */
-
-#include "th1520-lichee-module-4a.dtsi"
-#include "thead-th1520-binman.dtsi"
-
-/ {
-	model = "Sipeed Lichee Pi 4A";
-	compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
-
-	aliases {
-		gpio0 = &gpio0;
-		gpio1 = &gpio1;
-		gpio2 = &gpio2;
-		gpio3 = &gpio3;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		serial5 = &uart5;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
diff --git a/arch/riscv/dts/th1520-u-boot.dtsi b/arch/riscv/dts/th1520-u-boot.dtsi
new file mode 100644
index 00000000000..45ffccbb847
--- /dev/null
+++ b/arch/riscv/dts/th1520-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Yao Zi <[email protected]>
+ */
+
+&{/soc} {
+	ddrc: ddrc@fffd000000 {
+		compatible = "thead,th1520-ddrc";
+		reg = <0xff 0xfd000000 0x0 0x1000000>,
+		      <0xff 0xfe000000 0x0 0x1000000>,
+		      <0xff 0xff000000 0x0 0x4000>,
+		      <0xff 0xff005000 0x0 0x1000>;
+		reg-names = "phy-0", "phy-1", "ctrl", "sys";
+		bootph-pre-ram;
+	};
+};
+
+&cpus {
+	bootph-pre-ram;
+};
+
+&c910_0 {
+	bootph-pre-ram;
+};
+
+&c910_1 {
+	bootph-pre-ram;
+};
+
+&c910_2 {
+	bootph-pre-ram;
+};
+
+&c910_3 {
+	bootph-pre-ram;
+};
+
+&clint {
+	bootph-pre-ram;
+};
+
+&uart0 {
+	bootph-pre-ram;
+};
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
deleted file mode 100644
index c46925a132a..00000000000
--- a/arch/riscv/dts/th1520.dtsi
+++ /dev/null
@@ -1,530 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Alibaba Group Holding Limited.
- * Copyright (C) 2023 Jisheng Zhang <[email protected]>
- */
-
-#include <dt-bindings/clock/thead,th1520-clk-ap.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	compatible = "thead,th1520";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus: cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		bootph-pre-ram;
-		timebase-frequency = <3000000>;
-
-		c910_0: cpu@0 {
-			compatible = "thead,c910", "riscv";
-			device_type = "cpu";
-			riscv,isa = "rv64imafdc";
-			reg = <0>;
-			bootph-pre-ram;
-			i-cache-block-size = <64>;
-			i-cache-size = <65536>;
-			i-cache-sets = <512>;
-			d-cache-block-size = <64>;
-			d-cache-size = <65536>;
-			d-cache-sets = <512>;
-			next-level-cache = <&l2_cache>;
-			mmu-type = "riscv,sv39";
-
-			cpu0_intc: interrupt-controller {
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-				#interrupt-cells = <1>;
-			};
-		};
-
-		c910_1: cpu@1 {
-			compatible = "thead,c910", "riscv";
-			device_type = "cpu";
-			riscv,isa = "rv64imafdc";
-			reg = <1>;
-			bootph-pre-ram;
-			i-cache-block-size = <64>;
-			i-cache-size = <65536>;
-			i-cache-sets = <512>;
-			d-cache-block-size = <64>;
-			d-cache-size = <65536>;
-			d-cache-sets = <512>;
-			next-level-cache = <&l2_cache>;
-			mmu-type = "riscv,sv39";
-
-			cpu1_intc: interrupt-controller {
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-				#interrupt-cells = <1>;
-			};
-		};
-
-		c910_2: cpu@2 {
-			compatible = "thead,c910", "riscv";
-			device_type = "cpu";
-			riscv,isa = "rv64imafdc";
-			reg = <2>;
-			bootph-pre-ram;
-			i-cache-block-size = <64>;
-			i-cache-size = <65536>;
-			i-cache-sets = <512>;
-			d-cache-block-size = <64>;
-			d-cache-size = <65536>;
-			d-cache-sets = <512>;
-			next-level-cache = <&l2_cache>;
-			mmu-type = "riscv,sv39";
-
-			cpu2_intc: interrupt-controller {
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-				#interrupt-cells = <1>;
-			};
-		};
-
-		c910_3: cpu@3 {
-			compatible = "thead,c910", "riscv";
-			device_type = "cpu";
-			riscv,isa = "rv64imafdc";
-			reg = <3>;
-			bootph-pre-ram;
-			i-cache-block-size = <64>;
-			i-cache-size = <65536>;
-			i-cache-sets = <512>;
-			d-cache-block-size = <64>;
-			d-cache-size = <65536>;
-			d-cache-sets = <512>;
-			next-level-cache = <&l2_cache>;
-			mmu-type = "riscv,sv39";
-
-			cpu3_intc: interrupt-controller {
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-				#interrupt-cells = <1>;
-			};
-		};
-
-		l2_cache: l2-cache {
-			compatible = "cache";
-			cache-block-size = <64>;
-			cache-level = <2>;
-			cache-size = <1048576>;
-			cache-sets = <1024>;
-			cache-unified;
-		};
-	};
-
-	osc: oscillator {
-		compatible = "fixed-clock";
-		clock-output-names = "osc_24m";
-		#clock-cells = <0>;
-	};
-
-	osc_32k: 32k-oscillator {
-		compatible = "fixed-clock";
-		clock-output-names = "osc_32k";
-		#clock-cells = <0>;
-	};
-
-	aonsys_clk: clock-73728000 {
-		compatible = "fixed-clock";
-		clock-frequency = <73728000>;
-		clock-output-names = "aonsys_clk";
-		#clock-cells = <0>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		interrupt-parent = <&plic>;
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		plic: interrupt-controller@ffd8000000 {
-			compatible = "thead,th1520-plic", "thead,c900-plic";
-			reg = <0xff 0xd8000000 0x0 0x01000000>;
-			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
-					      <&cpu1_intc 11>, <&cpu1_intc 9>,
-					      <&cpu2_intc 11>, <&cpu2_intc 9>,
-					      <&cpu3_intc 11>, <&cpu3_intc 9>;
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <2>;
-			riscv,ndev = <240>;
-		};
-
-		clint: timer@ffdc000000 {
-			compatible = "thead,th1520-clint", "thead,c900-clint";
-			reg = <0xff 0xdc000000 0x0 0x00010000>;
-			bootph-pre-ram;
-			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
-					      <&cpu1_intc 3>, <&cpu1_intc 7>,
-					      <&cpu2_intc 3>, <&cpu2_intc 7>,
-					      <&cpu3_intc 3>, <&cpu3_intc 7>;
-		};
-
-		uart0: serial@ffe7014000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xe7014000 0x0 0x100>;
-			bootph-pre-ram;
-			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
-			clock-names = "buadclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		gmac1: ethernet@ffe7060000 {
-			compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
-			reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
-			reg-names = "dwmac", "apb";
-			interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
-			clock-names = "stmmaceth", "pclk";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-			snps,multicast-filter-bins = <64>;
-			snps,perfect-filter-entries = <32>;
-			status = "disabled";
-
-			mdio1: mdio {
-				compatible = "snps,dwmac-mdio";
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		gmac0: ethernet@ffe7070000 {
-			compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
-			reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
-			reg-names = "dwmac", "apb";
-			interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
-			clock-names = "stmmaceth", "pclk";
-			snps,pbl = <32>;
-			snps,fixed-burst;
-			snps,multicast-filter-bins = <64>;
-			snps,perfect-filter-entries = <32>;
-			status = "disabled";
-
-			mdio0: mdio {
-				compatible = "snps,dwmac-mdio";
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
-		emmc: mmc@ffe7080000 {
-			compatible = "thead,th1520-dwcmshc";
-			reg = <0xff 0xe7080000 0x0 0x10000>;
-			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_EMMC_SDIO>;
-			clock-names = "core";
-			status = "disabled";
-		};
-
-		sdio0: mmc@ffe7090000 {
-			compatible = "thead,th1520-dwcmshc";
-			reg = <0xff 0xe7090000 0x0 0x10000>;
-			interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_EMMC_SDIO>;
-			clock-names = "core";
-			status = "disabled";
-		};
-
-		sdio1: mmc@ffe70a0000 {
-			compatible = "thead,th1520-dwcmshc";
-			reg = <0xff 0xe70a0000 0x0 0x10000>;
-			interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_EMMC_SDIO>;
-			clock-names = "core";
-			status = "disabled";
-		};
-
-		uart1: serial@ffe7f00000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xe7f00000 0x0 0x100>;
-			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
-			clock-names = "buadclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart3: serial@ffe7f04000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xe7f04000 0x0 0x100>;
-			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
-			clock-names = "buadclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		gpio2: gpio@ffe7f34000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xe7f34000 0x0 0x1000>;
-			clocks = <&clk CLK_GPIO2>;
-			clock-names = "bus";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portc: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		gpio3: gpio@ffe7f38000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xe7f38000 0x0 0x1000>;
-			clocks = <&clk CLK_GPIO3>;
-			clock-names = "bus";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portd: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		padctrl1_apsys: pinctrl@ffe7f3c000 {
-			compatible = "thead,th1520-pinctrl";
-			reg = <0xff 0xe7f3c000 0x0 0x1000>;
-			clocks = <&clk CLK_PADCTRL1>;
-			thead,pad-group = <2>;
-		};
-
-		gpio0: gpio@ffec005000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xec005000 0x0 0x1000>;
-			clocks = <&clk CLK_GPIO0>;
-			clock-names = "bus";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			porta: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		gpio1: gpio@ffec006000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xec006000 0x0 0x1000>;
-			clocks = <&clk CLK_GPIO1>;
-			clock-names = "bus";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portb: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		padctrl0_apsys: pinctrl@ffec007000 {
-			compatible = "thead,th1520-pinctrl";
-			reg = <0xff 0xec007000 0x0 0x1000>;
-			clocks = <&clk CLK_PADCTRL0>;
-			thead,pad-group = <3>;
-		};
-
-		uart2: serial@ffec010000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xec010000 0x0 0x4000>;
-			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
-			clock-names = "buadclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		clk: clock-controller@ffef010000 {
-			compatible = "thead,th1520-clk-ap";
-			reg = <0xff 0xef010000 0x0 0x1000>;
-			clocks = <&osc>;
-			#clock-cells = <1>;
-		};
-
-		timer0: timer@ffefc32000 {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xefc32000 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		timer1: timer@ffefc32014 {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xefc32014 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		timer2: timer@ffefc32028 {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xefc32028 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		timer3: timer@ffefc3203c {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xefc3203c 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		uart4: serial@fff7f08000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xf7f08000 0x0 0x4000>;
-			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
-			clock-names = "buadclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		uart5: serial@fff7f0c000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0xff 0xf7f0c000 0x0 0x4000>;
-			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
-			clock-names = "buadclk", "apb_pclk";
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			status = "disabled";
-		};
-
-		ddrc: ddrc@fffd000000 {
-			compatible = "thead,th1520-ddrc";
-			reg = <0xff 0xfd000000 0x0 0x1000000>,
-			      <0xff 0xfe000000 0x0 0x1000000>,
-			      <0xff 0xff000000 0x0 0x4000>,
-			      <0xff 0xff005000 0x0 0x1000>;
-			reg-names = "phy-0", "phy-1", "ctrl", "sys";
-			bootph-pre-ram;
-		};
-
-		timer4: timer@ffffc33000 {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xffc33000 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		timer5: timer@ffffc33014 {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xffc33014 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		timer6: timer@ffffc33028 {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xffc33028 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		timer7: timer@ffffc3303c {
-			compatible = "snps,dw-apb-timer";
-			reg = <0xff 0xffc3303c 0x0 0x14>;
-			clocks = <&clk CLK_PERI_APB_PCLK>;
-			clock-names = "timer";
-			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		ao_gpio0: gpio@fffff41000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xfff41000 0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			porte: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-
-		padctrl_aosys: pinctrl@fffff4a000 {
-			compatible = "thead,th1520-pinctrl";
-			reg = <0xff 0xfff4a000 0x0 0x2000>;
-			clocks = <&aonsys_clk>;
-			thead,pad-group = <1>;
-		};
-
-		ao_gpio1: gpio@fffff52000 {
-			compatible = "snps,dw-apb-gpio";
-			reg = <0xff 0xfff52000 0x0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			portf: gpio-controller@0 {
-				compatible = "snps,dw-apb-gpio-port";
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <32>;
-				reg = <0>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
-			};
-		};
-	};
-};
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 56c5da86e86..ae3e5bce5c1 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -95,7 +95,6 @@
 #define DEFAULT_MTVEC		0x00001010
 #define CFG_STRING_ADDR	0x0000100C
 #define EXT_IO_BASE		0x40000000
-#define DRAM_BASE		0x80000000
 
 // page table entry (PTE) fields
 #define PTE_V		0x001 // Valid
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index f5c9a8aecf2..e48eb23cdc0 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -35,6 +35,7 @@
 #include <asm/state.h>
 #include <os.h>
 #include <rtc_def.h>
+#include <env.h>
 
 /* Environment variable for time offset */
 #define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET"
@@ -1014,7 +1015,7 @@ long os_get_time_offset(void)
 {
 	const char *offset;
 
-	offset = getenv(ENV_TIME_OFFSET);
+	offset = env_get(ENV_TIME_OFFSET);
 	if (offset)
 		return strtol(offset, NULL, 0);
 	return 0;
diff --git a/arch/sandbox/include/asm/atomic.h b/arch/sandbox/include/asm/atomic.h
new file mode 100644
index 00000000000..2fe49f52f34
--- /dev/null
+++ b/arch/sandbox/include/asm/atomic.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/include/asm/atomic.h which is:
+ * Copyright 2023 SiFive, Inc.
+ */
+
+#ifndef __SANDBOX_ATOMIC_H
+#define __SANDBOX_ATOMIC_H
+
+/* use the generic asm/atomic.h until we define a better one */
+
+#include <asm/system.h>
+#include <asm-generic/atomic.h>
+
+#endif
diff --git a/arch/sandbox/include/asm/dma-mapping.h b/arch/sandbox/include/asm/dma-mapping.h
index 853b0877b33..410760c2231 100644
--- a/arch/sandbox/include/asm/dma-mapping.h
+++ b/arch/sandbox/include/asm/dma-mapping.h
@@ -1 +1,28 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copied from arch/arm/include/asm/dma-mapping.h which is:
+ *
+ * (C) Copyright 2007
+ * Stelian Pop <[email protected]>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#ifndef __ASM_SANDBOX_DMA_MAPPING_H
+#define __ASM_SANDBOX_DMA_MAPPING_H
+
+#include <asm/cache.h>
+#include <linux/types.h>
+#include <malloc.h>
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
+	return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+	free(addr);
+}
+
+#endif
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 11ed89e0071..cd3f5d6fd40 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -12,6 +12,10 @@ static inline void sync(void)
 {
 }
 
+#define mb()	sync()
+#define dmb()	sync()
+#define wmb()	sync()
+
 enum sandboxio_size_t {
 	SB_SIZE_8,
 	SB_SIZE_16,
@@ -53,6 +57,16 @@ void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size);
 #define writeq(v, addr) sandbox_write((void *)addr, v, SB_SIZE_64)
 #endif
 
+#define readb_relaxed			readb
+#define readw_relaxed			readw
+#define readl_relaxed			readl
+#define readq_relaxed			readq
+
+#define writeb_relaxed			writeb
+#define writew_relaxed			writew
+#define writel_relaxed			writel
+#define writeq_relaxed			writeq
+
 /*
  * Clear and set bits in one shot. These macros can be used to clear and
  * set multiple bits in a register using a single call. These macros can
diff --git a/arch/sandbox/include/asm/processor.h b/arch/sandbox/include/asm/processor.h
index 8dced6006bd..6521274efb0 100644
--- a/arch/sandbox/include/asm/processor.h
+++ b/arch/sandbox/include/asm/processor.h
@@ -6,6 +6,7 @@
 #ifndef _ASM_PROCESSOR_H
 #define _ASM_PROCESSOR_H
 
-/* This file is required for PCI */
+/* Assorted dummy functions */
+#define cpu_relax()
 
 #endif
diff --git a/arch/sandbox/include/asm/system.h b/arch/sandbox/include/asm/system.h
index 7933b6292e2..73f34683b27 100644
--- a/arch/sandbox/include/asm/system.h
+++ b/arch/sandbox/include/asm/system.h
@@ -7,10 +7,9 @@
 #define __ASM_SANDBOX_SYSTEM_H
 
 /* Define this as nops for sandbox architecture */
-#define local_irq_save(x)
+#define local_irq_save(x)	do { (x) = 0; } while (0)
 #define local_irq_enable()
 #define local_irq_disable()
-#define local_save_flags(x)
 #define local_irq_restore(x)
 
 #endif