Merge tag 'u-boot-socfpga-next-20260213' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.

DDR and memory handling

  * Add DRAM size checking support for Arria10.
  * Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
  * Assign unit address to memory node for improved memory
    representation and consistency.

Agilex / Agilex5 updates

  * Restore multi-DTB support for NAND boot and fix NAND clock handling.
  * Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
  * Fix DT property naming conventions for Agilex5.
  * Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
    to avoid unintended clock control.

New board support

  * Add support for CoreCourse Cyclone V boards:
     * AC501
     * AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.

Fixes and cleanup

  * Fix GEN5 handoff script path.
  * Remove incorrect CONFIG_SPL_LDSCRIPT settings.
  * Replace legacy TARGET namespace and perform related cleanup across
    SoCFPGA code.
  * General Kconfig, build and SoCFPGA maintenance updates.

Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.

[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <[email protected]>

40 files changed, 551 insertions, 171 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd6a454fd60..5508fce796a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -30,7 +30,7 @@ config COUNTER_FREQUENCY
 			ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
 	default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
 	default 100000000 if ARCH_ZYNQMP
-	default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M
+	default 200000000 if ARCH_SOCFPGA_AGILEX5 || ARCH_SOCFPGA_AGILEX7M
 	default 0
 	help
 	  For platforms with ARMv8-A and ARMv7-A which features a system
@@ -1145,35 +1145,35 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select ARCH_EARLY_INIT_R
-	select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-	select ARM64 if TARGET_SOCFPGA_SOC64
-	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select ARCH_MISC_INIT if !ARCH_SOCFPGA_ARRIA10
+	select ARM64 if ARCH_SOCFPGA_SOC64
+	select CPU_V7A if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
-	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
-	select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64
+	select ENABLE_ARM_SOC_BOOT0_HOOK if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
+	select LMB_ARCH_MEM_MAP if ARCH_SOCFPGA_SOC64
 	select OF_CONTROL
 	select SPL_DM_RESET if DM_RESET
 	select SPL_DM_SERIAL
 	select SPL_LIBCOMMON_SUPPORT
 	select SPL_LIBGENERIC_SUPPORT
 	select SPL_OF_CONTROL
-	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
-	select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
-	select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
+	select SPL_SEPARATE_BSS if ARCH_SOCFPGA_SOC64
+	select SPL_DRIVERS_MISC if ARCH_SOCFPGA_SOC64
+	select SPL_SOCFPGA_DT_REG if ARCH_SOCFPGA_SOC64
 	select SPL_SERIAL
 	select SPL_SYSRESET
 	select SPL_WATCHDOG
 	select SUPPORT_SPL
 	select SYS_NS16550
-	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
+	select SYS_THUMB_BUILD if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
 	select SYSRESET
-	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
-	select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
-           TARGET_SOCFPGA_SOC64
-	select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
-	select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64
+	select SYSRESET_SOCFPGA if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
+	select SYSRESET_SOCFPGA_SOC64 if !ARCH_SOCFPGA_AGILEX5 && \
+           ARCH_SOCFPGA_SOC64
+	select SYSRESET_PSCI if ARCH_SOCFPGA_AGILEX5
+	select USE_BOOTFILE if SPL_ATF && ARCH_SOCFPGA_SOC64
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 82ad3035308..264b13b6f5d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -469,6 +469,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
 	socfpga_cyclone5_vining_fpga.dtb		\
+	socfpga_cyclone5_ac501soc.dtb			\
+	socfpga_cyclone5_ac550soc.dtb			\
 	socfpga_n5x_socdk.dtb				\
 	socfpga_stratix10_socdk.dtb
 
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index 695242bec21..ddef9a2896d 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -5,7 +5,7 @@
  * Copyright (c) 2019 Simon Goldschmidt
  */
 /{
-	memory {
+	memory@0 {
 		bootph-all;
 	};
 
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index 770f6cad292..c0f932d0e11 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -264,7 +264,7 @@
 };
 #endif
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M
+#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M
 &sdr {
 	compatible = "intel,sdr-ctl-agilex7m";
 	reg = <0xf8020000 0x100>;
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 5a7aa5841e3..c03f78b2fdf 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -110,26 +110,49 @@
 	status = "okay";
 
 	no-mmc;
-	no-1-8-v;
 	disable-wp;
 	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
 	vmmc-supply = <&sd_emmc_power>;
 	vqmmc-supply = <&sd_io_1v8_reg>;
 	max-frequency = <200000000>;
+	sdhci-caps = <0x00000000 0x0000c800>;
+	sdhci-caps-mask = <0x00002000 0x0000ff00>;
 
 	/* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */
 	cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
-	cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>;
+	cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>;
 	cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
 	cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
 
 	/* SD card high speed and UHS-I SDR25 mode timing configuration */
 	cdns,phy-dqs-timing-delay-sd-hs = <0x780001>;
-	cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>;
+	cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>;
 	cdns,phy-dq-timing-delay-sd-hs = <0x10000001>;
 	cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>;
 	cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>;
 
+	/* SD card UHS-I SDR50 mode timing configuration */
+	cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>;
+	cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>;
+	cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>;
+	cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>;
+	cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>;
+	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>;
+	cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
+	cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>;
+
+	/* SD card UHS-I SDR104 mode timing configuration */
+	cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
+	cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
+	cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
+	cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>;
+	cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
+	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
+	cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
+	cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+
 	bootph-all;
 };
 
diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
index f6848c373cd..c06781064ca 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
@@ -25,11 +25,14 @@
 	disable-wp;
 	non-removable;
 	cap-mmc-highspeed;
-
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
 	bus-width = <8>;
 	vmmc-supply = <&sd_emmc_power>;
 	vqmmc-supply = <&emmc_io_1v8_reg>;
 	max-frequency = <200000000>;
+	sdhci-caps = <0x00000000 0x0004c800>;	/* SDHCI_CAN_DO_8BIT */
+	sdhci-caps-mask = <0x00000000 0x0000ff00>;
 
 	/* eMMC legacy mode timing configuration */
 	cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
@@ -46,4 +49,26 @@
 	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
 	cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
 	cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
+
+	/* eMMC HS200 mode timing configuration */
+	cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
+	cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
+	cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
+	cdns,phy-dq-timing-delay-emmc-hs200 = <0x10000001>;
+	cdns,phy-dll-master-ctrl-emmc-hs200 = <0x4>;
+	cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
+	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
+	cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
+	cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+
+	/* eMMC HS400 mode timing configuration */
+	cdns,phy-dqs-timing-delay-emmc-hs400 = <0x680004>;
+	cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400 = <0x81a40040>;
+	cdns,phy-dll-slave-ctrl-emmc-hs400 = <0x4d4b40>;
+	cdns,phy-dq-timing-delay-emmc-hs400 = <0x10000001>;
+	cdns,phy-dll-master-ctrl-emmc-hs400 = <0x4>;
+	cdns,ctrl-hrs09-timing-delay-emmc-hs400 = <0xf1c18000>;
+	cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>;
+	cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>;
+	cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>;
 };
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index 6f2fe7bf746..f2150b7eb7b 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -8,7 +8,7 @@
 
 #include "socfpga_agilex-u-boot.dtsi"
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#ifdef CONFIG_ARCH_SOCFPGA_AGILEX
 /{
 	chosen {
 		stdout-path = "serial0:115200n8";
@@ -27,7 +27,7 @@
 };
 #endif
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M
+#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M
 /{
 	model = "SoCFPGA Agilex7-M SoCDK";
 	chosen {
@@ -181,3 +181,41 @@
 		};
 	};
 };
+
+#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&fdt_0_blob {
+	filename = "dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dtb";
+};
+
+&images {
+	fdt-1 {
+		description = "socfpga_socdk_nand";
+		type = "flat_dt";
+		compression = "none";
+		fdt_1_blob: blob-ext {
+			filename = "dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dtb";
+		};
+		hash {
+			algo = "crc32";
+		};
+	};
+};
+
+&board_config {
+	board-1 {
+		description = "board_1";
+		firmware = "atf";
+		loadables = "uboot";
+		fdt = "fdt-1";
+		signature {
+			algo = "crc32";
+			key-name-hint = "dev";
+			sign-images = "atf", "uboot", "fdt-1";
+		};
+	};
+};
+
+&binman {
+	/delete-node/ kernel;
+};
+#endif
diff --git a/arch/arm/dts/socfpga_arria5_secu1.dts b/arch/arm/dts/socfpga_arria5_secu1.dts
index 8e9c3bbdf9d..dfc04cc2d7a 100644
--- a/arch/arm/dts/socfpga_arria5_secu1.dts
+++ b/arch/arm/dts/socfpga_arria5_secu1.dts
@@ -16,7 +16,7 @@
 		bootargs = "console=ttyS0,115200";
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x20000000>; /* 512MB */
diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi
new file mode 100644
index 00000000000..8d2caf69dd1
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright Altera Corporation (C) 2015
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+	aliases {
+		udc0 = &usb1;
+	};
+};
+
+&watchdog0 {
+	status = "disabled";
+};
+
+&mmc {
+	bootph-all;
+};
+
+&uart0 {
+	clock-frequency = <100000000>;
+	bootph-all;
+};
+
+&uart1 {
+	clock-frequency = <100000000>;
+};
+
+&porta {
+	bank-name = "porta";
+};
+
+&portb {
+	bank-name = "portb";
+};
+
+&portc {
+	bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc.dts b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
new file mode 100644
index 00000000000..6b02fa63c7c
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025, Brian Sune
+ *
+ * based on socfpga_cyclone5_socdk.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "CoreCourse AC501SoC";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb1;
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <420>;
+	rxd1-skew-ps = <420>;
+	rxd2-skew-ps = <420>;
+	rxd3-skew-ps = <420>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <1860>;
+	rxdv-skew-ps = <420>;
+	rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&mmc0 {
+	vmmc-supply = <&regulator_3_3v>;
+	vqmmc-supply = <&regulator_3_3v>;
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi
new file mode 100644
index 00000000000..8d2caf69dd1
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright Altera Corporation (C) 2015
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+	aliases {
+		udc0 = &usb1;
+	};
+};
+
+&watchdog0 {
+	status = "disabled";
+};
+
+&mmc {
+	bootph-all;
+};
+
+&uart0 {
+	clock-frequency = <100000000>;
+	bootph-all;
+};
+
+&uart1 {
+	clock-frequency = <100000000>;
+};
+
+&porta {
+	bank-name = "porta";
+};
+
+&portb {
+	bank-name = "portb";
+};
+
+&portc {
+	bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc.dts b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts
new file mode 100644
index 00000000000..cc841e85560
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025, Brian Sune
+ *
+ * based on socfpga_cyclone5_socdk.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "CoreCourse AC550SoC,AC802-CVA6";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb1;
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		hps0 {
+			label = "hps_led0";
+			gpios = <&portb 6 1>;
+		};
+
+		hps1 {
+			label = "hps_led1";
+			gpios = <&porta 9 1>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		hps0 {
+			label = "HPS GPIO0";
+			gpios = <&porta 0 0>;
+		};
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&i2c3 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	i2c-sda-falling-time-ns = <5000>;
+	i2c-scl-falling-time-ns = <5000>;
+
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <420>;
+	rxd1-skew-ps = <420>;
+	rxd2-skew-ps = <420>;
+	rxd3-skew-ps = <420>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <1860>;
+	rxdv-skew-ps = <420>;
+	rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&mmc0 {
+	vmmc-supply = <&regulator_3_3v>;
+	vqmmc-supply = <&regulator_3_3v>;
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index ca030c8c41b..094db1cb7d4 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -20,7 +20,7 @@
 		udc0 = &usb1;
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index 34886ec1ad8..346b2ef9e2d 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -22,7 +22,7 @@
 		udc0 = &usb1;
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
index b38f0723823..37203b63410 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
@@ -22,7 +22,7 @@
 		udc0 = &usb1;
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index e9de72429f2..264ca3dd53f 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -20,7 +20,7 @@
 		udc0 = &usb1;
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 58a5faf6ea2..b26248b023e 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -15,7 +15,7 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory {
+	memory@0 {
 		name = "memory";
 		device_type = "memory";
 		reg = <0x0 0x10000000>;
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index 93a8e0697d6..88f0154463d 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -28,7 +28,7 @@
 					os = "U-Boot";
 					arch = "arm64";
 					compression = "none";
-				#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+				#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 					load = <0x80200000>;
 				#else
 					load = <0x00200000>;
@@ -47,7 +47,7 @@
 					os = "arm-trusted-firmware";
 					arch = "arm64";
 					compression = "none";
-				#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+				#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 					load = <0x80000000>;
 					entry = <0x80000000>;
 				#else
@@ -106,7 +106,7 @@
 					arch = "arm64";
 					os = "linux";
 					compression = "none";
-				#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+				#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 					load = <0x86000000>;
 					entry = <0x86000000>;
 				#else
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index f2e959b5662..aec0fb7b1c8 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,15 +1,15 @@
 if ARCH_SOCFPGA
 
 config ERR_PTR_OFFSET
-	default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
+	default 0xfffec000 if ARCH_SOCFPGA_GEN5 # Boot ROM range
 
 config NR_DRAM_BANKS
 	default 1
 
 config SOCFPGA_SECURE_VAB_AUTH
 	bool "Enable boot image authentication with Secure Device Manager"
-	depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \
-	  TARGET_SOCFPGA_AGILEX5
+	depends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \
+	  ARCH_SOCFPGA_AGILEX5
 	select FIT_IMAGE_POST_PROCESS
 	select SHA384
 	select SHA512
@@ -23,32 +23,32 @@ config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
 	depends on SOCFPGA_SECURE_VAB_AUTH
 
 config SPL_SIZE_LIMIT
-	default 0x10000 if TARGET_SOCFPGA_GEN5
+	default 0x10000 if ARCH_SOCFPGA_GEN5
 
 config SPL_SIZE_LIMIT_PROVIDE_STACK
-	default 0x200 if TARGET_SOCFPGA_GEN5
+	default 0x200 if ARCH_SOCFPGA_GEN5
 
 config SPL_STACK_R_ADDR
-	default 0x00800000 if TARGET_SOCFPGA_GEN5
+	default 0x00800000 if ARCH_SOCFPGA_GEN5
 
 config SPL_SYS_MALLOC_F
-	default y if TARGET_SOCFPGA_GEN5
+	default y if ARCH_SOCFPGA_GEN5
 
 config SPL_SYS_MALLOC_F_LEN
-	default 0x800 if TARGET_SOCFPGA_GEN5
+	default 0x800 if ARCH_SOCFPGA_GEN5
 
 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
 	default 0xa2
 
 config SYS_MALLOC_F_LEN
-	default 0x2000 if TARGET_SOCFPGA_ARRIA10
-	default 0x2000 if TARGET_SOCFPGA_GEN5
+	default 0x2000 if ARCH_SOCFPGA_ARRIA10
+	default 0x2000 if ARCH_SOCFPGA_GEN5
 
 config TEXT_BASE
-	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
-	default 0x01000040 if TARGET_SOCFPGA_GEN5
+	default 0x01000040 if ARCH_SOCFPGA_ARRIA10
+	default 0x01000040 if ARCH_SOCFPGA_GEN5
 
-config TARGET_SOCFPGA_AGILEX
+config ARCH_SOCFPGA_AGILEX
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
@@ -58,9 +58,9 @@ config TARGET_SOCFPGA_AGILEX
 	select GICV2
 	select NCORE_CACHE
 	select SPL_CLK if SPL
-	select TARGET_SOCFPGA_SOC64
+	select ARCH_SOCFPGA_SOC64
 
-config TARGET_SOCFPGA_AGILEX7M
+config ARCH_SOCFPGA_AGILEX7M
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
@@ -70,21 +70,21 @@ config TARGET_SOCFPGA_AGILEX7M
 	select GICV2
 	select NCORE_CACHE
 	select SPL_CLK if SPL
-	select TARGET_SOCFPGA_SOC64
+	select ARCH_SOCFPGA_SOC64
 
-config TARGET_SOCFPGA_AGILEX5
+config ARCH_SOCFPGA_AGILEX5
 	bool
 	select BINMAN if SPL_ATF
 	select CLK
 	select FPGA_INTEL_SDM_MAILBOX
 	select SPL_CLK if SPL
-	select TARGET_SOCFPGA_SOC64
+	select ARCH_SOCFPGA_SOC64
 
-config TARGET_SOCFPGA_ARRIA5
+config ARCH_SOCFPGA_ARRIA5
 	bool
-	select TARGET_SOCFPGA_GEN5
+	select ARCH_SOCFPGA_GEN5
 
-config TARGET_SOCFPGA_ARRIA10
+config ARCH_SOCFPGA_ARRIA10
 	bool
 	select GICV2
 	select SPL_ALTERA_SDRAM
@@ -105,17 +105,17 @@ config TARGET_SOCFPGA_ARRIA10
 
 config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
 	bool "Always reprogram Arria 10 FPGA"
-	depends on TARGET_SOCFPGA_ARRIA10
+	depends on ARCH_SOCFPGA_ARRIA10
 	help
 	  Arria 10 FPGA is only programmed during the cold boot.
 	  This option forces the FPGA to be reprogrammed every reboot,
 	  allowing to change the bitstream and apply it with warm reboot.
 
-config TARGET_SOCFPGA_CYCLONE5
+config ARCH_SOCFPGA_CYCLONE5
 	bool
-	select TARGET_SOCFPGA_GEN5
+	select ARCH_SOCFPGA_GEN5
 
-config TARGET_SOCFPGA_GEN5
+config ARCH_SOCFPGA_GEN5
 	bool
 	select SPL_ALTERA_SDRAM
 	imply FPGA_SOCFPGA
@@ -125,7 +125,7 @@ config TARGET_SOCFPGA_GEN5
 	imply SPL_SYS_MALLOC_SIMPLE
 	imply SPL_USE_TINY_PRINTF
 
-config TARGET_SOCFPGA_N5X
+config ARCH_SOCFPGA_N5X
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
@@ -135,23 +135,23 @@ config TARGET_SOCFPGA_N5X
 	select NCORE_CACHE
 	select SPL_ALTERA_SDRAM
 	select SPL_CLK if SPL
-	select TARGET_SOCFPGA_SOC64
+	select ARCH_SOCFPGA_SOC64
 
 config TARGET_SOCFPGA_N5X_SOCDK
 	bool "Intel eASIC SoCDK (N5X)"
-	select TARGET_SOCFPGA_N5X
+	select ARCH_SOCFPGA_N5X
 
-config TARGET_SOCFPGA_SOC64
+config ARCH_SOCFPGA_SOC64
 	bool
 
-config TARGET_SOCFPGA_STRATIX10
+config ARCH_SOCFPGA_STRATIX10
 	bool
 	select ARMV8_MULTIENTRY
 	select ARMV8_SET_SMPEN
 	select BINMAN if SPL_ATF
 	select FPGA_INTEL_SDM_MAILBOX
 	select GICV2
-	select TARGET_SOCFPGA_SOC64
+	select ARCH_SOCFPGA_SOC64
 
 choice
 	prompt "Altera SOCFPGA board select"
@@ -159,85 +159,93 @@ choice
 
 config TARGET_SOCFPGA_AGILEX_SOCDK
 	bool "Intel SOCFPGA SoCDK (Agilex)"
-	select TARGET_SOCFPGA_AGILEX
+	select ARCH_SOCFPGA_AGILEX
 
 config TARGET_SOCFPGA_AGILEX7M_SOCDK
 	bool "Intel SOCFPGA SoCDK (Agilex7 M-series)"
-	select TARGET_SOCFPGA_AGILEX7M
+	select ARCH_SOCFPGA_AGILEX7M
 
 config TARGET_SOCFPGA_AGILEX5_SOCDK
 	bool "Intel SOCFPGA SoCDK (Agilex5)"
-	select TARGET_SOCFPGA_AGILEX5
+	select ARCH_SOCFPGA_AGILEX5
 
 config TARGET_SOCFPGA_ARIES_MCVEVK
 	bool "Aries MCVEVK (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_ARRIA10_SOCDK
 	bool "Altera SOCFPGA SoCDK (Arria 10)"
-	select TARGET_SOCFPGA_ARRIA10
+	select ARCH_SOCFPGA_ARRIA10
 
 config TARGET_SOCFPGA_ARRIA5_SECU1
 	bool "ABB SECU1 (Arria V)"
-	select TARGET_SOCFPGA_ARRIA5
+	select ARCH_SOCFPGA_ARRIA5
 	select VENDOR_KM
 
 config TARGET_SOCFPGA_ARRIA5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Arria V)"
-	select TARGET_SOCFPGA_ARRIA5
+	select ARCH_SOCFPGA_ARRIA5
 
 config TARGET_SOCFPGA_CHAMELEONV3
 	bool "Google Chameleon v3 (Arria 10)"
-	select TARGET_SOCFPGA_ARRIA10
+	select ARCH_SOCFPGA_ARRIA10
 
 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	bool "Devboards DBM-SoC1 (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_IS1
 	bool "IS1 (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 	bool "Softing VIN|ING FPGA (Cyclone V)"
 	select BOARD_LATE_INIT
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_STRATIX10_SOCDK
 	bool "Intel SOCFPGA SoCDK (Stratix 10)"
-	select TARGET_SOCFPGA_STRATIX10
+	select ARCH_SOCFPGA_STRATIX10
 
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 	bool "Terasic DE10-Nano (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 	bool "Terasic DE10-Standard (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 	bool "Terasic DE1-SoC (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_TERASIC_SOCKIT
 	bool "Terasic SoCkit (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
+	select ARCH_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_CORECOURSE_AC501SOC
+	bool "CoreCourse AC501SoC (Cyclone V)"
+	select ARCH_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_CORECOURSE_AC550SOC
+	bool "CoreCourse AC550SoC (Cyclone V)"
+	select ARCH_SOCFPGA_CYCLONE5
 
 endchoice
 
@@ -263,6 +271,8 @@ config SYS_BOARD
 	default "sr1500" if TARGET_SOCFPGA_SR1500
 	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+	default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
+	default "ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC
 
 config SYS_VENDOR
 	default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK
@@ -284,6 +294,8 @@ config SYS_VENDOR
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
+	default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC550SOC
 
 config SYS_SOC
 	default "socfpga"
@@ -310,5 +322,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+	default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
+	default "socfpga_ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC
 
 endif
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4e85bfb00d4..b6f35ddacc4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,7 +10,7 @@ obj-y	+= board.o
 obj-y	+= clock_manager.o
 obj-y	+= misc.o
 
-ifdef CONFIG_TARGET_SOCFPGA_GEN5
+ifdef CONFIG_ARCH_SOCFPGA_GEN5
 obj-y	+= clock_manager_gen5.o
 obj-y	+= misc_gen5.o
 obj-y	+= reset_manager_gen5.o
@@ -21,14 +21,14 @@ obj-y	+= wrap_pll_config.o
 obj-y	+= fpga_manager.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
 obj-y	+= clock_manager_arria10.o
 obj-y	+= misc_arria10.o
 obj-y	+= pinmux_arria10.o
 obj-y	+= reset_manager_arria10.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+ifdef CONFIG_ARCH_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
@@ -41,7 +41,7 @@ obj-y	+= wrap_handoff_soc64.o
 obj-y	+= wrap_pll_config_soc64.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+ifdef CONFIG_ARCH_SOCFPGA_AGILEX
 obj-y	+= clock_manager_agilex.o
 obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
@@ -57,7 +57,7 @@ obj-y	+= wrap_pll_config_soc64.o
 obj-y	+= altera-sysmgr.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
+ifdef CONFIG_ARCH_SOCFPGA_AGILEX5
 obj-y	+= clock_manager_agilex5.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_soc64.o
@@ -73,7 +73,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= secure_vab.o
 obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= vab.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M
+ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M
 obj-y	+= clock_manager_agilex.o
 obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
@@ -89,7 +89,7 @@ obj-y	+= wrap_pll_config_soc64.o
 obj-y	+= altera-sysmgr.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_N5X
+ifdef CONFIG_ARCH_SOCFPGA_N5X
 obj-y	+= clock_manager_n5x.o
 obj-y	+= lowlevel_init_soc64.o
 obj-y	+= mailbox_s10.o
@@ -105,34 +105,34 @@ obj-y	+= wrap_pll_config_soc64.o
 endif
 
 ifdef CONFIG_XPL_BUILD
-ifdef CONFIG_TARGET_SOCFPGA_GEN5
+ifdef CONFIG_ARCH_SOCFPGA_GEN5
 obj-y	+= spl_gen5.o
 obj-y	+= freeze_controller.o
 obj-y	+= wrap_iocsr_config.o
 obj-y	+= wrap_pinmux_config.o
 obj-y	+= wrap_sdram_config.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_SOC64
+ifdef CONFIG_ARCH_SOCFPGA_SOC64
 obj-y	+= firewall.o
 obj-y	+= spl_soc64.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
 obj-y	+= spl_a10.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+ifdef CONFIG_ARCH_SOCFPGA_STRATIX10
 obj-y	+= spl_s10.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+ifdef CONFIG_ARCH_SOCFPGA_AGILEX
 obj-y	+= spl_agilex.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_N5X
+ifdef CONFIG_ARCH_SOCFPGA_N5X
 obj-y	+= spl_n5x.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
+ifdef CONFIG_ARCH_SOCFPGA_AGILEX5
 obj-y	+= spl_soc64.o
 obj-y	+= spl_agilex5.o
 endif
-ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M
+ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M
 obj-y	+= spl_agilex7m.o
 endif
 else
@@ -140,7 +140,7 @@ obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
 obj-$(CONFIG_SPL_ATF) += smc_api.o
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_GEN5
+ifdef CONFIG_ARCH_SOCFPGA_GEN5
 # QTS-generated config file wrappers
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 7f65aed4540..4d7f0b9a79c 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -61,7 +61,7 @@ int board_init(void)
 
 int dram_init_banksize(void)
 {
-#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #ifndef CONFIG_SPL_BUILD
 	struct spl_handoff *ho;
 
@@ -72,7 +72,7 @@ int dram_init_banksize(void)
 #endif
 #else
 	fdtdec_setup_memory_banksize();
-#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
+#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */
 
 	return 0;
 }
@@ -145,7 +145,7 @@ u8 socfpga_get_board_id(void)
 	return board_id;
 }
 
-#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64)
 int board_fit_config_name_match(const char *name)
 {
 	char board_name[10];
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 134eaf08e0a..da71f5759db 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -18,7 +18,7 @@ void cm_wait_for_lock(u32 mask)
 	u32 inter_val;
 	u32 retry = 0;
 	do {
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 		inter_val = readl(socfpga_get_clkmgr_addr() +
 				  CLKMGR_INTER) & mask;
 #else
@@ -45,7 +45,7 @@ int cm_wait_for_fsm(void)
 
 int set_cpu_clk_info(void)
 {
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 	/* Calculate the clock frequencies required for drivers */
 	cm_get_l4_sp_clk_hz();
 	cm_get_mmc_controller_clk_hz();
@@ -54,7 +54,7 @@ int set_cpu_clk_info(void)
 	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
 	gd->bd->bi_dsp_freq = 0;
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
 #else
 	gd->bd->bi_ddr_freq = 0;
@@ -63,7 +63,7 @@ int set_cpu_clk_info(void)
 	return 0;
 }
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64)
 int cm_set_qspi_controller_clk_hz(u32 clk_hz)
 {
 	u32 reg;
diff --git a/arch/arm/mach-socfpga/config.mk b/arch/arm/mach-socfpga/config.mk
index 2290118f747..1ca1d33cb16 100644
--- a/arch/arm/mach-socfpga/config.mk
+++ b/arch/arm/mach-socfpga/config.mk
@@ -2,9 +2,9 @@
 #
 # Brian Sune <[email protected]>
 
-ifeq ($(CONFIG_TARGET_SOCFPGA_CYCLONE5),y)
+ifeq ($(CONFIG_ARCH_SOCFPGA_CYCLONE5),y)
 archprepare: socfpga_g5_handoff_prepare
-else ifeq ($(CONFIG_TARGET_SOCFPGA_ARRIA5),y)
+else ifeq ($(CONFIG_ARCH_SOCFPGA_ARRIA5),y)
 archprepare: socfpga_g5_handoff_prepare
 endif
 
@@ -23,7 +23,7 @@ socfpga_g5_handoff_prepare:
 		if [ -z "$$VENDOR" ] || [ -z "$$BOARD" ]; then \
 			exit 0; \
 		fi; \
-		BOARD_DIR=$(src)/board/$$VENDOR/$$BOARD; \
+		BOARD_DIR=$(srctree)/board/$$VENDOR/$$BOARD; \
 		if [ "$$HANDOFF_PATH" ]; then \
 			echo "[INFO] Using manually specified handoff folder: $$HANDOFF_PATH"; \
 		else \
@@ -44,5 +44,5 @@ socfpga_g5_handoff_prepare:
 		fi; \
 		echo "[INFO] Found hiof file: $$HIOF_FILE"; \
 		echo "[INFO] Running BSP generator..."; \
-		python3 $(src)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \
+		python3 $(srctree)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \
 		echo "[DONE] SoCFPGA QTS handoff conversion complete."
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 074b9691af8..61982c2d508 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -7,7 +7,7 @@
 #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
 #define _SOCFPGA_SOC64_BASE_HARDWARE_H_
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SOCFPGA_CCU_ADDRESS			0x1c000000
 #define SOCFPGA_F2SDRAM_MGR_ADDRESS		0x18001000
 #define SOCFPGA_SMMU_ADDRESS			0x16000000
@@ -47,9 +47,9 @@
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
 #define SOCFPGA_FW_MPFE_SCR_ADDRESS		0xf8020000
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
-	IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \
-	IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
+	IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || \
+	IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
 #else
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
@@ -84,6 +84,6 @@
 #define SOCFPGA_OCRAM_ADDRESS			0xffe00000
 #define GICD_BASE				0xfffc1000
 #define GICC_BASE				0xfffc2000
-#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */
+#endif /* IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) */
 
 #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index f0431c081d8..48001dbff21 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -17,22 +17,22 @@ void cm_print_clock_quick_summary(void);
 unsigned long cm_get_mpu_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
 
-#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+#if defined(CONFIG_ARCH_SOCFPGA_SOC64)
 int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #endif
 #endif
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 #include <asm/arch/clock_manager_gen5.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
 #include <asm/arch/clock_manager_arria10.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#elif defined(CONFIG_ARCH_SOCFPGA_STRATIX10)
 #include <asm/arch/clock_manager_s10.h>
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 #include <asm/arch/clock_manager_agilex.h>
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #include <asm/arch/clock_manager_agilex5.h>
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 #include <asm/arch/clock_manager_n5x.h>
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 2b436b64816..b47b577ae75 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -138,7 +138,7 @@ struct socfpga_firwall_l4_sys {
 #define MPUREGION0_ENABLE				BIT(0)
 #define NONMPUREGION0_ENABLE				BIT(8)
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
 	writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \
 	writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg))
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index 481b66bbd86..fc084823b51 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -9,9 +9,9 @@
 
 #include <altera.h>
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 #include <asm/arch/fpga_manager_gen5.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
 #include <asm/arch/fpga_manager_arria10.h>
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index b8f2f73e283..ae5af1f0100 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -19,7 +19,7 @@
 #define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
 #define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
 #define SOC64_HANDOFF_MAGIC_SDRAM	0x5344524D
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_MAGIC_PERI	0x50455249
 #else
 #define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
@@ -29,11 +29,11 @@
 #define SOC64_HANDOFF_OFFSET_DATA	0x10
 #define SOC64_HANDOFF_SIZE		4096
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
-	IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
-	IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) || \
+	IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \
+	IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 #define SOC64_HANDOFF_BASE		0xFFE3F000
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 #define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x634)
 /* DDR handoff */
 #define SOC64_HANDOFF_DDR_BASE	(SOC64_HANDOFF_BASE + 0x610)
@@ -43,9 +43,9 @@
 #else
 #define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x610)
 #endif
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_BASE		0x0007F000
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 #define SOC64_HANDOFF_BASE		0xFFE5F000
 #define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x630)
 
@@ -76,17 +76,17 @@
 #define SOC64_HANDOFF_FPGA		(SOC64_HANDOFF_BASE + 0x330)
 #define SOC64_HANDOFF_DELAY		(SOC64_HANDOFF_BASE + 0x3F0)
 #define SOC64_HANDOFF_CLOCK		(SOC64_HANDOFF_BASE + 0x580)
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_PERI		(SOC64_HANDOFF_BASE + 0x620)
 #define SOC64_HANDOFF_PERI_LEN		1
 #define SOC64_HANDOFF_SDRAM		(SOC64_HANDOFF_BASE + 0x634)
 #define SOC64_HANDOFF_SDRAM_LEN		5
 #endif
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
 #define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x608)
 #define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x60C)
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x60c)
 #define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x610)
 #else
@@ -96,9 +96,9 @@
 
 #define SOC64_HANDOFF_MUX_LEN			96
 #define SOC64_HANDOFF_IOCTL_LEN			96
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)
 #define SOC64_HANDOFF_FPGA_LEN			42
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_FPGA_LEN			44
 #else
 #define SOC64_HANDOFF_FPGA_LEN			40
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 0b80e952131..5a6a76b5ace 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -24,7 +24,7 @@ void socfpga_fpga_add(void *fpga_desc);
 static inline void socfpga_fpga_add(void *fpga_desc) {}
 #endif
 
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+#ifdef CONFIG_ARCH_SOCFPGA_GEN5
 void socfpga_sdram_remap_zero(void);
 static inline bool socfpga_is_booting_from_fpga(void)
 {
@@ -35,14 +35,14 @@ static inline bool socfpga_is_booting_from_fpga(void)
 }
 #endif
 
-#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
 void socfpga_init_security_policies(void);
 void socfpga_sdram_remap_zero(void);
 #endif
 
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
-	defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \
-	defined(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#if defined(CONFIG_ARCH_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_ARCH_SOCFPGA_AGILEX) || \
+	defined(CONFIG_ARCH_SOCFPGA_AGILEX7M)
 int is_fpga_config_ready(void);
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 1d68034cb55..97bb48474f3 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -39,11 +39,11 @@ void socfpga_per_reset_all(void);
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 #include <asm/arch/reset_manager_gen5.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
 #include <asm/arch/reset_manager_arria10.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
+#elif defined(CONFIG_ARCH_SOCFPGA_SOC64)
 #include <asm/arch/reset_manager_soc64.h>
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index 4b010be9ee8..5d72480dc13 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -39,7 +39,7 @@ void socfpga_bridges_reset(int enable, unsigned int mask);
 #define RSTMGR_STAT_SDMWARMRST		0x2
 #define RSTMGR_STAT_MPU0RST_BITPOS	8
 #define RSTMGR_STAT_L4WD0RST_BITPOS	16
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define RSTMGR_STAT_L4WD0RST_BIT	0x1F0000
 #define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
 		RSTMGR_STAT_L4WD0RST_BIT)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 79cb9e6064a..9a261eb9383 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -7,9 +7,9 @@
 
 #ifndef __ASSEMBLY__
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 #include <asm/arch/sdram_gen5.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
 #include <asm/arch/sdram_arria10.h>
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 5603eaa3d02..3d5bd81e1b5 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -8,7 +8,7 @@
 
 phys_addr_t socfpga_get_sysmgr_addr(void);
 
-#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+#if defined(CONFIG_ARCH_SOCFPGA_SOC64)
 #include <asm/arch/system_manager_soc64.h>
 #else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
@@ -85,9 +85,9 @@ phys_addr_t socfpga_get_sysmgr_addr(void);
 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK	BIT(1)
 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK	BIT(1)
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_ARCH_SOCFPGA_GEN5)
 #include <asm/arch/system_manager_gen5.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
 #include <asm/arch/system_manager_arria10.h>
 #endif
 
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index f768a3a55cb..8be98d0ee46 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -12,7 +12,7 @@ void sysmgr_pinmux_init(void);
 void populate_sysmgr_fpgaintf_module(void);
 void populate_sysmgr_pinmux(void);
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 #define SYSMGR_SOC64_SILICONID_1		0x00
 #define SYSMGR_SOC64_SILICONID_2		0x04
 #define SYSMGR_SOC64_MPU_STATUS			0x10
@@ -62,7 +62,7 @@ void populate_sysmgr_pinmux(void);
 #else
 #define SYSMGR_SOC64_NAND_AXUSER		0x5c
 #define SYSMGR_SOC64_DMA_L3MASTER		0x74
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 #define SYSMGR_SOC64_DDR_MODE			0xb8
 #else
 #define SYSMGR_SOC64_HMC_CLK			0xb4
@@ -73,7 +73,7 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_GPI			0xe8
 #define SYSMGR_SOC64_MPU			0xf0
 #define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK	GENMASK(27, 0)
-#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/
+#endif /*CONFIG_ARCH_SOCFPGA_AGILEX5*/
 
 #define SYSMGR_SOC64_DMA			0x20
 #define SYSMGR_SOC64_DMA_PERIPH			0x24
@@ -218,7 +218,7 @@ void populate_sysmgr_pinmux(void);
 
 #define SYSMGR_WDDBG_PAUSE_ALL_CPU	0xFF0F0F0F
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 #define	SYSMGR_SOC64_DDR_MODE_MSK	BIT(0)
 #endif
 
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 07694107c8a..1eef7893e54 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,7 +54,7 @@ struct bsel bsel_str[] = {
 
 int dram_init(void)
 {
-#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 	struct spl_handoff *ho;
 
 	ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
@@ -65,7 +65,7 @@ int dram_init(void)
 #else
 	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;
-#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
+#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */
 
 	return 0;
 }
@@ -261,21 +261,21 @@ void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();
 
-	if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
-	    !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) &&
-	    !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
+	if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
+	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
+	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) {
 		ret = socfpga_get_base_addr("altr,sys-mgr",
 					    &socfpga_sysmgr_base);
 		if (ret)
 			hang();
 	}
 
-	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+	if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X))
 		ret = socfpga_get_base_addr("intel,n5x-clkmgr",
 					    &socfpga_clkmgr_base);
-	else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
-		 !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) &&
-		 !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+	else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
+		 !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
+		 !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5))
 		ret = socfpga_get_base_addr("altr,clk-mgr",
 					    &socfpga_clkmgr_base);
 
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 5222b384434..b74685df168 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -94,7 +94,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
 int print_cpuinfo(void)
 {
 	printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
-	       IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");
+	       IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index 1dc44ab4797..33520aae6cd 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -9,7 +9,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 static struct mm_region socfpga_agilex5_mem_map[] = {
 	{
 		/* OCRAM 512KB */
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index abb62a9b49f..67b16180ae7 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -79,7 +79,7 @@ static void socfpga_f2s_bridges_reset(int enable, unsigned int mask)
 	u32 flaginstatus_idleack = 0;
 	u32 flaginstatus_respempty = 0;
 
-	if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) {
+	if (CONFIG_IS_ENABLED(ARCH_SOCFPGA_STRATIX10)) {
 		/* Support fpga2soc and f2sdram */
 		brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK |
 				   RSTMGR_BRGMODRST_F2SDRAM0_MASK |
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c
index 913f93c8f94..94624deef10 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -12,7 +12,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 /*
  * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse
  * generation and setting PORT_OVERCURRENT bit so that until we turn on the
@@ -39,7 +39,7 @@ void sysmgr_pinmux_init(void)
 	populate_sysmgr_pinmux();
 	populate_sysmgr_fpgaintf_module();
 
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 	sysmgr_config_usb3();
 #endif
 }
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 7105cdc4905..ecde90f76f4 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -29,13 +29,13 @@ static enum endianness check_endianness(u32 handoff)
 	case SOC64_HANDOFF_MAGIC_DELAY:
 	case SOC64_HANDOFF_MAGIC_CLOCK:
 	case SOC64_HANDOFF_MAGIC_SDRAM:
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)
 	case SOC64_HANDOFF_MAGIC_PERI:
 #else
 	case SOC64_HANDOFF_MAGIC_MISC:
 #endif
 		return BIG_ENDIAN;
-#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)
 	case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
 		debug("%s: umctl2 handoff data\n", __func__);
 		return LITTLE_ENDIAN;