Merge patch series "Relocate U-Boot in the last bank"

Ilias Apalodimas <[email protected]> says:

There was a discussion recently on the mailing lists regarding our
management of memory above ram_top [0]. The tl;dr is that we have two problems.

The first one is that U-Boot always relocates to the top of the first available
bank unless there's special board code to sidestep that. The second is we don't
successfully deal with devices that can only do 32-bit DMA.

This patch series deals with the first problem by adding a Kconfig option
allowing platforms to relocate to the top of the last discovered bank.

It's worth noting that this is easily testable with QEMU

qemu-system-aarch64 -m 8192 -smp 2 -nographic -cpu cortex-a57 \
    -machine virt,secure=off \
    -bios u-boot.bin \
    -device virtio-rng-pci \
    -drive id=os,if=none,file="$image" \
    -device virtio-blk-device,drive=os \
    -object memory-backend-ram,id=ram0,size=4G \
    -object memory-backend-ram,id=ram1,size=4G \
    -numa node,memdev=ram0 \
    -numa node,memdev=ram1

# RELOC_ADDR_TOP not set
Hit any key to stop autoboot: 0
=> bdinfo
[...]
relocaddr   = 0x000000013f66c000
reloc off   = 0x000000013f66c000
[...]
lmb_dump_all:
 memory.count = 0x1
 memory[0]	[0x40000000-0x23fffffff], 0x200000000 bytes, flags: none
 reserved.count = 0x2
 reserved[0]	[0x13d507000-0x13d509fff], 0x3000 bytes, flags: no-notify, no-overwrite
reserved[1]	[0x13d50aff0-0x23fffffff], 0x102af5010 bytes, flags: no-overwrite
devicetree  = board
[...]
TLB addr    = 0x000000013ffe0000
irq_sp      = 0x000000013e50aff0
sp start    = 0x000000013e50aff0
Early malloc usage: e88 / 2000
=>

# RELOC_ADDR_TOP enabled

=> bdinfo
[...]
relocaddr   = 0x000000023f66c000
reloc off   = 0x000000023f66c000
[...]
lmb_dump_all:
 memory.count = 0x1
 memory[0]	[0x40000000-0x23fffffff], 0x200000000 bytes, flags: none
 reserved.count = 0x2
 reserved[0]	[0x23d507000-0x23d509fff], 0x3000 bytes, flags: no-notify, no-overwrite
 reserved[1]	[0x23d50aff0-0x23fffffff], 0x2af5010 bytes, flags: no-overwrite
devicetree  = board
[...]
TLB addr    = 0x000000023ffe0000
irq_sp      = 0x000000023e50aff0
sp start    = 0x000000023e50aff0
Early malloc usage: e88 / 2000
=>

[0] https://lore.kernel.org/u-boot/CAC_iWjKFAzpj3B_MEW7-dnOrcAV-rfkhXXo8Bv0KgLNP2VJxRA@mail.gmail.com/

Link: https://lore.kernel.org/r/[email protected]

59 files changed, 314 insertions, 322 deletions

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6c85022556a..e59528e576e 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs)
 	}
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		mem_map[index].virt = gd->bd->bi_dram[i].start;
-		mem_map[index].phys = gd->bd->bi_dram[i].start;
-		mem_map[index].size = gd->bd->bi_dram[i].size;
+		mem_map[index].virt = gd->dram[i].start;
+		mem_map[index].phys = gd->dram[i].start;
+		mem_map[index].size = gd->dram[i].size;
 		mem_map[index].attrs = attrs;
 		index++;
 	}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index cbeac6d4383..88adcf35432 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,16 +538,16 @@ static inline void final_mmu_setup(void)
 		 */
 		switch (final_map[index].virt) {
 		case CFG_SYS_FSL_DRAM_BASE1:
-			final_map[index].virt = gd->bd->bi_dram[0].start;
-			final_map[index].phys = gd->bd->bi_dram[0].start;
-			final_map[index].size = gd->bd->bi_dram[0].size;
+			final_map[index].virt = gd->dram[0].start;
+			final_map[index].phys = gd->dram[0].start;
+			final_map[index].size = gd->dram[0].size;
 			break;
 #ifdef CFG_SYS_FSL_DRAM_BASE2
 		case CFG_SYS_FSL_DRAM_BASE2:
 #if (CONFIG_NR_DRAM_BANKS >= 2)
-			final_map[index].virt = gd->bd->bi_dram[1].start;
-			final_map[index].phys = gd->bd->bi_dram[1].start;
-			final_map[index].size = gd->bd->bi_dram[1].size;
+			final_map[index].virt = gd->dram[1].start;
+			final_map[index].phys = gd->dram[1].start;
+			final_map[index].size = gd->dram[1].size;
 #else
 			final_map[index].size = 0;
 #endif
@@ -556,9 +556,9 @@ static inline void final_mmu_setup(void)
 #ifdef CFG_SYS_FSL_DRAM_BASE3
 		case CFG_SYS_FSL_DRAM_BASE3:
 #if (CONFIG_NR_DRAM_BANKS >= 3)
-			final_map[index].virt = gd->bd->bi_dram[2].start;
-			final_map[index].phys = gd->bd->bi_dram[2].start;
-			final_map[index].size = gd->bd->bi_dram[2].size;
+			final_map[index].virt = gd->dram[2].start;
+			final_map[index].phys = gd->dram[2].start;
+			final_map[index].size = gd->dram[2].size;
 #else
 			final_map[index].size = 0;
 #endif
@@ -1396,10 +1396,10 @@ static int tfa_dram_init_banksize(void)
 		}
 
 		debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
-		gd->bd->bi_dram[i].start = res.a1;
-		gd->bd->bi_dram[i].size = res.a2;
+		gd->dram[i].start = res.a1;
+		gd->dram[i].size = res.a2;
 
-		dram_size -= gd->bd->bi_dram[i].size;
+		dram_size -= gd->dram[i].size;
 
 		i++;
 	} while (dram_size);
@@ -1410,24 +1410,24 @@ static int tfa_dram_init_banksize(void)
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
-	if (gd->bd->bi_dram[2].size >=
-	    board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
-		gd->arch.resv_ram = gd->bd->bi_dram[2].start +
-			    gd->bd->bi_dram[2].size -
-			    board_reserve_ram_top(gd->bd->bi_dram[2].size);
+	if (gd->dram[2].size >=
+	    board_reserve_ram_top(gd->dram[2].size)) {
+		gd->arch.resv_ram = gd->dram[2].start +
+			    gd->dram[2].size -
+			    board_reserve_ram_top(gd->dram[2].size);
 	} else
 #endif
 	{
-		if (gd->bd->bi_dram[1].size >=
-		    board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
-			gd->arch.resv_ram = gd->bd->bi_dram[1].start +
-				gd->bd->bi_dram[1].size -
-				board_reserve_ram_top(gd->bd->bi_dram[1].size);
-		} else if (gd->bd->bi_dram[0].size >
-			   board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
-			gd->arch.resv_ram = gd->bd->bi_dram[0].start +
-				gd->bd->bi_dram[0].size -
-				board_reserve_ram_top(gd->bd->bi_dram[0].size);
+		if (gd->dram[1].size >=
+		    board_reserve_ram_top(gd->dram[1].size)) {
+			gd->arch.resv_ram = gd->dram[1].start +
+				gd->dram[1].size -
+				board_reserve_ram_top(gd->dram[1].size);
+		} else if (gd->dram[0].size >
+			   board_reserve_ram_top(gd->dram[0].size)) {
+			gd->arch.resv_ram = gd->dram[0].start +
+				gd->dram[0].size -
+				board_reserve_ram_top(gd->dram[0].size);
 		}
 	}
 #endif	/* CONFIG_RESV_RAM */
@@ -1464,30 +1464,30 @@ int dram_init_banksize(void)
 	}
 #endif
 
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
+		gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+		gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
+		gd->dram[1].size = gd->ram_size -
 					  CFG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
-		if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
-			gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
-			gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
+		if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
+			gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
+			gd->dram[2].size = gd->dram[1].size -
 						  CONFIG_SYS_DDR_BLOCK2_SIZE;
-			gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
+			gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
 		}
 #endif
 	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
+		gd->dram[0].size = gd->ram_size;
 	}
 #ifdef CFG_SYS_MEM_RESERVE_SECURE
-	if (gd->bd->bi_dram[0].size >
+	if (gd->dram[0].size >
 				CFG_SYS_MEM_RESERVE_SECURE) {
-		gd->bd->bi_dram[0].size -=
+		gd->dram[0].size -=
 				CFG_SYS_MEM_RESERVE_SECURE;
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				      gd->bd->bi_dram[0].size;
+		gd->arch.secure_ram = gd->dram[0].start +
+				      gd->dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 		gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	}
@@ -1496,24 +1496,24 @@ int dram_init_banksize(void)
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
-	if (gd->bd->bi_dram[2].size >=
-	    board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
-		gd->arch.resv_ram = gd->bd->bi_dram[2].start +
-			    gd->bd->bi_dram[2].size -
-			    board_reserve_ram_top(gd->bd->bi_dram[2].size);
+	if (gd->dram[2].size >=
+	    board_reserve_ram_top(gd->dram[2].size)) {
+		gd->arch.resv_ram = gd->dram[2].start +
+			    gd->dram[2].size -
+			    board_reserve_ram_top(gd->dram[2].size);
 	} else
 #endif
 	{
-		if (gd->bd->bi_dram[1].size >=
-		    board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
-			gd->arch.resv_ram = gd->bd->bi_dram[1].start +
-				gd->bd->bi_dram[1].size -
-				board_reserve_ram_top(gd->bd->bi_dram[1].size);
-		} else if (gd->bd->bi_dram[0].size >
-			   board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
-			gd->arch.resv_ram = gd->bd->bi_dram[0].start +
-				gd->bd->bi_dram[0].size -
-				board_reserve_ram_top(gd->bd->bi_dram[0].size);
+		if (gd->dram[1].size >=
+		    board_reserve_ram_top(gd->dram[1].size)) {
+			gd->arch.resv_ram = gd->dram[1].start +
+				gd->dram[1].size -
+				board_reserve_ram_top(gd->dram[1].size);
+		} else if (gd->dram[0].size >
+			   board_reserve_ram_top(gd->dram[0].size)) {
+			gd->arch.resv_ram = gd->dram[0].start +
+				gd->dram[0].size -
+				board_reserve_ram_top(gd->dram[0].size);
 		}
 	}
 #endif	/* CONFIG_RESV_RAM */
@@ -1535,8 +1535,8 @@ int dram_init_banksize(void)
 					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 					  NULL, NULL, NULL);
 		if (dp_ddr_size) {
-			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-			gd->bd->bi_dram[2].size = dp_ddr_size;
+			gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+			gd->dram[2].size = dp_ddr_size;
 		} else {
 			puts("Not detected");
 		}
@@ -1567,8 +1567,8 @@ void lmb_arch_add_memory(void)
 		if (i == 2)
 			continue;	/* skip DP-DDR */
 #endif
-		ram_start = gd->bd->bi_dram[i].start;
-		ram_size = gd->bd->bi_dram[i].size;
+		ram_start = gd->dram[i].start;
+		ram_size = gd->dram[i].size;
 #ifdef CONFIG_RESV_RAM
 		if (gd->arch.resv_ram >= ram_start &&
 		    gd->arch.resv_ram < ram_start + ram_size)
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 2671f9a0ebf..a82ceeaf22f 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob)
 {
 	__maybe_unused int ret = 0;
 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
-	struct bd_info *bd = gd->bd;
 	int bank;
 	u64 start[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = bd->bi_dram[bank].start;
-		size[bank] = bd->bi_dram[bank].size;
+		start[bank] = gd->dram[bank].start;
+		size[bank] = gd->dram[bank].size;
 #ifdef CONFIG_ARMV7_NONSEC
 		ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
 		if (ret)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 1cde655bc80..9a115cc6078 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd)
 		params->hdr.tag = ATAG_MEM;
 		params->hdr.size = tag_size (tag_mem32);
 
-		params->u.mem.start = bd->bi_dram[i].start;
-		params->u.mem.size = bd->bi_dram[i].size;
+		params->u.mem.start = gd->dram[i].start;
+		params->u.mem.size = gd->dram[i].size;
 
 		params = tag_next (params);
 	}
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 947012f2996..28bb6fd36c8 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
 
 __weak void dram_bank_mmu_setup(int bank)
 {
-	struct bd_info *bd = gd->bd;
 	int	i;
 
-	/* bd->bi_dram is available only after relocation */
+	/* gd->dram is available only after relocation */
 	if ((gd->flags & GD_FLG_RELOC) == 0)
 		return;
 
 	debug("%s: bank: %d\n", __func__, bank);
-	for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
-	     i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
-		 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
+	for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT;
+	     i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) +
+		 (gd->dram[bank].size >> MMU_SECTION_SHIFT);
 	     i++)
 		set_section_dcache(i, DCACHE_DEFAULT_OPTION);
 }
diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c
index 1f672eee2c8..2268661de93 100644
--- a/arch/arm/lib/image.c
+++ b/arch/arm/lib/image.c
@@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
 	if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3)))
 		dst = image - text_offset;
 	else
-		dst = gd->bd->bi_dram[0].start;
+		dst = gd->dram[0].start;
 
 	*relocated_addr = ALIGN(dst, SZ_2M) + text_offset;
 
diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c
index ab32706a79d..f33527ca129 100644
--- a/arch/arm/mach-airoha/an7581/init.c
+++ b/arch/arm/mach-airoha/an7581/init.c
@@ -23,12 +23,12 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = gd->ram_base;
-	gd->bd->bi_dram[0].size = get_effective_memsize();
+	gd->dram[0].start = gd->ram_base;
+	gd->dram[0].size = get_effective_memsize();
 
 	if (gd->ram_size > SZ_2G) {
-		gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G;
-		gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+		gd->dram[1].start = gd->ram_base + SZ_2G;
+		gd->dram[1].size = gd->ram_size - SZ_2G;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 20054f54089..e74a5a76919 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -807,8 +807,8 @@ void build_mem_map(void)
 		;
 
 	/* Align RAM mapping to page boundaries */
-	base = gd->bd->bi_dram[0].start;
-	size = gd->bd->bi_dram[0].size;
+	base = gd->dram[0].start;
+	size = gd->dram[0].size;
 	size += (base - ALIGN_DOWN(base, SZ_4K));
 	base = ALIGN_DOWN(base, SZ_4K);
 	size = ALIGN(size, SZ_4K);
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index 07125eac7cd..2281686d633 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -33,8 +33,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 86b11bdf2ac..e1284833ac5 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -311,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
 static inline bool check_in_dram(ulong addr)
 {
 	int i;
-	struct bd_info *bd = gd->bd;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
-		if (bd->bi_dram[i].size) {
-			if (addr >= bd->bi_dram[i].start &&
-			    addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+		if (gd->dram[i].size) {
+			if (addr >= gd->dram[i].start &&
+			    addr < (gd->dram[i].start + gd->dram[i].size))
 				return true;
 		}
 	}
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 71a3b341913..34712747fa3 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -111,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
 static inline bool check_in_dram(ulong addr)
 {
 	int i;
-	struct bd_info *bd = gd->bd;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
-		if (bd->bi_dram[i].size) {
-			if (addr >= bd->bi_dram[i].start &&
-			    addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+		if (gd->dram[i].size) {
+			if (addr >= gd->dram[i].start &&
+			    addr < (gd->dram[i].start + gd->dram[i].size))
 				return true;
 		}
 	}
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index f4738e3fda8..b52675d8aba 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank)
 	phys_size_t size;
 
 	while (current_bank > 0) {
-		if (gd->bd->bi_dram[current_bank - 1].start >
-		    gd->bd->bi_dram[current_bank].start) {
-			start = gd->bd->bi_dram[current_bank - 1].start;
-			size = gd->bd->bi_dram[current_bank - 1].size;
+		if (gd->dram[current_bank - 1].start >
+		    gd->dram[current_bank].start) {
+			start = gd->dram[current_bank - 1].start;
+			size = gd->dram[current_bank - 1].size;
 
-			gd->bd->bi_dram[current_bank - 1].start =
-				gd->bd->bi_dram[current_bank].start;
-			gd->bd->bi_dram[current_bank - 1].size =
-				gd->bd->bi_dram[current_bank].size;
+			gd->dram[current_bank - 1].start =
+				gd->dram[current_bank].start;
+			gd->dram[current_bank - 1].size =
+				gd->dram[current_bank].size;
 
-			gd->bd->bi_dram[current_bank].start = start;
-			gd->bd->bi_dram[current_bank].size = size;
+			gd->dram[current_bank].start = start;
+			gd->dram[current_bank].size = size;
 		}
 		current_bank--;
 	}
@@ -643,24 +643,24 @@ int dram_init_banksize(void)
 				continue;
 
 			if (start >= phys_sdram_1_start && start <= end1) {
-				gd->bd->bi_dram[i].start = start;
+				gd->dram[i].start = start;
 
 				if ((end + 1) <= end1)
-					gd->bd->bi_dram[i].size =
+					gd->dram[i].size =
 						end - start + 1;
 				else
-					gd->bd->bi_dram[i].size = end1 - start;
+					gd->dram[i].size = end1 - start;
 
 				dram_bank_sort(i);
 				i++;
 			} else if (start >= phys_sdram_2_start && start <= end2) {
-				gd->bd->bi_dram[i].start = start;
+				gd->dram[i].start = start;
 
 				if ((end + 1) <= end2)
-					gd->bd->bi_dram[i].size =
+					gd->dram[i].size =
 						end - start + 1;
 				else
-					gd->bd->bi_dram[i].size = end2 - start;
+					gd->dram[i].size = end2 - start;
 
 				dram_bank_sort(i);
 				i++;
@@ -670,10 +670,10 @@ int dram_init_banksize(void)
 
 	/* If error, set to the default value */
 	if (!i) {
-		gd->bd->bi_dram[0].start = phys_sdram_1_start;
-		gd->bd->bi_dram[0].size = phys_sdram_1_size;
-		gd->bd->bi_dram[1].start = phys_sdram_2_start;
-		gd->bd->bi_dram[1].size = phys_sdram_2_size;
+		gd->dram[0].start = phys_sdram_1_start;
+		gd->dram[0].size = phys_sdram_1_size;
+		gd->dram[1].start = phys_sdram_2_start;
+		gd->dram[1].size = phys_sdram_2_size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 498bbe6704f..e600fd6b33e 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -224,11 +224,11 @@ void enable_caches(void)
 
 	while (i < CONFIG_NR_DRAM_BANKS &&
 	       entry < ARRAY_SIZE(imx8m_mem_map)) {
-		if (gd->bd->bi_dram[i].start == 0)
+		if (gd->dram[i].start == 0)
 			break;
-		imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
-		imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
-		imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
+		imx8m_mem_map[entry].phys = gd->dram[i].start;
+		imx8m_mem_map[entry].virt = gd->dram[i].start;
+		imx8m_mem_map[entry].size = gd->dram[i].size;
 		imx8m_mem_map[entry].attrs = attrs;
 		debug("Added memory mapping (%d): %llx %llx\n", entry,
 		      imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
@@ -290,24 +290,24 @@ int dram_init_banksize(void)
 		sdram_b2_size = 0;
 	}
 
-	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	gd->dram[bank].start = PHYS_SDRAM;
 	if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
 		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 		phys_size_t optee_size = (size_t)rom_pointer[1];
 
-		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		gd->dram[bank].size = optee_start - gd->dram[bank].start;
 		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
 			if (++bank >= CONFIG_NR_DRAM_BANKS) {
 				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 				return -1;
 			}
 
-			gd->bd->bi_dram[bank].start = optee_start + optee_size;
-			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
-				sdram_b1_size - gd->bd->bi_dram[bank].start;
+			gd->dram[bank].start = optee_start + optee_size;
+			gd->dram[bank].size = PHYS_SDRAM +
+				sdram_b1_size - gd->dram[bank].start;
 		}
 	} else {
-		gd->bd->bi_dram[bank].size = sdram_b1_size;
+		gd->dram[bank].size = sdram_b1_size;
 	}
 
 	if (sdram_b2_size) {
@@ -315,8 +315,8 @@ int dram_init_banksize(void)
 			puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
 			return -1;
 		}
-		gd->bd->bi_dram[bank].start = 0x100000000UL;
-		gd->bd->bi_dram[bank].size = sdram_b2_size;
+		gd->dram[bank].start = 0x100000000UL;
+		gd->dram[bank].size = sdram_b2_size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index ccdb949a9da..6d6f3b81aca 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -512,11 +512,11 @@ void enable_caches(void)
 
 		while (i < CONFIG_NR_DRAM_BANKS &&
 		       entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
-			if (gd->bd->bi_dram[i].start == 0)
+			if (gd->dram[i].start == 0)
 				break;
-			imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
-			imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
-			imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
+			imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start;
+			imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start;
+			imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size;
 			imx8ulp_arm64_mem_map[entry].attrs = attrs;
 			debug("Added memory mapping (%d): %llx %llx\n", entry,
 			      imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
@@ -568,24 +568,24 @@ int dram_init_banksize(void)
 	if (ret)
 		return ret;
 
-	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	gd->dram[bank].start = PHYS_SDRAM;
 	if (rom_pointer[1]) {
 		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 		phys_size_t optee_size = (size_t)rom_pointer[1];
 
-		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		gd->dram[bank].size = optee_start - gd->dram[bank].start;
 		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
 			if (++bank >= CONFIG_NR_DRAM_BANKS) {
 				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 				return -1;
 			}
 
-			gd->bd->bi_dram[bank].start = optee_start + optee_size;
-			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
-				sdram_size - gd->bd->bi_dram[bank].start;
+			gd->dram[bank].start = optee_start + optee_size;
+			gd->dram[bank].size = PHYS_SDRAM +
+				sdram_size - gd->dram[bank].start;
 		}
 	} else {
-		gd->bd->bi_dram[bank].size = sdram_size;
+		gd->dram[bank].size = sdram_size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index 123c1d51a4d..82b3cdffeea 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -356,11 +356,11 @@ void enable_caches(void)
 
 	while (i < CONFIG_NR_DRAM_BANKS &&
 	       entry < ARRAY_SIZE(imx9_mem_map)) {
-		if (gd->bd->bi_dram[i].start == 0)
+		if (gd->dram[i].start == 0)
 			break;
-		imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start;
-		imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start;
-		imx9_mem_map[entry].size = gd->bd->bi_dram[i].size;
+		imx9_mem_map[entry].phys = gd->dram[i].start;
+		imx9_mem_map[entry].virt = gd->dram[i].start;
+		imx9_mem_map[entry].size = gd->dram[i].size;
 		imx9_mem_map[entry].attrs = attrs;
 		debug("Added memory mapping (%d): %llx %llx\n", entry,
 		      imx9_mem_map[entry].phys, imx9_mem_map[entry].size);
@@ -453,24 +453,24 @@ int dram_init_banksize(void)
 		sdram_b2_size = 0;
 	}
 
-	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	gd->dram[bank].start = PHYS_SDRAM;
 	if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) {
 		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 		phys_size_t optee_size = (size_t)rom_pointer[1];
 
-		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		gd->dram[bank].size = optee_start - gd->dram[bank].start;
 		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
 			if (++bank >= CONFIG_NR_DRAM_BANKS) {
 				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 				return -1;
 			}
 
-			gd->bd->bi_dram[bank].start = optee_start + optee_size;
-			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
-				sdram_b1_size - gd->bd->bi_dram[bank].start;
+			gd->dram[bank].start = optee_start + optee_size;
+			gd->dram[bank].size = PHYS_SDRAM +
+				sdram_b1_size - gd->dram[bank].start;
 		}
 	} else {
-		gd->bd->bi_dram[bank].size = sdram_b1_size;
+		gd->dram[bank].size = sdram_b1_size;
 	}
 
 	if (sdram_b2_size) {
@@ -478,8 +478,8 @@ int dram_init_banksize(void)
 			puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
 			return -1;
 		}
-		gd->bd->bi_dram[bank].start = 0x100000000UL;
-		gd->bd->bi_dram[bank].size = sdram_b2_size;
+		gd->dram[bank].start = 0x100000000UL;
+		gd->dram[bank].size = sdram_b2_size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 6576ecefd5f..0c731e76329 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -367,11 +367,11 @@ void enable_caches(void)
 
 	while (i < CONFIG_NR_DRAM_BANKS &&
 	       entry < ARRAY_SIZE(imx93_mem_map)) {
-		if (gd->bd->bi_dram[i].start == 0)
+		if (gd->dram[i].start == 0)
 			break;
-		imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;
-		imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;
-		imx93_mem_map[entry].size = gd->bd->bi_dram[i].size;
+		imx93_mem_map[entry].phys = gd->dram[i].start;
+		imx93_mem_map[entry].virt = gd->dram[i].start;
+		imx93_mem_map[entry].size = gd->dram[i].size;
 		imx93_mem_map[entry].attrs = attrs;
 		debug("Added memory mapping (%d): %llx %llx\n", entry,
 		      imx93_mem_map[entry].phys, imx93_mem_map[entry].size);
@@ -445,24 +445,24 @@ int dram_init_banksize(void)
 		sdram_b2_size = 0;
 	}
 
-	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	gd->dram[bank].start = PHYS_SDRAM;
 	if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
 		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 		phys_size_t optee_size = (size_t)rom_pointer[1];
 
-		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		gd->dram[bank].size = optee_start - gd->dram[bank].start;
 		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
 			if (++bank >= CONFIG_NR_DRAM_BANKS) {
 				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 				return -1;
 			}
 
-			gd->bd->bi_dram[bank].start = optee_start + optee_size;
-			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
-				sdram_b1_size - gd->bd->bi_dram[bank].start;
+			gd->dram[bank].start = optee_start + optee_size;
+			gd->dram[bank].size = PHYS_SDRAM +
+				sdram_b1_size - gd->dram[bank].start;
 		}
 	} else {
-		gd->bd->bi_dram[bank].size = sdram_b1_size;
+		gd->dram[bank].size = sdram_b1_size;
 	}
 
 	if (sdram_b2_size) {
@@ -470,8 +470,8 @@ int dram_init_banksize(void)
 			puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
 			return -1;
 		}
-		gd->bd->bi_dram[bank].start = 0x100000000UL;
-		gd->bd->bi_dram[bank].size = sdram_b2_size;
+		gd->dram[bank].start = 0x100000000UL;
+		gd->dram[bank].size = sdram_b2_size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c
index 180a745d435..5f7709e00b0 100644
--- a/arch/arm/mach-imx/mx5/mx53_dram.c
+++ b/arch/arm/mach-imx/mx5/mx53_dram.c
@@ -35,11 +35,11 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
 
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+	gd->dram[1].start = PHYS_SDRAM_2;
+	gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 57ae81c7834..1029c1e4e85 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit)
 #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = imx_ddr_size();
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c
index 6e3e60cdc86..35c30b1a16f 100644
--- a/arch/arm/mach-k3/k3-ddr.c
+++ b/arch/arm/mach-k3/k3-ddr.c
@@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image)
 	dram_init_banksize();
 
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = gd->bd->bi_dram[bank].start;
-		size[bank] = gd->bd->bi_dram[bank].size;
+		start[bank] = gd->dram[bank].start;
+		size[bank] = gd->dram[bank].size;
 	}
 
 	ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
index be2d9a25bf9..3ebb4294bdd 100644
--- a/arch/arm/mach-mvebu/alleycat5/cpu.c
+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c
@@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void)
 	/*
 	 * Config single DRAM bank
 	 */
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c
index 17525691e68..38d9b40f482 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void)
 		 * build_mem_map.
 		 */
 		if (last_end == dram_wins[win].base) {
-			gd->bd->bi_dram[bank - 1].size += size;
+			gd->dram[bank - 1].size += size;
 			last_end += size;
 		} else {
 			if (bank == CONFIG_NR_DRAM_BANKS) {
@@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void)
 				return -ENOBUFS;
 			}
 
-			gd->bd->bi_dram[bank].start = dram_wins[win].base;
-			gd->bd->bi_dram[bank].size = size;
+			gd->dram[bank].start = dram_wins[win].base;
+			gd->dram[bank].size = size;
 			last_end = dram_wins[win].base + size;
 			++bank;
 		}
@@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void)
 	 * the rest with zeros.
 	 */
 	for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
-		gd->bd->bi_dram[bank].start = 0;
-		gd->bd->bi_dram[bank].size = 0;
+		gd->dram[bank].start = 0;
+		gd->dram[bank].size = 0;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c
index fd58551d0e3..af37dfa2252 100644
--- a/arch/arm/mach-mvebu/armada8k/dram.c
+++ b/arch/arm/mach-mvebu/armada8k/dram.c
@@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void)
 	 */
 	phys_size_t max_bank0_size = SZ_4G - SZ_1G;
 
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
 	if (gd->ram_size <= max_bank0_size) {
-		gd->bd->bi_dram[0].size = gd->ram_size;
+		gd->dram[0].size = gd->ram_size;
 		return 0;
 	}
 
-	gd->bd->bi_dram[0].size = max_bank0_size;
+	gd->dram[0].size = max_bank0_size;
 	if (CONFIG_NR_DRAM_BANKS > 1) {
-		gd->bd->bi_dram[1].start = SZ_4G;
-		gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
+		gd->dram[1].start = SZ_4G;
+		gd->dram[1].size = gd->ram_size - max_bank0_size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c
index c00c6b9b3fc..41eaaa24bd0 100644
--- a/arch/arm/mach-mvebu/dram.c
+++ b/arch/arm/mach-mvebu/dram.c
@@ -294,11 +294,11 @@ int dram_init_banksize(void)
 	int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
-		gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
+		gd->dram[i].start = mvebu_sdram_bar(i);
+		gd->dram[i].size = mvebu_sdram_bs(i);
 
 		/* Clip the banksize to 1GiB if it exceeds the max size */
-		size += gd->bd->bi_dram[i].size;
+		size += gd->dram[i].size;
 		if (size > MVEBU_SDRAM_SIZE_MAX)
 			mvebu_sdram_bs_set(i, 0x40000000);
 	}
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 8699cf46b67..729533d02d4 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -80,8 +80,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c
index 200a08fa5c8..f08a9b263f6 100644
--- a/arch/arm/mach-omap2/omap-cache.c
+++ b/arch/arm/mach-omap2/omap-cache.c
@@ -53,11 +53,10 @@ void enable_caches(void)
 
 void dram_bank_mmu_setup(int bank)
 {
-	struct bd_info *bd = gd->bd;
 	int	i;
 
-	u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
-	u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+	u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT;
+	u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT;
 	u32 end = start + size;
 
 	debug("%s: bank: %d\n", __func__, bank);
diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c
index 049eedfeb65..67e14d70e92 100644
--- a/arch/arm/mach-omap2/omap3/emif4.c
+++ b/arch/arm/mach-omap2/omap3/emif4.c
@@ -150,10 +150,10 @@ int dram_init_banksize(void)
 	size0 = get_sdr_cs_size(CS0);
 	size1 = get_sdr_cs_size(CS1);
 
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = size0;
+	gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->dram[1].size = size1;
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c
index 24fae484369..c4187369c29 100644
--- a/arch/arm/mach-omap2/omap3/sdrc.c
+++ b/arch/arm/mach-omap2/omap3/sdrc.c
@@ -222,10 +222,10 @@ int dram_init_banksize(void)
 	size0 = get_sdr_cs_size(CS0);
 	size1 = get_sdr_cs_size(CS1);
 
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
+	gd->dram[0].start = PHYS_SDRAM_1;
+	gd->dram[0].size = size0;
+	gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->dram[1].size = size1;
 
 	return 0;
 }
diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
index 0130cad7678..e316c2cc40e 100644
--- a/arch/arm/mach-owl/soc.c
+++ b/arch/arm/mach-owl/soc.c
@@ -50,8 +50,8 @@ int dram_init(void)
 /* This is called after dram_init() so use get_ram_size result */
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c
index d24419f5daa..f7dc2be6cca 100644
--- a/arch/arm/mach-renesas/memmap-gen3.c
+++ b/arch/arm/mach-renesas/memmap-gen3.c
@@ -70,8 +70,8 @@ void enable_caches(void)
 
 	/* Generate entires for DRAM in 32bit address space */
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start = gd->bd->bi_dram[bank].start;
-		size = gd->bd->bi_dram[bank].size;
+		start = gd->dram[bank].start;
+		size = gd->dram[bank].size;
 
 		/* Skip empty DRAM banks */
 		if (!size)
@@ -114,8 +114,8 @@ void enable_caches(void)
 
 	/* Generate entires for DRAM in 64bit address space */
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start = gd->bd->bi_dram[bank].start;
-		size = gd->bd->bi_dram[bank].size;
+		start = gd->dram[bank].start;
+		size = gd->dram[bank].size;
 
 		/* Skip empty DRAM banks */
 		if (!size)
diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c
index 3b3c6f7cde9..5981b3c9c4d 100644
--- a/arch/arm/mach-renesas/memmap-rzg2l.c
+++ b/arch/arm/mach-renesas/memmap-rzg2l.c
@@ -67,8 +67,8 @@ void enable_caches(void)
 
 	/* Generate entries for DRAM in 32bit address space */
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start = gd->bd->bi_dram[bank].start;
-		size = gd->bd->bi_dram[bank].size;
+		start = gd->dram[bank].start;
+		size = gd->dram[bank].size;
 
 		/* Skip empty DRAM banks */
 		if (!size)
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index eedce7b9b08..c8de1a21024 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -243,14 +243,14 @@ int arch_cpu_init(void)
 
 int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
 {
-	size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size;
+	size_t ram_top = gd->dram[1].start + gd->dram[1].size;
 
 	if (ram_top > DRAM_GAP_START) {
-		bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start;
+		gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start;
 
 		if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) {
-			bd->bi_dram[2].start = DRAM_GAP_END;
-			bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start;
+			gd->dram[2].start = DRAM_GAP_END;
+			gd->dram[2].size = ram_top - gd->dram[2].start;
 		}
 	}
 
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index ea0e3621af7..f0923186fa6 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void)
 
 	/*
 	 * Rockchip guaranteed DDR_MEM is ordered so no need to worry about
-	 * bi_dram order.
+	 * dram order.
 	 */
 	for (i = 0, j = 0; i < ddr_info->count; i++, j++) {
 		phys_size_t size = ddr_info->bank[(i + ddr_info->count)];
@@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void)
 				 * split the region in two, one for before the
 				 * reserved memory area and one for after.
 				 */
-				gd->bd->bi_dram[j].start = start_addr;
-				gd->bd->bi_dram[j].size = rsrv_start - start_addr;
+				gd->dram[j].start = start_addr;
+				gd->dram[j].size = rsrv_start - start_addr;
 
 				j++;
 
@@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void)
 			return -ENOMEM;
 		}
 
-		gd->bd->bi_dram[j].start = start_addr;
-		gd->bd->bi_dram[j].size = size;
+		gd->dram[j].start = start_addr;
+		gd->dram[j].size = size;
 	}
 
 	return 0;
@@ -309,15 +309,15 @@ int dram_init_banksize(void)
 	      ret);
 
 	/* Reserve 2M for ATF bl31 */
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
-	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
+	gd->dram[0].size = top - gd->dram[0].start;
 
 	/* Add usable memory beyond the blob of space for peripheral near 4GB */
 	if (ram_top > SZ_4G && top < SZ_4G) {
-		gd->bd->bi_dram[1].start = SZ_4G;
-		gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
+		gd->dram[1].start = SZ_4G;
+		gd->dram[1].size = ram_top - gd->dram[1].start;
 	} else if (ram_top > SZ_4G && top == SZ_4G) {
-		gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
+		gd->dram[0].size = ram_top - gd->dram[0].start;
 	}
 #else
 #ifdef CONFIG_SPL_OPTEE_IMAGE
@@ -327,23 +327,23 @@ int dram_init_banksize(void)
 			TRUST_PARAMETER_OFFSET);
 
 	if (tos_parameter->tee_mem.flags == 1) {
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = tos_parameter->tee_mem.phy_addr
 					- CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+		gd->dram[1].start = tos_parameter->tee_mem.phy_addr +
 					tos_parameter->tee_mem.size;
-		gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
+		gd->dram[1].size = top - gd->dram[1].start;
 	} else {
-		gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-		gd->bd->bi_dram[0].size = 0x8400000;
+		gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+		gd->dram[0].size = 0x8400000;
 		/* Reserve 32M for OPTEE with TA */
-		gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
-					+ gd->bd->bi_dram[0].size + 0x2000000;
-		gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
+		gd->dram[1].start = CFG_SYS_SDRAM_BASE
+					+ gd->dram[0].size + 0x2000000;
+		gd->dram[1].size = top - gd->dram[1].start;
 	}
 #else
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = top - gd->dram[0].start;
 #endif
 #endif
 
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 829a0109ac7..35735f1551c 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2)
 }
 
 /* This has to be done post-relocation since gd->bd isn't preserved */
-static void qcom_configure_bi_dram(void)
+static void qcom_configure_dram(void)
 {
 	int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;
-		gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;
+		gd->dram[i].start = prevbl_ddr_banks[i].start;
+		gd->dram[i].size = prevbl_ddr_banks[i].size;
 	}
 }
 
 int dram_init_banksize(void)
 {
-	qcom_configure_bi_dram();
+	qcom_configure_dram();
 
 	return 0;
 }
@@ -594,15 +594,15 @@ static void build_mem_map(void)
 	 */
 	mem_map[0].phys = 0x1000;
 	mem_map[0].virt = mem_map[0].phys;
-	mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
+	mem_map[0].size = gd->dram[0].start - mem_map[0].phys;
 	mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 
-	for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {
-		mem_map[i].phys = gd->bd->bi_dram[j].start;
+	for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) {
+		mem_map[i].phys = gd->dram[j].start;
 		mem_map[i].virt = mem_map[i].phys;
-		mem_map[i].size = gd->bd->bi_dram[j].size;
+		mem_map[i].size = gd->dram[j].size;
 		mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
 				   PTE_BLOCK_INNER_SHARE;
 	}
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 4d7f0b9a79c..b202ca258bc 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images)
 void lmb_arch_add_memory(void)
 {
 	int i;
-	struct bd_info *bd = gd->bd;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		if (bd->bi_dram[i].size)
-			lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size);
+		if (gd->dram[i].size)
+			lmb_add(gd->dram[i].start, gd->dram[i].size);
 	}
 }
 #endif
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 7e0f3875b7c..338f73d6e73 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,7 +246,6 @@ int qspi_flash_software_reset(void)
 
 void dram_bank_mmu_setup(int bank)
 {
-	struct bd_info *bd = gd->bd;
 	u32 start, size;
 	int i;
 
@@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank)
 	 * The default implementation of this function allows the DRAM dcache
 	 * to be enabled only after relocation. However, to speed up ECC
 	 * initialization, we want to be able to enable DRAM dcache before
-	 * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+	 * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram
 	 * is set first).
 	 */
-	start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
-	size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+	start = gd->dram[bank].start >> MMU_SECTION_SHIFT;
+	size = gd->dram[bank].size >> MMU_SECTION_SHIFT;
 	for (i = start; i < start + size; i++)
 		set_section_dcache(i, DCACHE_DEFAULT_OPTION);
 }
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index 835eaf48dfa..76c324b55ae 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data,
 		dev->mtd = mtd;
 		break;
 	case STM32PROG_RAM:
-		first_addr = gd->bd->bi_dram[0].start;
-		last_addr = first_addr + gd->bd->bi_dram[0].size;
+		first_addr = gd->dram[0].start;
+		last_addr = first_addr + gd->dram[0].size;
 		dev->erase_size = 1;
 		break;
 	default:
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 252aef1852e..4d81c70b230 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -52,7 +52,6 @@ u32 get_bootauth(void)
  */
 void dram_bank_mmu_setup(int bank)
 {
-	struct bd_info *bd = gd->bd;
 	int	i;
 	phys_addr_t start;
 	phys_addr_t addr;
@@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank)
 		size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
 #endif
 	} else if (gd->flags & GD_FLG_RELOC) {
-		/* bd->bi_dram is available only after relocation */
-		start = bd->bi_dram[bank].start;
-		size =  bd->bi_dram[bank].size;
+		/* gd->dram is available only after relocation */
+		start = gd->dram[bank].start;
+		size =  gd->dram[bank].size;
 		use_lmb = true;
 	} else {
 		/* mark cacheable and executable the beggining of the DDR */
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 396851c5bd8..1763f95ace4 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -393,18 +393,18 @@ int dram_init_banksize(void)
 
 	/* fall back to default DRAM bank size computation */
 
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = usable_ram_size_below_4g();
 
 #ifdef CONFIG_PHYS_64BIT
 	if (gd->ram_size > SZ_2G) {
-		gd->bd->bi_dram[1].start = 0x100000000;
-		gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+		gd->dram[1].start = 0x100000000;
+		gd->dram[1].size = gd->ram_size - SZ_2G;
 	} else
 #endif
 	{
-		gd->bd->bi_dram[1].start = 0;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[1].start = 0;
+		gd->dram[1].size = 0;
 	}
 
 	return 0;
@@ -418,7 +418,7 @@ int dram_init_banksize(void)
  * carve-out, as mentioned above.
  *
  * This function is called before dram_init_banksize(), so we can't simply
- * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
+ * return gd->dram[1].start + gd->dram[1].size.
  */
 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c
index e2342b2aece..ff15fa28eb5 100644
--- a/arch/arm/mach-tegra/cboot.c
+++ b/arch/arm/mach-tegra/cboot.c
@@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void)
 	}
 
 	for (i = 0; i < ram_bank_count; i++) {
-		gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
-		gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
+		gd->dram[i].start = tegra_mem_map[1 + i].virt;
+		gd->dram[i].size = tegra_mem_map[1 + i].size;
 	}
 
 	return 0;
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index 0e1164a2680..ae495808dec 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -280,9 +280,9 @@ int dram_init_banksize(void)
 		return ret;
 
 	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
-		if (i < ARRAY_SIZE(gd->bd->bi_dram)) {
-			gd->bd->bi_dram[i].start = dram_map[i].base;
-			gd->bd->bi_dram[i].size = dram_map[i].size;
+		if (i < ARRAY_SIZE(gd->dram)) {
+			gd->dram[i].start = dram_map[i].base;
+			gd->dram[i].size = dram_map[i].size;
 		}
 
 		if (!dram_map[i].size)
diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c
index dfa32fdd48b..4e1de15cd98 100644
--- a/arch/arm/mach-uniphier/fdt-fixup.c
+++ b/arch/arm/mach-uniphier/fdt-fixup.c
@@ -4,6 +4,7 @@
  *   Author: Masahiro Yamada <[email protected]>
  */
 
+#include <asm/global_data.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
 #include <jffs2/load_kernel.h>
@@ -20,6 +21,7 @@
  */
 static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	unsigned long rsv_addr;
 	const unsigned long rsv_size = 64;
 	int i, ret;
@@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)
 	    uniphier_get_soc_id() != UNIPHIER_LD20_ID)
 		return 0;
 
-	for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) {
-		if (!bd->bi_dram[i].size)
+	for (i = 0; i < ARRAY_SIZE(gd->dram); i++) {
+		if (!gd->dram[i].size)
 			continue;
 
-		rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size;
+		rsv_addr = gd->dram[i].start + gd->dram[i].size;
 		rsv_addr -= rsv_size;
 
 		ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c
index d088e440f63..78ead1f45f6 100644
--- a/arch/arm/mach-versal-net/cpu.c
+++ b/arch/arm/mach-versal-net/cpu.c
@@ -69,12 +69,12 @@ void mem_map_fill(void)
 
 	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		/* Zero size means no more DDR that's this is end */
-		if (!gd->bd->bi_dram[i].size)
+		if (!gd->dram[i].size)
 			break;
 
-		versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
-		versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
-		versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		versal_mem_map[banks].virt = gd->dram[i].start;
+		versal_mem_map[banks].phys = gd->dram[i].start;
+		versal_mem_map[banks].size = gd->dram[i].size;
 		versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 					      PTE_BLOCK_INNER_SHARE;
 		banks = banks + 1;
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 363ce3007fd..0dd5cc153c4 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -82,21 +82,21 @@ void mem_map_fill(void)
 
 	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		/* Zero size means no more DDR that's this is end */
-		if (!gd->bd->bi_dram[i].size)
+		if (!gd->dram[i].size)
 			break;
 
 #if defined(CONFIG_VERSAL_NO_DDR)
-		if (gd->bd->bi_dram[i].start < 0x80000000UL ||
-		    gd->bd->bi_dram[i].start > 0x100000000UL) {
+		if (gd->dram[i].start < 0x80000000UL ||
+		    gd->dram[i].start > 0x100000000UL) {
 			printf("Ignore caches over %llx/%llx\n",
-			       gd->bd->bi_dram[i].start,
-			       gd->bd->bi_dram[i].size);
+			       gd->dram[i].start,
+			       gd->dram[i].size);
 			continue;
 		}
 #endif
-		versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
-		versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
-		versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		versal_mem_map[banks].virt = gd->dram[i].start;
+		versal_mem_map[banks].phys = gd->dram[i].start;
+		versal_mem_map[banks].size = gd->dram[i].size;
 		versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 					      PTE_BLOCK_INNER_SHARE;
 		banks = banks + 1;
diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c
index a81609cdec7..f65c231bdab 100644
--- a/arch/arm/mach-versal2/cpu.c
+++ b/arch/arm/mach-versal2/cpu.c
@@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks)
  * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info
  *
  * Transfers DRAM bank information from the global versal2_mem_map[]
- * array to bd->bi_dram[] for passing memory configuration to the
+ * array to gd->dram[] for passing memory configuration to the
  * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical
  * address and size are copied.
  *
@@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks)
  */
 void fill_bd_mem_info(void)
 {
-	struct bd_info *bd = gd->bd;
 	int banks = VERSAL2_MEM_MAP_USED;
 
 	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		if (!versal2_mem_map[banks].size)
 			break;
 
-		bd->bi_dram[i].start = versal2_mem_map[banks].phys;
-		bd->bi_dram[i].size = versal2_mem_map[banks].size;
+		gd->dram[i].start = versal2_mem_map[banks].phys;
+		gd->dram[i].size = versal2_mem_map[banks].size;
 		banks++;
 	}
 }
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 5f194aaff9a..3dc47e5d48e 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -92,12 +92,12 @@ void mem_map_fill(void)
 #if !defined(CONFIG_ZYNQMP_NO_DDR)
 	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		/* Zero size means no more DDR that's this is end */
-		if (!gd->bd->bi_dram[i].size)
+		if (!gd->dram[i].size)
 			break;
 
-		zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
-		zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
-		zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		zynqmp_mem_map[banks].virt = gd->dram[i].start;
+		zynqmp_mem_map[banks].phys = gd->dram[i].start;
+		zynqmp_mem_map[banks].size = gd->dram[i].size;
 		zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 					      PTE_BLOCK_INNER_SHARE;
 		banks = banks + 1;
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 5b1311d8b5b..817728aa569 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c
@@ -41,8 +41,8 @@ int dram_init(void)
 		 * No DDR init yet -> run in L2 cache
 		 */
 		gd->ram_size = (4 << 20);
-		gd->bd->bi_dram[0].size = gd->ram_size;
-		gd->bd->bi_dram[1].size = 0;
+		gd->dram[0].size = gd->ram_size;
+		gd->dram[1].size = 0;
 	}
 
 	return 0;
diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c
index cc1e903c9dd..2893bc6b99a 100644
--- a/arch/riscv/cpu/k1/dram.c
+++ b/arch/riscv/cpu/k1/dram.c
@@ -56,12 +56,12 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);
+	gd->dram[0].start = CFG_SYS_SDRAM_BASE;
+	gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);
 
 	if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) {
-		gd->bd->bi_dram[1].start = 0x100000000;
-		gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
+		gd->dram[1].start = 0x100000000;
+		gd->dram[1].size = gd->ram_size - SZ_2G;
 	}
 
 	return 0;
@@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		start[i] = gd->bd->bi_dram[i].start;
-		size[i] = gd->bd->bi_dram[i].size;
+		start[i] = gd->dram[i].start;
+		size[i] = gd->dram[i].size;
 	}
 
 	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 1668b58d3fb..460013f933b 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image);
 int dram_init_banksize(void)
 {
 	/* These are necessary so TFTP can use LMBs to check its load address */
-	gd->bd->bi_dram[0].start = gd->ram_base;
-	gd->bd->bi_dram[0].size = get_effective_memsize();
+	gd->dram[0].start = gd->ram_base;
+	gd->dram[0].size = get_effective_memsize();
 
 	return 0;
 }
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index cc1edd7badd..81604ee12fb 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -91,8 +91,8 @@ int dram_init_banksize(void)
 			struct memrange *memrange = &lib_sysinfo.memrange[i];
 
 			if (memrange->type == CB_MEM_RAM) {
-				gd->bd->bi_dram[j].start = memrange->base;
-				gd->bd->bi_dram[j].size = memrange->size;
+				gd->dram[j].start = memrange->base;
+				gd->dram[j].size = memrange->size;
 				j++;
 				if (j >= CONFIG_NR_DRAM_BANKS)
 					break;
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index 6845ce72ff9..b86d50b2cab 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -123,8 +123,8 @@ int dram_init_banksize(void)
 		if (desc->type != EFI_CONVENTIONAL_MEMORY ||
 		    (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20)
 			continue;
-		gd->bd->bi_dram[num_banks].start = desc->physical_start;
-		gd->bd->bi_dram[num_banks].size = desc->num_pages <<
+		gd->dram[num_banks].start = desc->physical_start;
+		gd->dram[num_banks].size = desc->num_pages <<
 			EFI_PAGE_SHIFT;
 		num_banks++;
 	}
diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c
index 6fe40071140..e09fce8bb1b 100644
--- a/arch/x86/cpu/efi/sdram.c
+++ b/arch/x86/cpu/efi/sdram.c
@@ -24,8 +24,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = efi_get_ram_base();
-	gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
+	gd->dram[0].start = efi_get_ram_base();
+	gd->dram[0].size = CONFIG_EFI_RAM_SIZE;
 
 	return 0;
 }
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index baa1f0e32d6..11ce97b5143 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void)
 
 		if (area->start >= 1ULL << 32)
 			continue;
-		gd->bd->bi_dram[num_banks].start = area->start;
-		gd->bd->bi_dram[num_banks].size = area->size;
+		gd->dram[num_banks].start = area->start;
+		gd->dram[num_banks].size = area->size;
 		num_banks++;
 	}
 }
diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c
index d20c9a2a379..a5e81dfada5 100644
--- a/arch/x86/cpu/ivybridge/sdram_nop.c
+++ b/arch/x86/cpu/ivybridge/sdram_nop.c
@@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int dram_init(void)
 {
 	gd->ram_size = 1ULL << 31;
-	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = 0;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index ba3638e6acc..3cba04f2c3e 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -69,13 +69,13 @@ int dram_init_banksize(void)
 {
 	u64 high_mem_size;
 
-	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = qemu_get_low_memory_size();
+	gd->dram[0].start = 0;
+	gd->dram[0].size = qemu_get_low_memory_size();
 
 	high_mem_size = qemu_get_high_memory_size();
 	if (high_mem_size) {
-		gd->bd->bi_dram[1].start = SZ_4G;
-		gd->bd->bi_dram[1].size = high_mem_size;
+		gd->dram[1].start = SZ_4G;
+		gd->dram[1].size = high_mem_size;
 	}
 
 	return 0;
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 34e576940d4..34fdb7e026a 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -169,8 +169,8 @@ int dram_init(void)
 
 int dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = 0;
+	gd->dram[0].size = gd->ram_size;
 
 	return 0;
 }
diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c
index 75ca5273625..5aa4f6d3e07 100644
--- a/arch/x86/cpu/slimbootloader/sdram.c
+++ b/arch/x86/cpu/slimbootloader/sdram.c
@@ -129,8 +129,8 @@ int dram_init_banksize(void)
 		return 0;
 
 	/* simply use a single bank to have whole size for now */
-	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->dram[0].start = 0;
+	gd->dram[0].size = gd->ram_size;
 	return 0;
 }
 
diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c
index 6192f2296b8..6ce96b0569b 100644
--- a/arch/x86/cpu/tangier/sdram.c
+++ b/arch/x86/cpu/tangier/sdram.c
@@ -160,8 +160,8 @@ static int sfi_get_bank_size(void)
 		if (mentry->type != SFI_MEM_CONV)
 			continue;
 
-		gd->bd->bi_dram[bank].start = mentry->phys_start;
-		gd->bd->bi_dram[bank].size = mentry->pages << 12;
+		gd->dram[bank].start = mentry->phys_start;
+		gd->dram[bank].size = mentry->pages << 12;
 		bank++;
 	}
 
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index cde4fbf3557..e054f42fa86 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void)
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
 int arch_fixup_memory_node(void *blob)
 {
-	struct bd_info	*bd = gd->bd;
 	int bank;
 	u64 start[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start[bank] = bd->bi_dram[bank].start;
-		size[bank] = bd->bi_dram[bank].size;
+		start[bank] = gd->dram[bank].start;
+		size[bank] = gd->dram[bank].size;
 	}
 
 	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 730721dc176..a45e4060ef2 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -64,8 +64,8 @@ int dram_init_banksize(void)
 	update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
 
 	if (!ll_boot_init()) {
-		gd->bd->bi_dram[0].start = 0;
-		gd->bd->bi_dram[0].size = gd->ram_size;
+		gd->dram[0].start = 0;
+		gd->dram[0].size = gd->ram_size;
 
 		if (update_mtrr)
 			mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
@@ -89,21 +89,21 @@ int dram_init_banksize(void)
 			mtrr_top = max(mtrr_top,
 				       res_desc->phys_start + res_desc->len);
 		} else {
-			gd->bd->bi_dram[bank].start = res_desc->phys_start;
-			gd->bd->bi_dram[bank].size = res_desc->len;
+			gd->dram[bank].start = res_desc->phys_start;
+			gd->dram[bank].size = res_desc->len;
 			if (update_mtrr)
 				mtrr_add_request(MTRR_TYPE_WRBACK,
 						 res_desc->phys_start,
 						 res_desc->len);
 			log_debug("ram %llx %llx\n",
-				  gd->bd->bi_dram[bank].start,
-				  gd->bd->bi_dram[bank].size);
+				  gd->dram[bank].start,
+				  gd->dram[bank].size);
 		}
 	}
 
 	/* Add the memory below 4GB */
-	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = low_end;
+	gd->dram[0].start = 0;
+	gd->dram[0].size = low_end;
 
 	/*
 	 * Set up an MTRR to the top of low, reserved memory. This is necessary
@@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries,
 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
 int handoff_arch_save(struct spl_handoff *ho)
 {
-	ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
+	ho->arch.usable_ram_top = gd->dram[0].size;
 	ho->arch.hob_list = gd->arch.hob_list;
 
 	return 0;