diff options
| author | Teresa Remmet <[email protected]> | 2021-07-07 12:57:59 +0000 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2021-07-10 16:53:34 +0200 |
| commit | 1feac813fe54ff6466ea2d575960bc1de45b0e5c (patch) | |
| tree | 803a4cf75291dc22fd93afbdbbbf2460ae401a05 /arch | |
| parent | 3240d9c63a67880e55e33268d0796f71f65a1acd (diff) | |
board: phytec: phycore_imx8mp: Change debug UART
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 6c1528934a9..32ed037e372 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -18,7 +18,7 @@ u-boot,dm-spl; }; -&pinctrl_uart2 { +&pinctrl_uart1 { u-boot,dm-spl; }; @@ -54,7 +54,7 @@ u-boot,dm-spl; }; -&uart2 { +&uart1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts index 2031a9d40be..984a6b9ded8 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts @@ -16,7 +16,7 @@ "phytec,imx8mp-phycore-som", "fsl,imx8mp"; chosen { - stdout-path = &uart2; + stdout-path = &uart1; }; reg_usdhc2_vmmc: regulator-usdhc2 { @@ -95,9 +95,9 @@ }; /* debug console */ -&uart2 { +&uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; @@ -154,10 +154,10 @@ >; }; - pinctrl_uart2: uart2grp { + pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 >; }; |