Merge tag 'xilinx-for-v2026.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

AMD/Xilinx/FPGA changes for v2026.04-rc1

xilinx:
- Sync ESRT with detected GUID
- DT cleanups
- Add logic for FRU information multiple times
- Enable more drivers pca9541, usb5744
- Enable more commands
- Cleanup firmware DT bindings

firmware:
- Add enhancement SMC format support

clk/versal:
- Various cleanups
- Add support for Versal Gen 2

i2c:
- cdns: Add timeout for RXDV status bit polling

spi:
- cadence: Remove cdns,is-dma DT property
- cadence: Remove duplicated return
- cadence_versal: Update flash reset delay

memtop:
- Update max memory reserved spaces to 64

Versal Gen 2:
- Aligned addresses with default memory map
- Add support for reading multiboot value

MB-V:
- Make SPL smaller
- Add support for SPI
- Move SPL to run out of BRAM

ZynqMP:
- Change default load address for BL32

5 files changed, 6 insertions, 9 deletions

diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index eec2a08e7c7..8429dc585d5 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -29,7 +29,7 @@
 	};
 
 	ospi: spi@f1010000 {
-		compatible = "cdns,qspi-nor";
+		compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor";
 		status = "okay";
 		reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
 		clock-names = "ref_clk", "pclk";
@@ -38,7 +38,6 @@
 		num-cs = <1>;
 		cdns,fifo-depth = <256>;
 		cdns,fifo-width = <4>;
-		cdns,is-dma = <1>;
 		cdns,trigger-address = <0xc0000000>;
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi
index 1c94b352dc9..78404960f2f 100644
--- a/arch/arm/dts/versal-net-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-net-mini-ospi.dtsi
@@ -43,7 +43,7 @@
 	};
 
 	ospi: spi@f1010000 {
-		compatible = "cdns,qspi-nor";
+		compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor";
 		status = "okay";
 		reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
 		clock-names = "ref_clk", "pclk";
@@ -52,7 +52,6 @@
 		num-cs = <1>;
 		cdns,fifo-depth = <256>;
 		cdns,fifo-width = <4>;
-		cdns,is-dma = <1>;
 		cdns,is-stig-pgm = <1>;
 		cdns,trigger-address = <0xc0000000>;
 		#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
index c1945ea6f8d..5a4e5f09250 100644
--- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
@@ -13,9 +13,6 @@
 /plugin/;
 
 &{/} {
-	#address-cells = <2>;
-	#size-cells = <2>;
-
 	compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA",
 		     "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp";
 
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
index 7ca2bbb7550..81a0df89357 100644
--- a/arch/arm/mach-versal2/include/mach/hardware.h
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2016 - 2022, Xilinx, Inc.
- * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
  */
 
 #ifndef __ASSEMBLY__
@@ -73,6 +73,8 @@ struct crp_regs {
 #define JTAG_MODE	0x00000000
 #define BOOT_MODE_USE_ALT	0x100
 #define BOOT_MODE_ALT_SHIFT	12
+#define PMC_MULTI_BOOT_REG	0xF1110004
+#define PMC_MULTI_BOOT_MASK	0x1FFF
 
 enum versal2_platform {
 	VERSAL2_SILICON = 0,
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 151cfada436..8a4356bc060 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -138,7 +138,7 @@ config BL31_LOAD_ADDR
 
 config BL32_LOAD_ADDR
 	hex "Load address of BL32 image (mostly secure OS)"
-	default 0
+	default 0x60000000
 	help
 	  The load address for the BL32 image. This value is used to build the
 	  FIT image header that places BL32 in memory where it will run.