diff options
| author | Pali Rohár <[email protected]> | 2021-07-31 14:22:53 +0200 |
|---|---|---|
| committer | Stefan Roese <[email protected]> | 2021-08-11 08:42:26 +0200 |
| commit | 2ddf554b8648d892efc5733e7486cec5e93dc269 (patch) | |
| tree | 657272fc09b52c05a4fa88d1d569690adee12eaf /arch | |
| parent | 29795302b942e6ee41c9d95f7e6e29f57d108d42 (diff) | |
arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index cb323aa59a7..eb6906ad802 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -145,6 +145,9 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ + 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) |