diff options
| author | David Wu <[email protected]> | 2017-09-20 14:28:18 +0800 |
|---|---|---|
| committer | Philipp Tomsich <[email protected]> | 2017-10-01 00:33:29 +0200 |
| commit | 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38 (patch) | |
| tree | 1aca6576b715876b47853f4aab24c0f353464676 /arch | |
| parent | ae3ed042ed31d1acbdd56938b45bd6c5076bebe3 (diff) | |
rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <[email protected]>
Acked-by: Philipp Tomsich <[email protected]>
Reviewed-by: Philipp Tomsich <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 2a1ae692bef..ad2dc964675 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -90,6 +90,11 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON22 */ + CLK_SARADC_DIV_CON_SHIFT= 0, + CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), + CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, |