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authorTom Rini <[email protected]>2022-06-12 20:02:04 -0400
committerTom Rini <[email protected]>2022-06-28 17:11:48 -0400
commit3371eddaa10212b1303b2de305e1d976fe7770ca (patch)
tree1328087906bd0b877adb77a563c750544149855d /arch
parent525fbfabf1f91bde3bd8fc8aa3ec8504e77c074f (diff)
Convert CONFIG_USB_MAX_CONTROLLER_COUNT to Kconfig
This converts the following to Kconfig: CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Tom Rini <[email protected]>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h1
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fdt.c4
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h24
3 files changed, 0 insertions, 29 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 2f3409e3e87..aa790ab54c3 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -95,7 +95,6 @@
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 67f8b100018..871554a7f48 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -17,10 +17,6 @@
#include <phy.h>
#include <hwconfig.h>
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
{
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 47bfcc72444..06f66d02de2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -31,7 +31,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -41,25 +40,19 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_TSECV2
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_TSECV2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
@@ -68,11 +61,9 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_TSECV2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@@ -84,7 +75,6 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -92,9 +82,6 @@
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#endif
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@@ -118,7 +105,6 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -132,7 +118,6 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
@@ -151,7 +136,6 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
@@ -163,7 +147,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
@@ -172,7 +155,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
@@ -204,7 +186,6 @@
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
@@ -234,7 +215,6 @@
#define CONFIG_SYS_CPRI
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_CPRI_CLK 3
#define CONFIG_SYS_ULB_CLK 4
@@ -255,7 +235,6 @@
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -278,7 +257,6 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
@@ -309,7 +287,6 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
@@ -343,7 +320,6 @@
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0