diff options
| author | Jakob Unterwurzacher <[email protected]> | 2026-06-25 13:55:15 +0200 |
|---|---|---|
| committer | Quentin Schulz <[email protected]> | 2026-07-10 10:45:05 +0200 |
| commit | 6037673a10f1ec24cd8e9fe03785d1e7e19e6854 (patch) | |
| tree | 907af70a0e1b279a2bb2a0e5b9c0c89eb8982392 /arch | |
| parent | 07ab38e11f56b687ef40fa8c62de5556ae645a26 (diff) | |
board: rockchip: set M.2 NVMe PERSTN low in spl_board_init on Jaguar
As it is, an NVMe's built-in PERSTN pull-up fights against the
SoC's built-in pull-down which results in an undefined logic state
on the Samsung SSD 980 and likely others.
Fix that by forcing PERSTN low as early as possible, which is SPL.
Both Linux and U-Boot (via "pci enum") set the pin high later
as needed and the NVMe is detected fine.
Oscillocope shots ("x" means undefined logic state at around 1.5V):
Before:
3V3 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
PERSTN ____xxxxxxxxxxxxxxx_|‾‾‾‾‾
PCICLK ____∿∿∿∿∿∿∿∿∿∿∿∿___∿∿∿∿∿∿∿
^U-Boot ^ Linux
After:
3V3 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
PERSTN ____x_______________|‾‾‾‾‾
PCICLK ____∿∿∿∿∿∿∿∿∿∿∿∿___∿∿∿∿∿∿∿
^U-Boot ^ Linux
With this change, the power-up sequence conforms to PCIe specs,
except a remaining short PERSTN glitch. The glitch is about 400ms
long. It could be shortened by moving the logic to TPL, but
completely fixing it is only possible in hardware.
Signed-off-by: Jakob Unterwurzacher <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://patch.msgid.link/20260625-pub-jaguar-puma-ringneck-tiger-v2025-07_nvme-v2-1-c57bf1020d63@cherry.de
Signed-off-by: Quentin Schulz <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/rk3588-jaguar-u-boot.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi index dcda4f99d6e..0fbbb50fc5a 100644 --- a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi +++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi @@ -21,6 +21,12 @@ bootph-some-ram; }; +&gpio0 { + /* Need gpio0 in SPL for spl_board_init() to control GPIO0_D0 */ + /* TODO: once we have a U-Boot TPL, use bootph-pre-sram; */ + bootph-pre-ram; +}; + &gpio2 { bootph-pre-ram; bootph-some-ram; |
