Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell

CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=379&view=results

- mvebu: Disable JFFS2 support for Kirkwood and Armada XP boards (Tony)
- kirkwood: Enable bootstd for Sheevaplug board (Tony)
- mvebu: Add Allied Telesis x250 board (Chris)
- mvebu: Updates for Allied Telesis boards (Chris)

3 files changed, 286 insertions, 1 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 042282f3723..6ad59aeed5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -190,7 +190,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9130-crb-A.dtb			\
 	cn9130-crb-B.dtb			\
 	ac5-98dx35xx-rd.dtb			\
-	ac5-98dx35xx-atl-x240.dtb
+	ac5-98dx35xx-atl-x240.dtb		\
+	cn9130-atl-x250.dtb
 endif
 
 dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
diff --git a/arch/arm/dts/cn9130-atl-x250.dts b/arch/arm/dts/cn9130-atl-x250.dts
new file mode 100644
index 00000000000..f2c82da9d14
--- /dev/null
+++ b/arch/arm/dts/cn9130-atl-x250.dts
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Allied Telesis Labs
+ */
+
+#include "cn9130.dtsi"
+
+/ {
+	model = "Allied Telesis x250";
+	compatible = "alliedtelesis,x250",
+		"marvell,cn9130",
+		"marvell,armada-ap806-quad",
+		"marvell,armada-ap806";
+
+	aliases {
+		serial0 = &uart0;
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		fault {
+			label = "fault:red";
+			gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+	/* AP_MPP Pins:
+	 * GPIO & NC [0-6,9-10,12]
+	 * UART0 [11,19]
+	 * UART1 [7,8]
+	 * Note: The x250-28XTm PT1 units has the console port wired
+	 *       to the second uart pins (UART1). This was fixed in all
+	 *       subsequent models.
+	 *       Here we choose to configure the pin control for both
+	 *       uarts to cater for either unit.
+	 */
+		/*   0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 0 0 0 0 0 0 0 3 3 0
+		     0 3 0 0 0 0 0 0 0 3 >;
+};
+
+&ap_gpio0 {
+	pp-reset {
+		gpio-hog;
+		gpios = <0 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "pp-reset";
+	};
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+	/* MPP Bus:
+	 *	[0-1]	DEV
+	 *	[2-8]	GPIO
+	 *	[9]	DEV
+	 *	[10-12]	GPIO
+	 *	[13]	ND_RB
+	 *	[14]	GPIO
+	 *	[15-28]	DEV
+	 *	[29-30]	GPIO
+	 *	[31]	DEV
+	 *	[32-34]	GPIO
+	 *	[35-36]	I2C1
+	 *	[37-38]	I2C0
+	 *	[39-55]	GPIO
+	 *	[56-60]	SPI
+	 *	[61-62]	GPIO
+	 */
+		/*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = < 1   1   0   0   0   0   0   0   0   1
+		     0   0   0   2   0   1   1   1   1   1
+		     1   1   1   1   1   1   1   1   1   0
+		     0   1   0   0   0   2   2   2   2   0
+		     0   0   0   0   0   0   0   0   0   0
+		     0   0   0   0   0   0   6   6   6   6
+		     6   0   0>;
+
+	cp0_i2c0_pins: cp0-i2c-pins-0 {
+		marvell,pins = <37 38>;
+		marvell,function = <2>;
+	};
+
+	cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 {
+		marvell,pins = <37 38>;
+		marvell,function = <0>;
+	};
+
+	cp0_i2c1_pins: cp0-i2c-pins-1 {
+		marvell,pins = <35 36>;
+		marvell,function = <2>;
+	};
+
+	cp0_nand_pins: cp0-nand-pins {
+		marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>;
+		marvell,function = <1>;
+	};
+
+	cp0_nand_rb: cp0-nand-rb {
+		marvell,pins = <13>;
+		marvell,function = <2>;
+	};
+
+	cp0_spi0_pins: cp0-spi-pins-0 {
+		marvell,pins = <56 57 58 59 60>;
+		marvell,function = <6>;
+	};
+};
+
+&cp0_comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_IGNORE>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_IGNORE>;
+	};
+
+	phy3 {
+		phy-type = <COMPHY_TYPE_IGNORE>;
+	};
+
+	phy4 {
+		phy-type = <COMPHY_TYPE_IGNORE>;
+	};
+
+	phy5 {
+		phy-type = <COMPHY_TYPE_IGNORE>;
+	};
+};
+
+&cp0_pcie0 {
+	num-lanes = <1>;
+		/* non-prefetchable memory */
+	ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	clock-frequency = <200000000>;
+};
+
+&cp0_utmi0 {
+	status = "okay";
+};
+
+&cp0_usb3_0 {
+	status = "okay";
+};
+
+&cp0_spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi0_pins>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+	};
+};
+
+&cp0_nand {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+	nand-timing-mode = <4>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@user {
+			reg = <0x00000000 0x10000000>;
+			label = "user";
+		};
+	};
+};
+
+&cp0_gpio0
+{
+	nand-protect {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "nand-protect";
+	};
+};
+
+&cp0_gpio1
+{
+	usb-en {
+		gpio-hog;
+		gpios = <0 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "usb-en";
+	};
+
+	phy-reset {
+		gpio-hog;
+		gpios = <21 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "phy-reset";
+	};
+};
+
+&cp0_i2c0 {
+	status = "okay";
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	pinctrl-1 = <&cp0_i2c0_gpio_pins>;
+	scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+	mux@71 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,pca9546";
+		reg = <0x71>;
+		i2c-mux-idle-disconnect;
+		reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			hwmon@2e {
+				compatible = "adi,adt7476";
+				reg = <0x2e>;
+			};
+
+			rtc@68 {
+				compatible = "adi,max31331";
+				reg = <0x68>;
+			};
+		};
+	};
+};
+
+&cp0_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index c1a1a333e6c..adb816982f8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -215,9 +215,16 @@ config TARGET_X530
 	bool "Support Allied Telesis x530"
 	select 88F6820
 
+config TARGET_X250
+	bool "Support Allied Telesis x250"
+	select ARMADA_8K
+	imply SCSI
+	imply BOOTSTD_DEFAULTS
+
 config TARGET_X240
 	bool "Support Allied Telesis x240"
 	select ALLEYCAT_5
+	imply BOOTSTD_DEFAULTS
 
 config TARGET_DB_XC3_24G4XG
 	bool "Support DB-XC3-24G4XG"
@@ -301,6 +308,7 @@ config SYS_BOARD
 	default "theadorable" if TARGET_THEADORABLE
 	default "a38x" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "x250" if TARGET_X250
 	default "x240" if TARGET_X240
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@@ -325,6 +333,7 @@ config SYS_CONFIG_NAME
 	default "turris_mox" if TARGET_TURRIS_MOX
 	default "controlcenterdc" if TARGET_CONTROLCENTERDC
 	default "x530" if TARGET_X530
+	default "x250" if TARGET_X250
 	default "x240" if TARGET_X240
 	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
 	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@@ -349,6 +358,7 @@ config SYS_VENDOR
 	default "CZ.NIC" if TARGET_TURRIS_MOX
 	default "gdsys" if TARGET_CONTROLCENTERDC
 	default "alliedtelesis" if TARGET_X530
+	default "alliedtelesis" if TARGET_X250
 	default "alliedtelesis" if TARGET_X240
 	default "mikrotik" if TARGET_CRS3XX_98DX3236
 	default "Marvell" if TARGET_MVEBU_ALLEYCAT5