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authorChris Morgan <[email protected]>2024-09-19 09:00:19 -0500
committerKever Yang <[email protected]>2024-10-25 20:48:40 +0800
commit7344fa41a2e39a2f10ffcc5f3ea5725b56d0e285 (patch)
treedd69b5a999d0324cee87ccc455be11f7d190271f /arch
parent609e71e68e46a0183978352a330198e570a89a86 (diff)
board: rockchip: Convert Anbernic RGxx3 to OF_UPSTREAM
Refactor the board detection logic (again) to make it compatible with the upstream device-trees, and switch to OF_UPSTREAM. Now the device boots with the device-tree for the 353P, and then loads the correct device tree (of 10) in the later stages of SPL. Signed-off-by: Chris Morgan <[email protected]> Reviewed-by: Kever Yang <[email protected]>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi34
-rw-r--r--arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi52
-rw-r--r--arch/arm/dts/rk3566-anbernic-rgxx3.dts28
3 files changed, 34 insertions, 80 deletions
diff --git a/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi
new file mode 100644
index 00000000000..fa3fbe6c810
--- /dev/null
+++ b/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = &sdmmc0, &sdhci;
+ };
+
+ /*
+ * Adding fixed regulator to work around driver regulator
+ * requirements. Note that the correct regulator is on by
+ * default at boot and that saradc regulator gets corrected
+ * when proper device-tree is loaded.
+ */
+ vcc_1v8_dummy: vcc-1v8-dummy {
+ bootph-pre-ram;
+ bootph-some-ram;
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_dummy";
+ status = "okay";
+ };
+};
+
+&saradc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ vref-supply = <&vcc_1v8_dummy>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
deleted file mode 100644
index c7e849816a6..00000000000
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-#include "rk356x-u-boot.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = &sdmmc0, &sdhci;
- };
-};
-
-&dsi_dphy0 {
- status = "okay";
-};
-
-&dsi0 {
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-0 = <&i2c2m1_xfer>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pmucru {
- assigned-clocks = <&pmucru SCLK_32K_IOE>;
- assigned-clock-parents = <&pmucru CLK_RTC_32K>;
-};
-
-/*
- * We don't need the clocks, but if they are present they may cause
- * probing to fail so we remove them for U-Boot.
- */
-&rk817 {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ clocks;
- /delete-property/ clock-names;
-};
-
-&sdhci {
- pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
- <&emmc_datastrobe>, <&emmc_rstnout>;
- pinctrl-names = "default";
- bus-width = <8>;
- max-frequency = <200000000>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
deleted file mode 100644
index c393c8d07af..00000000000
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "rk3566-anbernic-rgxx3.dtsi"
-
-/ {
-
-/*
- * Note this is a pseudo-model that doesn't exist in mainline Linux.
- * This model is used for all RGXX3 devices and the board.c file will
- * set the correct dtb name for loading mainline Linux automatically.
- */
- model = "RGXX3";
- compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s",
- "anbernic,rg353m", "anbernic,rg353p",
- "anbernic,rg353ps", "anbernic,rg353v",
- "anbernic,rg353vs", "anbernic,rg503",
- "powkiddy,rgb10max3", "powkiddy,rgb30",
- "powkiddy,rk2023", "rockchip,rk3566";
-};
-
-&cru {
- assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
- <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
- assigned-clock-rates = <32768>, <1200000000>,
- <200000000>, <241500000>;
-};