board: phytec: phycore-imx91-93: Add phyCORE-i.MX91 support

As the PHYTEC phyCORE-i.MX91 [1] is just another variant of the existing
PHYTEC phyCORE-i.MX93 SoM but with i.MX91 SoC populated instead, add it
to the existing board-code "phycore_imx93", and rename that board to
"phycore_imx91_93" to reflect the dual SoCs support. While at it, also
rename and change common files accordingly. This way i.MX91 and i.MX93
SoC variants of the phyCORE SoM share most of the code and documentation
without duplication, while maintaining own device-tree and defconfigs
for each CPU variant.

Supported features:
 - 1GB LPDDR4 RAM
 - Debug UART
 - EEPROM
 - eMMC
 - Ethernet
 - SD-card
 - USB

Product page SoM:
[1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/

Signed-off-by: Primoz Fiser <[email protected]>

5 files changed, 258 insertions, 222 deletions

diff --git a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
new file mode 100644
index 00000000000..64ed7af9946
--- /dev/null
+++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <[email protected]>
+ *
+ */
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	aliases {
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc0", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0} {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_cd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_default {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pmic@25 {
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+		};
+	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&wdog3 {
+	bootph-all;
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
new file mode 100644
index 00000000000..5d788854de5
--- /dev/null
+++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <[email protected]>
+ *
+ */
+
+#include "imx91-u-boot.dtsi"
+#include "imx91-93-phyboard-segin-common-u-boot.dtsi"
+
+/ {
+	/*
+	 * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as
+	 * reference, but does only make use of its SoM (phyCORE) contained
+	 * periphery.
+	 */
+	model = "PHYTEC phyCORE-i.MX91";
+};
diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
index 646b617949d..b80ce20e942 100644
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "imx93-u-boot.dtsi"
+#include "imx91-93-phyboard-segin-common-u-boot.dtsi"
 
 / {
 	/*
@@ -17,224 +18,4 @@
 	 * periphery.
 	 */
 	model = "PHYTEC phyCORE-i.MX93";
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog3>;
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-
-	aliases {
-		ethernet0 = &fec;
-		ethernet1 = &eqos;
-	};
-
-	bootstd {
-		bootph-verify;
-		compatible = "u-boot,boot-std";
-
-		filename-prefixes = "/", "/boot/";
-		bootdev-order = "mmc0", "mmc1", "ethernet";
-
-		rauc {
-			compatible = "u-boot,distro-rauc";
-		};
-
-		script {
-			compatible = "u-boot,script";
-		};
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-};
-
-&{/soc@0} {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&aips1 {
-	bootph-pre-ram;
-	bootph-all;
-};
-
-&aips2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&aips3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&iomuxc {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&reg_usdhc2_vmmc {
-	u-boot,off-on-delay-us = <20000>;
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_cd {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_default {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpuart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-	fsl,signal-voltage-switch-extra-delay-ms = <8>;
-};
-
-&lpi2c1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-
-	pmic@25 {
-		bootph-pre-ram;
-		bootph-some-ram;
-
-		regulators {
-			bootph-pre-ram;
-			bootph-some-ram;
-		};
-	};
-
-	eeprom@50 {
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-};
-
-&s4muap {
-	bootph-pre-ram;
-	bootph-some-ram;
-	status = "okay";
-};
-
-&clk {
-	bootph-all;
-	bootph-pre-ram;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-rates;
-	/delete-property/ assigned-clock-parents;
-};
-
-&osc_32k {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&osc_24m {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&clk_ext1 {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&wdog3 {
-	bootph-all;
-	bootph-pre-ram;
 };
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 6e0958c0842..fef1980ccef 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -129,6 +129,14 @@ config TARGET_KONTRON_MX93
 	  Kontron Electronics BL i.MX93 using SoM module conformant to OSM
 	  standard 1.1 size S.
 
+config TARGET_PHYCORE_IMX91
+	bool "phycore_imx91"
+	select IMX91
+	select IMX9_LPDDR4X
+	imply OF_UPSTREAM
+	select OF_BOARD_FIXUP
+	select OF_BOARD_SETUP
+
 config TARGET_PHYCORE_IMX93
 	bool "phycore_imx93"
 	select IMX93
@@ -181,7 +189,7 @@ source "board/nxp/imx93_evk/Kconfig"
 source "board/nxp/imx93_frdm/Kconfig"
 source "board/nxp/imx93_qsb/Kconfig"
 source "board/kontron/osm-s-mx93/Kconfig"
-source "board/phytec/phycore_imx93/Kconfig"
+source "board/phytec/phycore_imx91_93/Kconfig"
 source "board/variscite/imx93_var_som/Kconfig"
 source "board/nxp/imx94_evk/Kconfig"
 source "board/nxp/imx95_evk/Kconfig"
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 583c3a5a464..44b3e0f5310 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob)
 	return 0;
 }
 
-#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \
+	!defined(CONFIG_TARGET_PHYCORE_IMX91)
 #ifndef CONFIG_XPL_BUILD
 int board_fix_fdt(void *fdt)
 {