diff options
| author | Christian Marangi <[email protected]> | 2024-08-02 15:53:11 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-08-19 16:13:13 -0600 |
| commit | 78487cd093f7ac96ec89f99e2eb5b11e815b7a92 (patch) | |
| tree | 91743f4529ba282e5e56d3f9bd229c86052c4334 /arch | |
| parent | 807624c1e1a177fc1f3191ffecf7d5ac190aa02e (diff) | |
clk: mediatek: mt7981: drop 1/1 spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7981.
Drop the factor entry from mt7981-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.
Signed-off-by: Christian Marangi <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/mt7981.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index 1be1b797b3e..fc13b90caf6 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -140,7 +140,7 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CK_INFRA_PWM>, + clocks = <&topckgen CK_TOP_PWM_SEL>, <&infracfg_ao CK_INFRA_PWM_BSEL>, <&infracfg_ao CK_INFRA_PWM1_CK>, <&infracfg_ao CK_INFRA_PWM2_CK>, @@ -174,7 +174,7 @@ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, <&infracfg_ao CK_INFRA_UART0_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + <&topckgen CK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; bootph-all; @@ -188,7 +188,7 @@ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, <&infracfg_ao CK_INFRA_UART1_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + <&topckgen CK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -201,7 +201,7 @@ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, <&infracfg_ao CK_INFRA_UART2_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + <&topckgen CK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -270,7 +270,7 @@ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, <&infracfg CK_INFRA_SPI0_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI0>; + <&topckgen CK_TOP_SPI_SEL>; clock-names = "spi-clk", "sel-clk"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -285,7 +285,7 @@ assigned-clocks = <&topckgen CK_TOP_SPIM_MST_SEL>, <&infracfg CK_INFRA_SPI1_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI1>; + <&topckgen CK_TOP_SPIM_MST_SEL>; clock-names = "spi-clk", "sel-clk"; status = "disabled"; }; @@ -298,7 +298,7 @@ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, <&infracfg CK_INFRA_SPI2_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI0>; + <&topckgen CK_TOP_SPI_SEL>; clock-names = "spi-clk", "sel-clk"; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; |