diff options
| author | Andre Przywara <[email protected]> | 2022-10-05 23:19:54 +0100 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2022-10-19 14:15:02 +0100 |
| commit | 843ed983a07ee5d8d4e4ac5baa39fc53f12b5f33 (patch) | |
| tree | 2380b564b3db29540e5fdf9373dcd1c47deba812 /arch | |
| parent | b87fb196688b055383e3a44c40d87afe5c395a09 (diff) | |
suniv: add UART1 support
Some boards with the Allwinner F1C100s family SoCs use UART1 for its
debug UART, so define the pins for the SPL and the pinmux name and mux
value for U-Boot proper.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-sunxi/board.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 60ccf909dbf..220ed80ba79 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); |