diff options
| author | Lukas Auer <[email protected]> | 2018-11-22 11:26:12 +0100 |
|---|---|---|
| committer | Andes <[email protected]> | 2018-11-26 13:57:29 +0800 |
| commit | 862e2e75e8f317ff8bd660550d7da3fede2ead09 (patch) | |
| tree | 1c7affaf8b45a246101e92d149e5abc1c85267c1 /arch | |
| parent | 17f2ffea36bf9d2ef7238cfd52b8872cbb50034a (diff) | |
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/Kconfig | 16 | ||||
| -rw-r--r-- | arch/riscv/lib/setjmp.S | 2 |
2 files changed, 9 insertions, 9 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 168ca3de7ce..7c76b4d664d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,20 +20,20 @@ source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" choice - prompt "CPU selection" - default CPU_RISCV_32 + prompt "Base ISA" + default ARCH_RV32I -config CPU_RISCV_32 - bool "RISC-V 32-bit" +config ARCH_RV32I + bool "RV32I" select 32BIT help - Choose this option to build an U-Boot for RISCV32 architecture. + Choose this option to target the RV32I base integer instruction set. -config CPU_RISCV_64 - bool "RISC-V 64-bit" +config ARCH_RV64I + bool "RV64I" select 64BIT help - Choose this option to build an U-Boot for RISCV64 architecture. + Choose this option to target the RV64I base integer instruction set. endchoice diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 8f5a6a23aad..72bc9241f6a 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -6,7 +6,7 @@ #include <config.h> #include <linux/linkage.h> -#ifdef CONFIG_CPU_RISCV_64 +#ifdef CONFIG_ARCH_RV64I #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) #else |