diff options
| author | Yu Chien Peter Lin <[email protected]> | 2023-09-29 12:03:07 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2023-10-04 18:23:54 +0800 |
| commit | 8a0d5f2f51b72b3cabacfe90ff196db3e1c4dc4d (patch) | |
| tree | e73f03e8612808bdf02f7a738ab73669ccc26141 /arch | |
| parent | 5f2529763772e26ed6c7f7ecbefe9482ad75fb99 (diff) | |
riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode
The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.
Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/cpu/andesv5/Kconfig | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index 82bb5a2a532..f311291aedb 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -4,8 +4,9 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLMT_TIMER + imply SPL_ANDES_PLMT_TIMER imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) imply V5L2_CACHE imply SPL_CPU imply SPL_OPENSBI |