Merge tag 'xilinx-for-v2026.10-rc1-v3' of https://git.u-boot-project.org/u-boot/custodians/u-boot-amd

AMD/Xilinx/FPGA changes for v2026.10-rc1 v3 AMD: - Firmware interface decoupling (part 1) ZynqMP: - DT updates - Add TCG variant detection Versal/Versal2: - Drop DDR MMU mapping and map it dynamically tools: - Add register initialization to mkimage MAINTAINERS: - Clean Zynq/ZynqMP fragments ufs: - Fix driver reregistration fpga: - altera: Simplify driver conditional compilation selection
author: Tom Rini <[email protected]> 2026-07-08 10:13:24 -0600
committer: Tom Rini <[email protected]> 2026-07-08 10:13:24 -0600
commit: 913fedc816570c07bfc7f9c4046dc2a3a55e4099 (patch)
tree: 203a77dffb82a220a95e088004ab0e553a995660 /arch
parent: ee5d46b45ec0c63f8f9dd1e816e0dac3452ccc3d (diff)
parent: 34c89c840c33dd154746ebdc9bbf2e4f3614d292 (diff)
57 files changed, 1604 insertions, 550 deletions
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 482f432ba7f..877962df2b3 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -3,7 +3,7 @@
  * Clock specification for Xilinx ZynqMP
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -49,6 +49,14 @@
 		clock-frequency = <27000000>;
 		clock-output-names = "aux_ref_clk";
 	};
+
+	rtc_clk: rtc-clk {
+		bootph-all;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "rtc_clk";
+	};
 };
 
 &zynqmp_firmware {
@@ -302,3 +310,8 @@
 			  <&zynqmp_clk DP_AUDIO_REF>,
 			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
 };
+
+&rtc {
+	clocks = <&rtc_clk>;
+	clock-names = "rtc";
+};
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index d48b6f3a8ec..83c39ce1a26 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -90,6 +90,9 @@
 	status = "okay";
 	phy-handle = <&phy0>;
 	phy-mode = "sgmii"; /* DTG generates this properly  1512 */
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "mac-address";
+
 	mdio: mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -119,10 +122,10 @@
 		  "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
 		  "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
 		  "", "", /* 78 - 79 */
-		  "", "", "", "", "", /* 80 - 84 */
-		  "", "", "", "", "", /* 85 - 89 */
-		  "", "", "", "", "", /* 90 - 94 */
-		  "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+		  "", "", "", "", "PMOD_0", /* 80 - 84 */
+		  "PMOD_1", "PMOD_2", "PMOD_3", "PMOD_4", "PMOD_5", /* 85 -89 */
+		  "PMOD_6", "PMOD_7", "", "", "", /* 90 - 94 */
+		  "", "", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
 		  "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
 		  "", "", "", "", "", /* 105 - 109 */
 		  "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
@@ -153,6 +156,12 @@
 	eeprom: eeprom@50 { /* u46 */
 		compatible = "atmel,24c32";
 		reg = <0x50>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		eth_mac: mac-address@20 {
+			reg = <0x20 0x6>;
+		};
 	};
 	/* u138 - TUSB320IRWBR - for USB-C */
 };
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index aebceb20736..824d189d246 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -51,83 +51,103 @@
 
 	ina226-vccint {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
 	};
 	ina226-vcc-soc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
 	};
 	ina226-vcc-pmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
 	};
 	ina226-vcc-ram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
 	};
 	ina226-vcc-pslp {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
 	};
 	ina226-vcc-psfp {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
 	};
 	ina226-vccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
 	};
 	ina226-vccaux-pmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
 	};
 	ina226-vcco-500 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
 	};
 	ina226-vcco-501 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
 	};
 	ina226-vcco-502 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
 	};
 	ina226-vcco-503 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
 	};
 	ina226-vcc-1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
 	};
 	ina226-vcc-3v3 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
 	};
 	ina226-vcc-1v2-ddr4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>,
 			      <&vcc_1v2_ddr4 3>;
 	};
 	ina226-vcc-1v1-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
 	};
 	ina226-vadj-fmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
 	};
 	ina226-mgtyavcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
 	};
 	ina226-mgtyavtt {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
 	};
 	ina226-mgtyvccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
 	};
 };
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index 7c9764c31f7..bf4ea35067c 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -40,26 +40,32 @@
 
 	ina226-u74 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 	};
 	ina226-u75 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 	};
 	ina226-u78 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
 	};
 	ina226-u79 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 	};
 	ina226-u82 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;
 	};
 	ina226-u84 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 	};
 };
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index f9d7528ff2e..2bf6af9c065 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -45,27 +45,33 @@
 
 	ina226-vcc-aux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
 	};
 	ina226-vcc-ram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
 	};
 	ina226-vcc1v1-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
 	};
 	ina226-vcc1v2-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
 	};
 	ina226-vdd1-1v8-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
 			      <&vdd1_1v8_lp4 3>;
 	};
 	ina226-vcc0v6-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
 	};
 };
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index b4da0d341c3..fbeae394c62 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -45,22 +45,27 @@
 
 	ina226-vcc-aux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
 	};
 	ina226-vcc-ram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
 	};
 	ina226-vcc1v1-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
 	};
 	ina226-vcc1v2-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
 	};
 	ina226-vdd1-1v8-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
 			      <&vdd1_1v8_lp4 3>;
 	};
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 729efd4098c..33a86fad604 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -45,22 +45,27 @@
 
 	ina226-vcc-aux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
 	};
 	ina226-vcc-ram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
 	};
 	ina226-vcc1v1-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
 	};
 	ina226-vcc1v2-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
 	};
 	ina226-vdd1-1v8-lp4 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
 			      <&vdd1_1v8_lp4 3>;
 	};
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 6181072c1da..afaecfa5a27 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -136,7 +136,6 @@
 		#size-cells = <0>;
 
 		phy0: ethernet-phy@1 {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <1>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -194,93 +193,97 @@
 	/* QSPI should also have PINCTRL setup */
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <40000000>; /* 40MHz */
-		partition@0 {
-			label = "Image Selector";
-			reg = <0x0 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@80000 {
-			label = "Image Selector Golden";
-			reg = <0x80000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@100000 {
-			label = "Persistent Register";
-			reg = <0x100000 0x20000>; /* 128KB */
-		};
-		partition@120000 {
-			label = "Persistent Register Backup";
-			reg = <0x120000 0x20000>; /* 128KB */
-		};
-		partition@140000 {
-			label = "Open_1";
-			reg = <0x140000 0xc0000>; /* 768KB */
-		};
-		partition@200000 {
-			label = "Image A (FSBL, PMU, ATF, U-Boot)";
-			reg = <0x200000 0xd00000>; /* 13MB */
-		};
-		partition@f00000 {
-			label = "ImgSel Image A Catch";
-			reg = <0xf00000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@f80000 {
-			label = "Image B (FSBL, PMU, ATF, U-Boot)";
-			reg = <0xf80000 0xd00000>; /* 13MB */
-		};
-		partition@1c80000 {
-			label = "ImgSel Image B Catch";
-			reg = <0x1c80000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@1d00000 {
-			label = "Open_2";
-			reg = <0x1d00000 0x100000>; /* 1MB */
-		};
-		partition@1e00000 {
-			label = "Recovery Image";
-			reg = <0x1e00000 0x200000>; /* 2MB */
-			read-only;
-			lock;
-		};
-		partition@2000000 {
-			label = "Recovery Image Backup";
-			reg = <0x2000000 0x200000>; /* 2MB */
-			read-only;
-			lock;
-		};
-		partition@2200000 {
-			label = "U-Boot storage variables";
-			reg = <0x2200000 0x20000>; /* 128KB */
-		};
-		partition@2220000 {
-			label = "U-Boot storage variables backup";
-			reg = <0x2220000 0x20000>; /* 128KB */
-		};
-		partition@2240000 {
-			label = "SHA256";
-			reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
-			read-only;
-			lock;
-		};
-		partition@2280000 {
-			label = "Secure OS Storage";
-			reg = <0x2280000 0x20000>; /* 128KB */
-		};
-		partition@22a0000 {
-			label = "User";
-			reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "Image Selector";
+				reg = <0x0 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@80000 {
+				label = "Image Selector Golden";
+				reg = <0x80000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@100000 {
+				label = "Persistent Register";
+				reg = <0x100000 0x20000>; /* 128KB */
+			};
+			partition@120000 {
+				label = "Persistent Register Backup";
+				reg = <0x120000 0x20000>; /* 128KB */
+			};
+			partition@140000 {
+				label = "Open_1";
+				reg = <0x140000 0xc0000>; /* 768KB */
+			};
+			partition@200000 {
+				label = "Image A (FSBL, PMU, ATF, U-Boot)";
+				reg = <0x200000 0xd00000>; /* 13MB */
+			};
+			partition@f00000 {
+				label = "ImgSel Image A Catch";
+				reg = <0xf00000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@f80000 {
+				label = "Image B (FSBL, PMU, ATF, U-Boot)";
+				reg = <0xf80000 0xd00000>; /* 13MB */
+			};
+			partition@1c80000 {
+				label = "ImgSel Image B Catch";
+				reg = <0x1c80000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@1d00000 {
+				label = "Open_2";
+				reg = <0x1d00000 0x100000>; /* 1MB */
+			};
+			partition@1e00000 {
+				label = "Recovery Image";
+				reg = <0x1e00000 0x200000>; /* 2MB */
+				read-only;
+				lock;
+			};
+			partition@2000000 {
+				label = "Recovery Image Backup";
+				reg = <0x2000000 0x200000>; /* 2MB */
+				read-only;
+				lock;
+			};
+			partition@2200000 {
+				label = "U-Boot storage variables";
+				reg = <0x2200000 0x20000>; /* 128KB */
+			};
+			partition@2220000 {
+				label = "U-Boot storage variables backup";
+				reg = <0x2220000 0x20000>; /* 128KB */
+			};
+			partition@2240000 {
+				label = "SHA256";
+				reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
+				read-only;
+				lock;
+			};
+			partition@2280000 {
+				label = "Secure OS Storage";
+				reg = <0x2280000 0x20000>; /* 128KB */
+			};
+			partition@22a0000 {
+				label = "User";
+				reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts
index 530a4a5f080..b9b192f0986 100644
--- a/arch/arm/dts/zynqmp-sc-revC.dts
+++ b/arch/arm/dts/zynqmp-sc-revC.dts
@@ -23,7 +23,6 @@
 		#size-cells = <0>;
 
 		phy0: ethernet-phy@1 { /* ADI1300 */
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id0283.bc30";
 			reg = <1>;
 			adi,rx-internal-delay-ps = <2400>;
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
index e94b784e8e1..7212ee9df86 100644
--- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP VEK280 revA
  *
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -13,8 +13,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
-		     "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
index a3983f330d0..a57e9b50b20 100644
--- a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP VEK280 revB
  *
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -10,6 +10,5 @@
 #include "zynqmp-sc-vek280-revA.dtso"
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
-		     "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
 };
diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
index fd25731b0b4..2fe35596143 100644
--- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VHK158 revA
  *
  * (C) Copyright 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
-		     "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
index 4d0f10e13c3..58be0e1c890 100644
--- a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP VM-P-M1369-00
  *
- * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ * Copyright (C) 2024-2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -18,66 +18,82 @@
 
 	ina226-u19 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>;
 	};
 	ina226-u287 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
 	};
 	ina226-u288 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>;
 	};
 	ina226-u289 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
 	};
 	ina226-u290 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>;
 	};
 	ina226-u291 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
 	};
 	ina226-u292 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
 	};
 	ina226-u293 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
 	};
 	ina226-u294 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
 	};
 	ina226-u295 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>;
 	};
 	ina226-u298 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>;
 	};
 	ina226-u296 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>;
 	};
 	ina226-u299 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>;
 	};
 	ina226-u300 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>;
 	};
 	ina226-u301 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>;
 	};
 	ina226-u297 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>;
 	};
 };
@@ -393,7 +409,7 @@
 	};
 
 	/* connected via J425 connector
-	 ucd90320: power-sequencer@73 { // u16
+	ucd90320: power-sequencer@73 { // u16
 		compatible = "ti,ucd90320";
 		reg = <0x73>;
 	};*/
diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
index 5a4e5f09250..39be25be8f6 100644
--- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
@@ -22,66 +22,82 @@
 
 	ina226-u1700 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
 	};
 	ina226-u1732 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>;
 	};
 	ina226-u1733 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
 	};
 	ina226-u1736 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>;
 	};
 	ina226-u1737 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
 	};
 	ina226-u1739 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
 	};
 	ina226-u1741 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
 	};
 	ina226-u1743 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
 	};
 	ina226-u1745 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>;
 	};
 	ina226-u1747 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>;
 	};
 	ina226-u1750 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtyp_avcc_ina 0>, <&gtyp_avcc_ina 1>, <&gtyp_avcc_ina 2>;
 	};
 	ina226-u1752 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtyp_avtt_ina 0>, <&gtyp_avtt_ina 1>, <&gtyp_avtt_ina 2>;
 	};
 	ina226-u1754 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtyp_avccaux_ina 0>, <&gtyp_avccaux_ina 1>, <&gtyp_avccaux_ina 2>;
 	};
 	ina226-u1756 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>;
 	};
 	ina226-u1758 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>;
 	};
 	ina226-u1760 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>;
 	};
 
diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
index 29b3a73fde0..ae0691c0127 100644
--- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VPK120 revB
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
-		     "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp";
 };
 
 &i2c0 {
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
index 10466ce99de..9b6534f6383 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VPK180 revA
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
-		     "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
index 74e1c5c6dc9..941d26c025a 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
@@ -1,9 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * dts file for Xilinx ZynqMP VPK180 revA
+ * dts file for Xilinx ZynqMP VPK180 revB
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
-		     "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 8342479b108..a32073fa040 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -50,6 +50,24 @@
 		gpio-controller;
 		gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
 	};
+
+	vdd_usb_hub: regulator-vdd-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usb_hub";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd2_usb_hub: regulator-vdd2-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd2_usb_hub";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &can0 {
@@ -76,7 +94,6 @@
 	slg7xl45106: gpio@11 { /* u13 - reset logic */
 		compatible = "dlg,slg7xl45106";
 		reg = <0x11>;
-		label = "resetchip";
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpio-line-names = "USB0_PHY_RESET_B", "",
@@ -124,6 +141,8 @@
 		peer-hub = <&hub_3_0>;
 		i2c-bus = <&hub>;
 		reset-gpios = <&slg_delay 0 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -148,7 +167,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@8 { /* Adin u31 */
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id0283.bc30";
 			reg = <8>;
 			adi,rx-internal-delay-ps = <2000>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index db042ffb4f3..31b3c3582c2 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -66,6 +66,7 @@
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
 	};
+
 	dpcon {
 		compatible = "dp-connector";
 		label = "P11";
@@ -85,6 +86,24 @@
 		gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>,
 			<&slg7xl45106 4 GPIO_ACTIVE_LOW>;
 	};
+
+	vdd_usb_hub: regulator-vdd-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usb_hub";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd2_usb_hub: regulator-vdd2-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd2_usb_hub";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -105,7 +124,6 @@
 	slg7xl45106: gpio@11 { /* u19 - reset logic */
 		compatible = "dlg,slg7xl45106";
 		reg = <0x11>;
-		label = "resetchip";
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
@@ -196,6 +214,8 @@
 		peer-hub = <&hub_3_0>;
 		i2c-bus = <&hub_1>;
 		reset-gpios = <&slg_delay 0 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -233,6 +253,8 @@
 		peer-hub = <&hub1_3_0>;
 		i2c-bus = <&hub_2>;
 		reset-gpios = <&slg_delay 1 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -265,7 +287,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@4 { /* u81 */
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <4>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -277,7 +298,6 @@
 			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
 		};
 		phy1: ethernet-phy@8 { /* u36 */
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <8>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index e3567d0abfe..f1114a35aae 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -86,6 +86,24 @@
 		gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>,
 			<&slg7xl45106 4 GPIO_ACTIVE_LOW>;
 	};
+
+	vdd_usb_hub: regulator-vdd-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usb_hub";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd2_usb_hub: regulator-vdd2-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd2_usb_hub";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -106,7 +124,6 @@
 	slg7xl45106: gpio@11 { /* u19 - reset logic */
 		compatible = "dlg,slg7xl45106";
 		reg = <0x11>;
-		label = "resetchip";
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
@@ -197,6 +214,8 @@
 		peer-hub = <&hub_3_0>;
 		i2c-bus = <&hub_1>;
 		reset-gpios = <&slg_delay 0 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -234,6 +253,8 @@
 		peer-hub = <&hub1_3_0>;
 		i2c-bus = <&hub_2>;
 		reset-gpios = <&slg_delay 1 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -266,7 +287,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@4 { /* u81 */
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <4>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -278,7 +298,6 @@
 			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
 		};
 		phy1: ethernet-phy@8 { /* u36 */
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <8>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index f93c7460a55..967548744d5 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -85,6 +85,24 @@
 		gpio-controller;
 		gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 	};
+
+	vdd_usb_hub: regulator-vdd-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usb_hub";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd2_usb_hub: regulator-vdd2-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd2_usb_hub";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -169,6 +187,8 @@
 		reg = <1>;
 		peer-hub = <&hub_3_0>;
 		reset-gpios = <&slg_delay 0 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -209,7 +229,6 @@
 		#size-cells = <0>;
 
 		phy0: ethernet-phy@1 {
-			#phy-cells = <1>;
 			reg = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -227,23 +246,23 @@
 	status = "okay";
 
 	pinctrl_gpio0_default: gpio0-default {
-                conf {
-                        groups = "gpio0_38_grp";
-                        bias-pull-up;
-                        power-source = <IO_STANDARD_LVCMOS18>;
-                };
+		conf {
+			groups = "gpio0_38_grp";
+			bias-pull-up;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
 
-                mux {
-                        groups = "gpio0_38_grp";
-                        function = "gpio0";
-                };
+		mux {
+			groups = "gpio0_38_grp";
+			function = "gpio0";
+		};
 
-                conf-tx {
-                        pins = "MIO38";
-                        bias-disable;
-                        output-enable;
-                };
-        };
+		conf-tx {
+			pins = "MIO38";
+			bias-disable;
+			output-enable;
+		};
+	};
 
 	pinctrl_uart1_default: uart1-default {
 		conf {
@@ -402,9 +421,9 @@
 };
 
 &gpio {
-        status = "okay";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_gpio0_default>;
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio0_default>;
 };
 
 &uart1 {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index 70de6933600..0fa5a990adc 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * dts file for KV260 revA Carrier Card
+ * dts file for KV260 revB Carrier Card
  *
  * (C) Copyright 2020 - 2022, Xilinx, Inc.
  * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
@@ -81,6 +81,24 @@
 		gpio-controller;
 		gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 	};
+
+	vdd_usb_hub: regulator-vdd-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usb_hub";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd2_usb_hub: regulator-vdd2-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd2_usb_hub";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
 };
 
 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -156,6 +174,8 @@
 		peer-hub = <&hub_3_0>;
 		i2c-bus = <&hub>;
 		reset-gpios = <&slg_delay 0 10000 10000>;
+		vdd-supply = <&vdd_usb_hub>;
+		vdd2-supply = <&vdd2_usb_hub>;
 	};
 
 	/* 3.0 hub on port 2 */
@@ -200,7 +220,6 @@
 		#size-cells = <0>;
 
 		phy0: ethernet-phy@1 {
-			#phy-cells = <1>;
 			reg = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
index 653bd936226..34ee6af801d 100644
--- a/arch/arm/dts/zynqmp-sm-k24-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP SM-K24 RevA
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022-2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -21,3 +21,8 @@
 		reg = <0 0 0 0x80000000>;
 	};
 };
+
+&cma {
+	size = <0x0 0x4000000>;
+	alignment = <0x0 0x4000000>;
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 0abec77b3f3..c7fe253244f 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -61,6 +61,15 @@
 			reg = <0x0 0x7ff00000 0x0 0x100000>;
 			no-map;
 		};
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
 	};
 
 	gpio-keys {
diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
index 2037686b9b4..1dc0414b33d 100644
--- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
+++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
@@ -63,23 +63,27 @@
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <166000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@0 {
-			label = "qspi-boot-bin";
-			reg = <0x00000 0x60000>;
-		};
-		partition@60000 {
-			label = "qspi-u-boot-itb";
-			reg = <0x60000 0x100000>;
-		};
-		partition@160000 {
-			label = "qspi-u-boot-env";
-			reg = <0x160000 0x20000>;
-		};
-		partition@200000 {
-			label = "qspi-rootfs";
-			reg = <0x200000 0x1e00000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "qspi-boot-bin";
+				reg = <0x00000 0x60000>;
+			};
+			partition@60000 {
+				label = "qspi-u-boot-itb";
+				reg = <0x60000 0x100000>;
+			};
+			partition@160000 {
+				label = "qspi-u-boot-env";
+				reg = <0x160000 0x20000>;
+			};
+			partition@200000 {
+				label = "qspi-rootfs";
+				reg = <0x200000 0x1e00000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index e9c6d249a8d..94167770ed6 100644
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -88,15 +88,19 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>;
 		spi-tx-bus-width = <4>; /* maybe 4 here */
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>;
-		partition@0 { /* for testing purpose */
-			label = "qspi";
-			reg = <0 0x4000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi";
+				reg = <0 0x4000000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index bd1e2557187..3e461d9c4d0 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -88,15 +88,19 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>;
-		partition@0 { /* for testing purpose */
-			label = "qspi";
-			reg = <0 0x4000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi";
+				reg = <0 0x4000000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 9dcb9095371..f0e2a0b4588 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -31,6 +31,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &dcc {
@@ -40,28 +55,32 @@
 &qspi {
 	status = "okay";
 	flash@0 {
-		compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */
-		#address-cells = <1>;
-		#size-cells = <1>;
+		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
 		reg = <0x0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index cf3e9583204..e92caefd3aa 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -32,6 +32,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &dcc {
@@ -42,27 +57,31 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 32f317f3df4..2897c423f82 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
  * (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -41,6 +41,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	clock_si5338_0: clk27 {	/* u55 SI5338-GM */
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -357,28 +372,32 @@
 	num-cs = <2>;
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>, <1>;
 		parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index e3d5cf972e8..0b1185d862c 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  *
  * (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -39,6 +39,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &can0 {
@@ -138,8 +153,6 @@
 
 	nand@0 {
 		reg = <0x0>;
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
 		nand-ecc-mode = "hw";
 		nand-rb = <0>;
 		label = "main-storage-0";
@@ -147,35 +160,39 @@
 		nand-ecc-strength = <24>;
 		nand-on-flash-bbt;
 
-		partition@0 {	/* for testing purpose */
-			label = "nand-fsbl-uboot";
-			reg = <0x0 0x0 0x400000>;
-		};
-		partition@1 {	/* for testing purpose */
-			label = "nand-linux";
-			reg = <0x0 0x400000 0x1400000>;
-		};
-		partition@2 {	/* for testing purpose */
-			label = "nand-device-tree";
-			reg = <0x0 0x1800000 0x400000>;
-		};
-		partition@3 {	/* for testing purpose */
-			label = "nand-rootfs";
-			reg = <0x0 0x1c00000 0x1400000>;
-		};
-		partition@4 {	/* for testing purpose */
-			label = "nand-bitstream";
-			reg = <0x0 0x3000000 0x400000>;
-		};
-		partition@5 {	/* for testing purpose */
-			label = "nand-misc";
-			reg = <0x0 0x3400000 0xfcc00000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <2>;
+			#size-cells = <1>;
+
+			partition@0 {	/* for testing purpose */
+				label = "nand-fsbl-uboot";
+				reg = <0x0 0x0 0x400000>;
+			};
+			partition@1 {	/* for testing purpose */
+				label = "nand-linux";
+				reg = <0x0 0x400000 0x1400000>;
+			};
+			partition@2 {	/* for testing purpose */
+				label = "nand-device-tree";
+				reg = <0x0 0x1800000 0x400000>;
+			};
+			partition@3 {	/* for testing purpose */
+				label = "nand-rootfs";
+				reg = <0x0 0x1c00000 0x1400000>;
+			};
+			partition@4 {	/* for testing purpose */
+				label = "nand-bitstream";
+				reg = <0x0 0x3000000 0x400000>;
+			};
+			partition@5 {	/* for testing purpose */
+				label = "nand-misc";
+				reg = <0x0 0x3400000 0xfcc00000>;
+			};
 		};
 	};
 	nand@1 {
 		reg = <0x1>;
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
 		nand-ecc-mode = "hw";
 		nand-rb = <0>;
 		label = "main-storage-1";
@@ -183,29 +200,35 @@
 		nand-ecc-strength = <24>;
 		nand-on-flash-bbt;
 
-		partition@0 {	/* for testing purpose */
-			label = "nand1-fsbl-uboot";
-			reg = <0x0 0x0 0x400000>;
-		};
-		partition@1 {	/* for testing purpose */
-			label = "nand1-linux";
-			reg = <0x0 0x400000 0x1400000>;
-		};
-		partition@2 {	/* for testing purpose */
-			label = "nand1-device-tree";
-			reg = <0x0 0x1800000 0x400000>;
-		};
-		partition@3 {	/* for testing purpose */
-			label = "nand1-rootfs";
-			reg = <0x0 0x1c00000 0x1400000>;
-		};
-		partition@4 {	/* for testing purpose */
-			label = "nand1-bitstream";
-			reg = <0x0 0x3000000 0x400000>;
-		};
-		partition@5 {	/* for testing purpose */
-			label = "nand1-misc";
-			reg = <0x0 0x3400000 0xfcc00000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <2>;
+			#size-cells = <1>;
+
+			partition@0 {	/* for testing purpose */
+				label = "nand1-fsbl-uboot";
+				reg = <0x0 0x0 0x400000>;
+			};
+			partition@1 {	/* for testing purpose */
+				label = "nand1-linux";
+				reg = <0x0 0x400000 0x1400000>;
+			};
+			partition@2 {	/* for testing purpose */
+				label = "nand1-device-tree";
+				reg = <0x0 0x1800000 0x400000>;
+			};
+			partition@3 {	/* for testing purpose */
+				label = "nand1-rootfs";
+				reg = <0x0 0x1c00000 0x1400000>;
+			};
+			partition@4 {	/* for testing purpose */
+				label = "nand1-bitstream";
+				reg = <0x0 0x3000000 0x400000>;
+			};
+			partition@5 {	/* for testing purpose */
+				label = "nand1-misc";
+				reg = <0x0 0x3400000 0xfcc00000>;
+			};
 		};
 	};
 };
@@ -503,15 +526,18 @@
 	pinctrl-0 = <&pinctrl_spi0_default>;
 
 	spi0_flash0: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
 		compatible = "sst,sst25wf080", "jedec,spi-nor";
 		spi-max-frequency = <50000000>;
 		reg = <0>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
-		partition@0 {
-			label = "spi0-data";
-			reg = <0x0 0x100000>;
+			partition@0 {
+				label = "spi0-data";
+				reg = <0x0 0x100000>;
+			};
 		};
 	};
 };
@@ -523,15 +549,18 @@
 	pinctrl-0 = <&pinctrl_spi1_default>;
 
 	spi1_flash0: flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
 		compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
 		spi-max-frequency = <20000000>;
 		reg = <0>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
 
-		partition@0 {
-			label = "spi1-data";
-			reg = <0x0 0x84000>;
+			partition@0 {
+				label = "spi1-data";
+				reg = <0x0 0x84000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index a8856c20f5b..bfcc92cedfa 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -39,6 +39,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	clock_si5338_2: clk26 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -133,8 +148,6 @@
 
 	nand@0 {
 		reg = <0x0>;
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
 		nand-ecc-mode = "hw";
 		nand-rb = <0>;
 		label = "main-storage-0";
@@ -142,65 +155,74 @@
 		nand-ecc-strength = <24>;
 		nand-on-flash-bbt;
 
-		partition@0 {	/* for testing purpose */
-			label = "nand-fsbl-uboot";
-			reg = <0x0 0x0 0x400000>;
-		};
-		partition@1 {	/* for testing purpose */
-			label = "nand-linux";
-			reg = <0x0 0x400000 0x1400000>;
-		};
-		partition@2 {	/* for testing purpose */
-			label = "nand-device-tree";
-			reg = <0x0 0x1800000 0x400000>;
-		};
-		partition@3 {	/* for testing purpose */
-			label = "nand-rootfs";
-			reg = <0x0 0x1c00000 0x1400000>;
-		};
-		partition@4 {	/* for testing purpose */
-			label = "nand-bitstream";
-			reg = <0x0 0x3000000 0x400000>;
-		};
-		partition@5 {	/* for testing purpose */
-			label = "nand-misc";
-			reg = <0x0 0x3400000 0xfcc00000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <2>;
+			#size-cells = <1>;
+
+			partition@0 {	/* for testing purpose */
+				label = "nand-fsbl-uboot";
+				reg = <0x0 0x0 0x400000>;
+			};
+			partition@1 {	/* for testing purpose */
+				label = "nand-linux";
+				reg = <0x0 0x400000 0x1400000>;
+			};
+			partition@2 {	/* for testing purpose */
+				label = "nand-device-tree";
+				reg = <0x0 0x1800000 0x400000>;
+			};
+			partition@3 {	/* for testing purpose */
+				label = "nand-rootfs";
+				reg = <0x0 0x1c00000 0x1400000>;
+			};
+			partition@4 {	/* for testing purpose */
+				label = "nand-bitstream";
+				reg = <0x0 0x3000000 0x400000>;
+			};
+			partition@5 {	/* for testing purpose */
+				label = "nand-misc";
+				reg = <0x0 0x3400000 0xfcc00000>;
+			};
 		};
 	};
 	nand@1 {
 		reg = <0x1>;
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
 		nand-ecc-mode = "hw";
 		nand-rb = <0>;
 		label = "main-storage-1";
 		nand-ecc-step-size = <1024>;
 		nand-ecc-strength = <24>;
 		nand-on-flash-bbt;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <2>;
+			#size-cells = <1>;
 
-		partition@0 {	/* for testing purpose */
-			label = "nand1-fsbl-uboot";
-			reg = <0x0 0x0 0x400000>;
-		};
-		partition@1 {	/* for testing purpose */
-			label = "nand1-linux";
-			reg = <0x0 0x400000 0x1400000>;
-		};
-		partition@2 {	/* for testing purpose */
-			label = "nand1-device-tree";
-			reg = <0x0 0x1800000 0x400000>;
-		};
-		partition@3 {	/* for testing purpose */
-			label = "nand1-rootfs";
-			reg = <0x0 0x1c00000 0x1400000>;
-		};
-		partition@4 {	/* for testing purpose */
-			label = "nand1-bitstream";
-			reg = <0x0 0x3000000 0x400000>;
-		};
-		partition@5 {	/* for testing purpose */
-			label = "nand1-misc";
-			reg = <0x0 0x3400000 0xfcc00000>;
+			partition@0 {	/* for testing purpose */
+				label = "nand1-fsbl-uboot";
+				reg = <0x0 0x0 0x400000>;
+			};
+			partition@1 {	/* for testing purpose */
+				label = "nand1-linux";
+				reg = <0x0 0x400000 0x1400000>;
+			};
+			partition@2 {	/* for testing purpose */
+				label = "nand1-device-tree";
+				reg = <0x0 0x1800000 0x400000>;
+			};
+			partition@3 {	/* for testing purpose */
+				label = "nand1-rootfs";
+				reg = <0x0 0x1c00000 0x1400000>;
+			};
+			partition@4 {	/* for testing purpose */
+				label = "nand1-bitstream";
+				reg = <0x0 0x3000000 0x400000>;
+			};
+			partition@5 {	/* for testing purpose */
+				label = "nand1-misc";
+				reg = <0x0 0x3400000 0xfcc00000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 3b03b39e456..9b59952993f 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -38,6 +38,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &can0 {
@@ -174,27 +189,31 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 53aa3dca1dc..722b2e833b4 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -37,6 +37,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &fpd_dma_chan1 {
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 4ec8a400494..81353b60b38 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU100 revC
  *
  * (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  * Nathalie Chan King Choy
@@ -47,6 +47,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -61,6 +76,7 @@
 
 	iio-hwmon {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
 			      <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
 			      <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
@@ -120,6 +136,7 @@
 
 	ina226 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
 	};
 
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 6b1aea95e65..4d5f4754171 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
  * (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -45,6 +45,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -68,74 +83,92 @@
 
 	ina226-u76 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
 	};
 	ina226-u77 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
 	};
 	ina226-u78 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
 	};
 	ina226-u87 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
 	};
 	ina226-u85 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
 	};
 	ina226-u86 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
 	};
 	ina226-u93 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
 	};
 	ina226-u88 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
 	};
 	ina226-u15 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 	};
 	ina226-u92 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 	};
 	ina226-u79 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 	};
 	ina226-u81 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 	};
 	ina226-u80 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 	};
 	ina226-u84 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 	};
 	ina226-u16 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 	};
 	ina226-u65 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 	};
 	ina226-u74 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 	};
 	ina226-u75 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 	};
 
@@ -217,7 +250,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@21 {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <21>;
 			ti,rx-internal-delay = <0x8>;
@@ -987,28 +1019,32 @@
 	num-cs = <2>;
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>, <1>;
 		parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 3c28130909b..bad59d7b1d2 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -19,7 +19,6 @@
 	phy-handle = <&phyc>;
 	mdio: mdio {
 		phyc: ethernet-phy@c {
-			#phy-cells = <0x1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 0bfeed4293c..4479ff73514 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU104
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -43,6 +43,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	clock_8t49n287_5: clk125 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -126,7 +141,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
@@ -453,27 +467,31 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index a7387f4a0e6..0f1b1fd92a7 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU104
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -43,8 +43,24 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	ina226 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
 	};
 
@@ -131,7 +147,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
@@ -465,27 +480,31 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 7b1097579fc..ad76159084e 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU106
  *
  * (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -45,6 +45,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -68,74 +83,92 @@
 
 	ina226-u76 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
 	};
 	ina226-u77 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
 	};
 	ina226-u78 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
 	};
 	ina226-u87 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
 	};
 	ina226-u85 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
 	};
 	ina226-u86 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
 	};
 	ina226-u93 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
 	};
 	ina226-u88 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
 	};
 	ina226-u15 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 	};
 	ina226-u92 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 	};
 	ina226-u79 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 	};
 	ina226-u81 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 	};
 	ina226-u80 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 	};
 	ina226-u84 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 	};
 	ina226-u16 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 	};
 	ina226-u65 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 	};
 	ina226-u74 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 	};
 	ina226-u75 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 	};
 
@@ -217,7 +250,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			reg = <0xc>;
 			compatible = "ethernet-phy-id2000.a231";
 			ti,rx-internal-delay = <0x8>;
@@ -981,28 +1013,32 @@
 	num-cs = <2>;
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>, <1>;
 		parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index ba1b6339100..a9a47360237 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU111
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -45,6 +45,21 @@
 		/* Another 4GB connected to PL */
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -68,58 +83,72 @@
 
 	ina226-u67 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
 	};
 	ina226-u59 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
 	};
 	ina226-u61 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
 	};
 	ina226-u60 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
 	};
 	ina226-u64 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
 	};
 	ina226-u69 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
 	};
 	ina226-u66 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
 	};
 	ina226-u65 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 	};
 	ina226-u63 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
 	};
 	ina226-u3 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
 	};
 	ina226-u71 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
 	};
 	ina226-u77 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
 	};
 	ina226-u73 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
 	};
 	ina226-u79 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 	};
 
@@ -189,7 +218,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
@@ -804,28 +832,32 @@
 	num-cs = <2>;
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0>, <1>;
 		parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index cc9f5b16025..1a49ae3ba4e 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -32,6 +32,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &dcc {
@@ -46,27 +61,31 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index f78da036280..1b6f7a605d6 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -35,6 +35,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &dcc {
@@ -73,27 +88,31 @@
 	status = "okay";
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
-		#address-cells = <1>;
-		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <1>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
-		partition@0 { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@100000 { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@600000 { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@620000 { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5e0000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 { /* for testing purpose */
+				label = "qspi-fsbl-uboot";
+				reg = <0x0 0x100000>;
+			};
+			partition@100000 { /* for testing purpose */
+				label = "qspi-linux";
+				reg = <0x100000 0x500000>;
+			};
+			partition@600000 { /* for testing purpose */
+				label = "qspi-device-tree";
+				reg = <0x600000 0x20000>;
+			};
+			partition@620000 { /* for testing purpose */
+				label = "qspi-rootfs";
+				reg = <0x620000 0x5e0000>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 86a3217f9ab..b2d71f0f455 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -36,6 +36,21 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
 };
 
 &dcc {
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 888f711aad9..60231d7d3a2 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -43,6 +43,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -66,61 +81,75 @@
 
 	ina226-vccint {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
 	};
 	ina226-vccint-io-bram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
 			      <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
 	};
 	ina226-vcc1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
 	};
 	ina226-vcc1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
 	};
 	ina226-vadj-fmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
 	};
 	ina226-mgtavcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
 	};
 	ina226-mgt1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
 	};
 	ina226-mgt1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
 	};
 	ina226-vccint-ams {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
 	};
 	ina226-dac-avtt {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
 	};
 	ina226-dac-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
 			      <&dac_avccaux 3>;
 	};
 	ina226-adc-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
 	};
 	ina226-adc-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
 			      <&adc_avccaux 3>;
 	};
 	ina226-dac-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
 	};
 
@@ -176,7 +205,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index ccdbf8967aa..bfe6f97a760 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -43,6 +43,21 @@
 		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -66,61 +81,75 @@
 
 	ina226-vccint {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
 	};
 	ina226-vccint-io-bram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
 			      <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
 	};
 	ina226-vcc1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
 	};
 	ina226-vcc1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
 	};
 	ina226-vadj-fmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
 	};
 	ina226-mgtavcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
 	};
 	ina226-mgt1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
 	};
 	ina226-mgt1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
 	};
 	ina226-vccint-ams {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
 	};
 	ina226-dac-avtt {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
 	};
 	ina226-dac-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
 			      <&dac_avccaux 3>;
 	};
 	ina226-adc-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
 	};
 	ina226-adc-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
 			      <&adc_avccaux 3>;
 	};
 	ina226-dac-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
 	};
 
@@ -183,7 +212,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index 058d6b2e648..08e88745477 100644
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU670 (67DR)
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -46,6 +46,21 @@
 		/* Another 4GB connected to PL */
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -69,61 +84,75 @@
 
 	ina226-vccint {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
 	};
 	ina226-vccint-io-bram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
 			      <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
 	};
 	ina226-vcc1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
 	};
 	ina226-vcc1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
 	};
 	ina226-vadj-fmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
 	};
 	ina226-mgtavcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
 	};
 	ina226-mgt1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
 	};
 	ina226-mgt1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
 	};
 	ina226-vccint-ams {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
 	};
 	ina226-dac-avtt {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
 	};
 	ina226-dac-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
 			      <&dac_avccaux 3>;
 	};
 	ina226-adc-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
 	};
 	ina226-adc-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
 			      <&adc_avccaux 3>;
 	};
 	ina226-dac-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
 	};
 
@@ -185,7 +214,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index 010d412b202..5c9195239f1 100644
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP ZCU670 (67DR) revB
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
@@ -46,6 +46,21 @@
 		/* Another 4GB connected to PL */
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x8000000>;
+			alignment = <0x0 0x8000000>;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -69,61 +84,75 @@
 
 	ina226-vccint {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
 	};
 	ina226-vccint-io-bram {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
 			      <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
 	};
 	ina226-vcc1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
 	};
 	ina226-vcc1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
 	};
 	ina226-vadj-fmc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
 	};
 	ina226-mgtavcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
 	};
 	ina226-mgt1v2 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
 	};
 	ina226-mgt1v8 {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
 	};
 	ina226-vccint-ams {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
 	};
 	ina226-dac-avtt {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
 	};
 	ina226-dac-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
 			      <&dac_avccaux 3>;
 	};
 	ina226-adc-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
 	};
 	ina226-adc-avccaux {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
 			      <&adc_avccaux 3>;
 	};
 	ina226-dac-avcc {
 		compatible = "iio-hwmon";
+		status = "disabled";
 		io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
 	};
 
@@ -185,7 +214,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		phy0: ethernet-phy@c {
-			#phy-cells = <1>;
 			compatible = "ethernet-phy-id2000.a231";
 			reg = <0xc>;
 			ti,rx-internal-delay = <0x8>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 13cfca66657..c225eb219f4 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -1006,7 +1006,6 @@
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "alarm", "sec";
-			calibration = <0x7FFF>;
 		};
 
 		sata: ahci@fd0c0000 {
diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c
index 78ead1f45f6..7df7c49ac71 100644
--- a/arch/arm/mach-versal-net/cpu.c
+++ b/arch/arm/mach-versal-net/cpu.c
@@ -7,6 +7,10 @@
  */
 
 #include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <vsprintf.h>
 #include <asm/armv8/mmu.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
@@ -15,6 +19,9 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/cache.h>
 #include <dm/platdata.h>
+#include <linux/bitfield.h>
+#include <linux/string.h>
+#include "../../../board/xilinx/common/board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -88,6 +95,148 @@ u64 get_page_table_size(void)
 	return 0x14000;
 }
 
+void versal_net_timer_setup(void)
+{
+	u32 val;
+
+	debug("iou_switch ctrl div0 %x\n",
+	      readl(&crlapb_base->iou_switch_ctrl));
+
+	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+	       &crlapb_base->iou_switch_ctrl);
+
+	/* Global timer init - Program time stamp reference clk */
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+	writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+	debug("ref ctrl 0x%x\n",
+	      readl(&crlapb_base->timestamp_ref_ctrl));
+
+	/* Clear reset of timestamp reg */
+	writel(0, &crlapb_base->rst_timestamp);
+
+	/*
+	 * Program freq register in System counter and
+	 * enable system counter.
+	 */
+	writel(CONFIG_COUNTER_FREQUENCY,
+	       &iou_scntr_secure->base_frequency_id_register);
+
+	debug("counter val 0x%x\n",
+	      readl(&iou_scntr_secure->base_frequency_id_register));
+
+	writel(IOU_SCNTRS_CONTROL_EN,
+	       &iou_scntr_secure->counter_control_register);
+
+	debug("scntrs control 0x%x\n",
+	      readl(&iou_scntr_secure->counter_control_register));
+	debug("timer 0x%llx\n", get_ticks());
+	debug("timer 0x%llx\n", get_ticks());
+}
+
+u32 versal_net_bootmode_reg(void)
+{
+	return readl(&crp_base->boot_mode_usr);
+}
+
+u8 __weak versal_net_get_bootmode(void)
+{
+	u32 reg = versal_net_bootmode_reg();
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	return reg & BOOT_MODES_MASK;
+}
+
+static u32 platform_id, platform_version;
+
+char *soc_name_decode(void)
+{
+	char *name, *platform_name;
+
+	switch (platform_id) {
+	case VERSAL_NET_SPP:
+		platform_name = "ipp";
+		break;
+	case VERSAL_NET_EMU:
+		platform_name = "emu";
+		break;
+	case VERSAL_NET_QEMU:
+		platform_name = "qemu";
+		break;
+	default:
+		return NULL;
+	}
+
+	/*
+	 * --rev. are 6 chars
+	 * max platform name is qemu which is 4 chars
+	 * platform version number are 1+1
+	 * Plus 1 char for \n
+	 */
+	name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
+	if (!name)
+		return NULL;
+
+	sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD,
+		platform_name, platform_version / 10,
+		platform_version % 10);
+
+	return name;
+}
+
+bool soc_detection(void)
+{
+	u32 version, ps_version;
+
+	version = readl(PMC_TAP_VERSION);
+	platform_id = FIELD_GET(PLATFORM_MASK, version);
+	ps_version = FIELD_GET(PS_VERSION_MASK, version);
+
+	debug("idcode %x, version %x, usercode %x\n",
+	      readl(PMC_TAP_IDCODE), version,
+	      readl(PMC_TAP_USERCODE));
+
+	debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
+	      FIELD_GET(PMC_VERSION_MASK, version),
+	      ps_version,
+	      FIELD_GET(RTL_VERSION_MASK, version));
+
+	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
+
+	if (platform_id == VERSAL_NET_SPP ||
+	    platform_id == VERSAL_NET_EMU) {
+		if (ps_version == PS_VERSION_PRODUCTION) {
+			/*
+			 * ES1 version ends at 1.9 version where there was +9
+			 * used because of IPP/SPP conversion. Production
+			 * version have platform_version started from 0 again
+			 * that's why adding +20 to continue with the same line.
+			 * It means the last ES1 version ends at 1.9 version and
+			 * new PRODUCTION line starts at 2.0.
+			 */
+			platform_version += 20;
+		} else {
+			/*
+			 * 9 is diff for
+			 * 0 means 0.9 version
+			 * 1 means 1.0 version
+			 * 2 means 1.1 version
+			 * etc,
+			 */
+			platform_version += 9;
+		}
+	}
+
+	debug("Platform id: %d version: %d.%d\n", platform_id,
+	      platform_version / 10, platform_version % 10);
+
+	return true;
+}
+
 U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
 	.name = "soc_xilinx_versal_net",
 };
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index 23374d10a6b..4907dae1108 100644
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -7,3 +7,9 @@
 #include <linux/build_bug.h>
 
 void mem_map_fill(void);
+/* EL3 clock/timer register setup, called from board_early_init_r() */
+void versal_net_timer_setup(void);
+/* Overridable bootmode decode: weak MMIO default, firmware override */
+u8 versal_net_get_bootmode(void);
+/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */
+u32 versal_net_bootmode_reg(void);
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 0dd5cc153c4..7521d45bc1a 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -1,10 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * (C) Copyright 2026, Advanced Micro Devices, Inc.
+ *
  * Michal Simek <[email protected]>
  */
 
 #include <init.h>
+#include <log.h>
+#include <time.h>
 #include <asm/armv8/mmu.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
@@ -16,7 +20,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define VERSAL_MEM_MAP_USED	5
+#define VERSAL_MEM_MAP_USED	3
 
 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
 
@@ -44,26 +48,13 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
+	}, { /* FPD_AXI_PL_high */
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
 		.size = 0x200000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x600000000UL,
-		.phys = 0x600000000UL,
-		.size = 0x800000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xe00000000UL,
-		.phys = 0xe00000000UL,
-		.size = 0xf200000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}
 };
 
@@ -121,6 +112,72 @@ int arm_reserve_mmu(void)
 }
 #endif
 
+u32 versal_multi_boot_reg(void)
+{
+	return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK;
+}
+
+u32 __weak versal_pmc_multi_boot(void)
+{
+	return versal_multi_boot_reg();
+}
+
+void versal_timer_setup(void)
+{
+	u32 val;
+
+	debug("iou_switch ctrl div0 %x\n",
+	      readl(&crlapb_base->iou_switch_ctrl));
+
+	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+	       &crlapb_base->iou_switch_ctrl);
+
+	/* Global timer init - Program time stamp reference clk */
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+	writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+	debug("ref ctrl 0x%x\n",
+	      readl(&crlapb_base->timestamp_ref_ctrl));
+
+	/* Clear reset of timestamp reg */
+	writel(0, &crlapb_base->rst_timestamp);
+
+	/*
+	 * Program freq register in System counter and
+	 * enable system counter.
+	 */
+	writel(CONFIG_COUNTER_FREQUENCY,
+	       &iou_scntr_secure->base_frequency_id_register);
+
+	debug("counter val 0x%x\n",
+	      readl(&iou_scntr_secure->base_frequency_id_register));
+
+	writel(IOU_SCNTRS_CONTROL_EN,
+	       &iou_scntr_secure->counter_control_register);
+
+	debug("scntrs control 0x%x\n",
+	      readl(&iou_scntr_secure->counter_control_register));
+	debug("timer 0x%llx\n", get_ticks());
+	debug("timer 0x%llx\n", get_ticks());
+}
+
+u32 versal_bootmode_reg(void)
+{
+	return readl(&crp_base->boot_mode_usr);
+}
+
+u8 __weak versal_get_bootmode(void)
+{
+	u32 reg = versal_bootmode_reg();
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	return reg & BOOT_MODES_MASK;
+}
+
 U_BOOT_DRVINFO(soc_xilinx_versal) = {
 	.name = "soc_xilinx_versal",
 };
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index a6dfa556966..cb373e6fad9 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -3,6 +3,9 @@
  * Copyright 2016 - 2018 Xilinx, Inc.
  */
 
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
 #include <linux/build_bug.h>
 
 enum tcm_mode {
@@ -13,3 +16,16 @@ enum tcm_mode {
 void initialize_tcm(enum tcm_mode mode);
 void tcm_init(enum tcm_mode mode);
 void mem_map_fill(void);
+
+/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */
+u32 versal_pmc_multi_boot(void);
+/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */
+u32 versal_multi_boot_reg(void);
+/* Overridable bootmode decode: weak MMIO default, firmware override */
+u8 versal_get_bootmode(void);
+/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */
+u32 versal_bootmode_reg(void);
+/* EL3 clock/timer register setup, called from board_early_init_r() */
+void versal_timer_setup(void);
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c
index f65c231bdab..6cc6592b0fc 100644
--- a/arch/arm/mach-versal2/cpu.c
+++ b/arch/arm/mach-versal2/cpu.c
@@ -7,21 +7,29 @@
  */
 
 #include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <vsprintf.h>
 #include <asm/armv8/mmu.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <asm/system.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/cache.h>
 #include <dm/platdata.h>
+#include <linux/bitfield.h>
+#include <linux/string.h>
+#include "../../../board/xilinx/common/board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #if CONFIG_IS_ENABLED(PCIE_DW_AMD)
-#define VERSAL2_MEM_MAP_USED	6
+#define VERSAL2_MEM_MAP_USED	4
 #else
-#define VERSAL2_MEM_MAP_USED	5
+#define VERSAL2_MEM_MAP_USED	3
 #endif
 
 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
@@ -51,19 +59,6 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x600000000UL,
-		.phys = 0x600000000UL,
-		.size = 0x800000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xe00000000UL,
-		.phys = 0xe00000000UL,
-		.size = 0xf200000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 #if CONFIG_IS_ENABLED(PCIE_DW_AMD)
 	}, {
 		/* PCIe DBI (1 MB) and config space (255 MB) are contiguous */
@@ -140,6 +135,141 @@ u64 get_page_table_size(void)
 }
 #endif
 
+u32 versal2_multi_boot_reg(void)
+{
+	return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK;
+}
+
+u32 __weak versal2_pmc_multi_boot(void)
+{
+	return versal2_multi_boot_reg();
+}
+
+u8 __weak versal2_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg;
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+void versal2_timer_setup(void)
+{
+	u32 val;
+
+	debug("iou_switch ctrl div0 %x\n",
+	      readl(&crlapb_base->iou_switch_ctrl));
+
+	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+	       &crlapb_base->iou_switch_ctrl);
+
+	/* Global timer init - Program time stamp reference clk */
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+	writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+	debug("ref ctrl 0x%x\n",
+	      readl(&crlapb_base->timestamp_ref_ctrl));
+
+	/* Clear reset of timestamp reg */
+	writel(0, &crlapb_base->rst_timestamp);
+
+	/*
+	 * Program freq register in System counter and
+	 * enable system counter.
+	 */
+	writel(CONFIG_COUNTER_FREQUENCY,
+	       &iou_scntr_secure->base_frequency_id_register);
+
+	debug("counter val 0x%x\n",
+	      readl(&iou_scntr_secure->base_frequency_id_register));
+
+	writel(IOU_SCNTRS_CONTROL_EN,
+	       &iou_scntr_secure->counter_control_register);
+
+	debug("scntrs control 0x%x\n",
+	      readl(&iou_scntr_secure->counter_control_register));
+	debug("timer 0x%llx\n", get_ticks());
+	debug("timer 0x%llx\n", get_ticks());
+}
+
+static u32 platform_id, platform_version;
+
+char *soc_name_decode(void)
+{
+	char *name, *platform_name;
+
+	switch (platform_id) {
+	case VERSAL2_SPP:
+		platform_name = "spp";
+		break;
+	case VERSAL2_EMU:
+		platform_name = "emu";
+		break;
+	case VERSAL2_SPP_MMD:
+		platform_name = "spp-mmd";
+		break;
+	case VERSAL2_EMU_MMD:
+		platform_name = "emu-mmd";
+		break;
+	case VERSAL2_QEMU:
+		platform_name = "qemu";
+		break;
+	default:
+		return NULL;
+	}
+
+	/*
+	 * --rev.-el are 9 chars
+	 * max platform name is emu-mmd which is 7 chars
+	 * platform version number are 1+1
+	 * el is 1 char
+	 * Plus 1 char for NULL byte
+	 */
+	name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20);
+	if (!name)
+		return NULL;
+
+	sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD,
+		platform_name, platform_version / 10,
+		platform_version % 10, current_el());
+
+	return name;
+}
+
+bool soc_detection(void)
+{
+	u32 version, ps_version;
+
+	version = readl(PMC_TAP_VERSION);
+	platform_id = FIELD_GET(PLATFORM_MASK, version);
+	ps_version = FIELD_GET(PS_VERSION_MASK, version);
+
+	debug("idcode %x, version %x, usercode %x\n",
+	      readl(PMC_TAP_IDCODE), version,
+	      readl(PMC_TAP_USERCODE));
+
+	debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
+	      FIELD_GET(PMC_VERSION_MASK, version),
+	      ps_version,
+	      FIELD_GET(RTL_VERSION_MASK, version));
+
+	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
+
+	debug("Platform id: %d version: %d.%d\n", platform_id,
+	      platform_version / 10, platform_version % 10);
+
+	return true;
+}
+
 U_BOOT_DRVINFO(soc_amd_versal2) = {
 	.name = "soc_amd_versal2",
 };
diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h
index cee13488620..b8d12d1dd3b 100644
--- a/arch/arm/mach-versal2/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal2/include/mach/sys_proto.h
@@ -4,8 +4,22 @@
  * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
  */
 
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
 #include <linux/build_bug.h>
 #include <asm/armv8/mmu.h>
 
 void mem_map_fill(struct mm_region *bank_info, u32 num_banks);
 void fill_bd_mem_info(void);
+
+/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */
+u32 versal2_pmc_multi_boot(void);
+/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */
+u32 versal2_multi_boot_reg(void);
+/* Weak bootmode decode (MMIO default); a firmware/SCMI build may override */
+u8 versal2_get_bootmode(void);
+/* EL3 clock/timer register setup, called from board_early_init_r() */
+void versal2_timer_setup(void);
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 3dc47e5d48e..088cc962189 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -8,6 +8,7 @@
 #include <time.h>
 #include <linux/errno.h>
 #include <linux/types.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/armv8/mmu.h>
@@ -171,15 +172,19 @@ unsigned int zynqmp_get_silicon_version(void)
 	return ZYNQMP_CSU_VERSION_SILICON;
 }
 
-static int zynqmp_mmio_rawwrite(const u32 address,
-		      const u32 mask,
-		      const u32 value)
+int zynqmp_mmio_rawread(const u32 address, u32 *value)
+{
+	*value = readl((ulong)address);
+	return 0;
+}
+
+int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value)
 {
 	u32 data;
 	u32 value_local = value;
 	int ret;
 
-	ret = zynqmp_mmio_read(address, &data);
+	ret = zynqmp_mmio_rawread(address, &data);
 	if (ret)
 		return ret;
 
@@ -190,48 +195,44 @@ static int zynqmp_mmio_rawwrite(const u32 address,
 	return 0;
 }
 
-static int zynqmp_mmio_rawread(const u32 address, u32 *value)
+int __weak zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
 {
-	*value = readl((ulong)address);
-	return 0;
+	if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
+		return zynqmp_mmio_rawwrite(address, mask, value);
+
+	return -EINVAL;
 }
 
-int zynqmp_mmio_write(const u32 address,
-		      const u32 mask,
-		      const u32 value)
+int __weak zynqmp_mmio_read(const u32 address, u32 *value)
 {
+	if (!value)
+		return -EINVAL;
+
 	if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
-		return zynqmp_mmio_rawwrite(address, mask, value);
-#if defined(CONFIG_ZYNQMP_FIRMWARE)
-	else
-		return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
-					 value, 0, 0, 0, NULL);
-#endif
+		return zynqmp_mmio_rawread(address, value);
 
 	return -EINVAL;
 }
 
-int zynqmp_mmio_read(const u32 address, u32 *value)
+void zynqmp_timer_setup(void)
 {
-	u32 ret = -EINVAL;
+	u32 val;
 
-	if (!value)
-		return ret;
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 
-	if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
-		ret = zynqmp_mmio_rawread(address, value);
-	}
-#if defined(CONFIG_ZYNQMP_FIRMWARE)
-	else {
-		u32 ret_payload[PAYLOAD_ARG_CNT];
+	if (!val) {
+		val = readl(&crlapb_base->timestamp_ref_ctrl);
+		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+		writel(val, &crlapb_base->timestamp_ref_ctrl);
 
-		ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
-					0, 0, 0, ret_payload);
-		*value = ret_payload[1];
+		/* Program freq register in System counter */
+		writel(zynqmp_get_system_timer_freq(),
+		       &iou_scntr_secure->base_frequency_id_register);
+		/* And enable system counter */
+		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+		       &iou_scntr_secure->counter_control_register);
 	}
-#endif
-
-	return ret;
 }
 
 U_BOOT_DRVINFO(soc_xilinx_zynqmp) = {
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index b6a41df1da4..d2bb10ffcbb 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -54,5 +54,10 @@ void mem_map_fill(void);
 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
 void tcm_init(enum tcm_mode mode);
 #endif
+/* EL3 clock/timer register setup, called from board_early_init_r() */
+void zynqmp_timer_setup(void);
+/* Direct MMIO accessors (EL3/SPL or no-firmware path) */
+int zynqmp_mmio_rawread(const u32 address, u32 *value);
+int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value);
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */
author	Tom Rini <[email protected]>	2026-07-08 10:13:24 -0600
committer	Tom Rini <[email protected]>	2026-07-08 10:13:24 -0600
commit	913fedc816570c07bfc7f9c4046dc2a3a55e4099 (patch)
tree	203a77dffb82a220a95e088004ab0e553a995660 /arch
parent	ee5d46b45ec0c63f8f9dd1e816e0dac3452ccc3d (diff)
parent	34c89c840c33dd154746ebdc9bbf2e4f3614d292 (diff)