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authorCaleb Connolly <[email protected]>2025-04-10 10:52:38 +0200
committerCaleb Connolly <[email protected]>2025-04-11 15:30:21 +0200
commit91ba4976c05882f88232eaa4fc5eb9192701dbe3 (patch)
tree341bf8a6d14bfc2dfc306111538f999b93c426ea /arch
parent9c607005c51976b5e0301461bfc0f38d5bdebd0e (diff)
pinctrl: qcom: handle reserved ranges
Some Qualcomm boards feature reserved ranges of pins which are protected by firmware. Attempting to read or write any registers associated with these pins results the board resetting. Add support for parsing these ranges from devicetree and ensure that the pinctrl and GPIO drivers don't try to interact with these pins. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Sumit Garg <[email protected]> Link: https://lore.kernel.org/r/20250410-topic-sm8x50-pinctrl-reserved-ranges-v2-1-654488392b9a@linaro.org Signed-off-by: Caleb Connolly <[email protected]>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-snapdragon/include/mach/gpio.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
index cc8f405e20b..11e8104baf2 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -46,4 +46,19 @@ static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsig
return pindata->special_pins_start && pin >= pindata->special_pins_start;
}
+struct udevice;
+
+/**
+ * msm_pinctrl_is_reserved() - Check if a pin lies in a reserved range
+ *
+ * @dev: pinctrl device
+ * @pin: Pin number
+ *
+ * Returns: true if pin is reserved, otherwise false
+ *
+ * Call using dev_get_parent() from the GPIO device, it is a child of
+ * the pinctrl device.
+ */
+bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin);
+
#endif /* _QCOM_GPIO_H_ */