diff options
| author | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
| commit | 93f84ee022a8401421cdaab84fe7d106d83fdb4a (patch) | |
| tree | fb15a4af876e8faf9893fd86c1c0e127265dbe9a /arch | |
| parent | 88dc2788777babfd6322fa655df549a019aa1e69 (diff) | |
| parent | e2138cf1e6088f12ffa874e87cc8f4b198378635 (diff) | |
Merge branch 'next'
Diffstat (limited to 'arch')
315 files changed, 3538 insertions, 8337 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 4af0da2485f..4c4c070df87 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -190,6 +190,7 @@ config SANDBOX select HAVE_SETJMP select HAVE_INITJMP select ARCH_SUPPORTS_LTO + select AXI select BOARD_LATE_INIT select BZIP2 select CMD_POWEROFF if CMDLINE @@ -199,24 +200,37 @@ config SANDBOX select DM_GPIO select DM_I2C select DM_KEYBOARD + select DM_MAILBOX + select DM_RESET select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO select GZIP_COMPRESSED + select I2C select LZO select MMC select MTD select OF_BOARD_SETUP + select OF_CONTROL select PCI_ENDPOINT + select SANDBOX_RESET select SPI + select SERIAL select SUPPORT_OF_CONTROL select SUPPORT_BIG_ENDIAN select SUPPORT_LITTLE_ENDIAN - select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + select SYSRESET + select SYSRESET_CMD_RESET + select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF select SYS_CACHE_SHIFT_4 select IRQ select SUPPORT_EXTENSION_SCAN if CMDLINE select SUPPORT_ACPI + select TIMER + select SPL_TIMER if SPL + select TPL_TIMER if TPL + select VPL_TIMER if VPL imply BITREVERSE select BLOBLIST imply LTO @@ -240,7 +254,7 @@ config SANDBOX imply AVB_VERIFY imply LIBAVB imply CMD_AVB - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply SCP03 imply CMD_SCP03 imply UDP_FUNCTION_FASTBOOT @@ -250,7 +264,7 @@ config SANDBOX # Re-enable this when fully implemented # imply VIRTIO_BLK imply VIRTIO_NET - imply DM_SOUND + imply SOUND imply PCI_SANDBOX_EP imply PCH imply PHYLIB @@ -266,7 +280,6 @@ config SANDBOX imply PHY_FIXED imply DM_DSA imply CMD_EXTENSION - imply KEYBOARD imply PHYSMEM imply GENERATE_ACPI_TABLE imply BINMAN @@ -284,6 +297,7 @@ config SH config X86 bool "x86 architecture" + select AHCI select HAVE_SETJMP select SUPPORT_SPL select SUPPORT_TPL diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index b143392ee6c..91165a06a46 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -10,9 +10,6 @@ #include <irq_func.h> #include <log.h> #include <asm/cache.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; static int cleanup_before_linux(void) { @@ -53,17 +50,13 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) { ulong kernel_entry; unsigned int r0, r2; - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = images->ep; debug("## Transferring control to Linux (at address %08lx)...\n", kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + bootm_final(flag); if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { r0 = 2; @@ -75,7 +68,7 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) cleanup_before_linux(); - if (!fake) + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) board_jump_and_run(kernel_entry, r0, 0, r2); } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cd6a454fd60..03416c55265 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -30,7 +30,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M + default 200000000 if ARCH_SOCFPGA_AGILEX5 || ARCH_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -834,6 +834,9 @@ config ARCH_K3 imply DM_RNG if ARM64 imply TEE if ARM64 imply OPTEE if ARM64 + imply TPM if ARM64 && MMC + imply TPM2_FTPM_TEE if ARM64 && MMC + imply SUPPORT_EMMC_RPMB if ARM64 && MMC config ARCH_OMAP2PLUS bool "TI OMAP2+" @@ -1145,35 +1148,35 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R - select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_SOC64 - select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select ARCH_MISC_INIT if !ARCH_SOCFPGA_ARRIA10 + select ARM64 if ARCH_SOCFPGA_SOC64 + select CPU_V7A if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 select DM select DM_SERIAL select GPIO_EXTRA_HEADER - select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64 + select ENABLE_ARM_SOC_BOOT0_HOOK if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 + select LMB_ARCH_MEM_MAP if ARCH_SOCFPGA_SOC64 select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 - select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 - select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64 + select SPL_SEPARATE_BSS if ARCH_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if ARCH_SOCFPGA_SOC64 + select SPL_SOCFPGA_DT_REG if ARCH_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG select SUPPORT_SPL select SYS_NS16550 - select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYS_THUMB_BUILD if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 select SYSRESET - select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ - TARGET_SOCFPGA_SOC64 - select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 - select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 + select SYSRESET_SOCFPGA_SOC64 if !ARCH_SOCFPGA_AGILEX5 && \ + ARCH_SOCFPGA_SOC64 + select SYSRESET_PSCI if ARCH_SOCFPGA_AGILEX5 + select USE_BOOTFILE if SPL_ATF && ARCH_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY @@ -2154,7 +2157,6 @@ config TARGET_POMELO select SCSI_AHCI select AHCI_PCI select PCI - select DM_PCI select SCSI select DM_SERIAL imply CMD_PCI diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 27ffb450378..2c550439559 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -7,7 +7,6 @@ #include <command.h> #include <asm/system.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <asm/sections.h> #include <asm/io.h> #include <asm/arch/nexell.h> @@ -15,8 +14,6 @@ #include <asm/arch/tieoff.h> #include <cpu_func.h> -DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_ARCH_CPU_INIT #error must be define the macro "CONFIG_ARCH_CPU_INIT" #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 82ad3035308..d90e02ca4e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,17 +58,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3128) += \ dtb-$(CONFIG_ROCKCHIP_RK322X) += \ rk3229-evb.dtb -dtb-$(CONFIG_ROCKCHIP_RK3288) += \ - rk3288-evb.dtb \ - rk3288-popmetal.dtb \ - rk3288-rock2-square.dtb \ - rk3288-rock-pi-n8.dtb \ - rk3288-veyron-jerry.dtb \ - rk3288-veyron-mickey.dtb \ - rk3288-veyron-minnie.dtb \ - rk3288-veyron-speedy.dtb \ - rk3288-vyasa.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ @@ -469,6 +458,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_cyclone5_ac501soc.dtb \ + socfpga_cyclone5_ac550soc.dtb \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi index c5e24c76457..4548076b96a 100644 --- a/arch/arm/dts/an7581-u-boot.dtsi +++ b/arch/arm/dts/an7581-u-boot.dtsi @@ -35,6 +35,48 @@ reg = <0x0 0x1fa20000 0x0 0x388>; }; + pon_pcs: pcs@1fa08000 { + compatible = "airoha,an7581-pcs-pon"; + reg = <0x0 0x1fa08000 0x0 0x1000>, + <0x0 0x1fa80000 0x0 0x60>, + <0x0 0x1fa80a00 0x0 0x164>, + <0x0 0x1fa84000 0x0 0x450>, + <0x0 0x1fa85900 0x0 0x338>, + <0x0 0x1fa86000 0x0 0x300>, + <0x0 0x1fa8a000 0x0 0x1000>, + <0x0 0x1fa8b000 0x0 0x1000>; + reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "xfi_ana", "xfi_pma"; + + resets = <&scuclk EN7581_XPON_MAC_RST>, + <&scuclk EN7581_XPON_PHY_RST>; + reset-names = "mac", "phy"; + + airoha,scu = <&scuclk>; + }; + + eth_pcs: pcs@1fa09000 { + compatible = "airoha,an7581-pcs-eth"; + reg = <0x0 0x1fa09000 0x0 0x1000>, + <0x0 0x1fa70000 0x0 0x60>, + <0x0 0x1fa70a00 0x0 0x164>, + <0x0 0x1fa74000 0x0 0x450>, + <0x0 0x1fa75900 0x0 0x338>, + <0x0 0x1fa76000 0x0 0x300>, + <0x0 0x1fa7a000 0x0 0x1000>, + <0x0 0x1fa7b000 0x0 0x1000>; + reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "xfi_ana", "xfi_pma"; + + resets = <&scuclk EN7581_XSI_MAC_RST>, + <&scuclk EN7581_XSI_PHY_RST>; + reset-names = "mac", "phy"; + + airoha,scu = <&scuclk>; + }; + eth: ethernet@1fb50000 { compatible = "airoha,en7581-eth"; reg = <0 0x1fb50000 0 0x2600>, @@ -52,6 +94,35 @@ reset-names = "fe", "pdma", "qdma", "hsi0-mac", "hsi1-mac", "hsi-mac", "xfp-mac"; + + gdm1: ethernet@1 { + compatible = "airoha,eth-mac"; + reg = <1>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gdm2: ethernet@2 { + compatible = "airoha,eth-mac"; + reg = <2>; + pcs = <&pon_pcs>; + + status = "disabled"; + }; + + gdm4: ethernet@4 { + compatible = "airoha,eth-mac"; + reg = <4>; + pcs = <ð_pcs>; + + status = "disabled"; + }; }; switch: switch@1fb58000 { diff --git a/arch/arm/dts/cros-ec-sbs.dtsi b/arch/arm/dts/cros-ec-sbs.dtsi deleted file mode 100644 index 71f5c5ecce4..00000000000 --- a/arch/arm/dts/cros-ec-sbs.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Smart battery dts fragment for devices that use cros-ec-sbs - * - * Copyright (c) 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&i2c_tunnel { - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; -}; diff --git a/arch/arm/dts/en7523-evb-u-boot.dtsi b/arch/arm/dts/en7523-evb-u-boot.dtsi index c109d6794fb..d6ab621d590 100644 --- a/arch/arm/dts/en7523-evb-u-boot.dtsi +++ b/arch/arm/dts/en7523-evb-u-boot.dtsi @@ -9,3 +9,7 @@ }; #include "en7523-u-boot.dtsi" + +&gdm1 { + status = "okay"; +}; diff --git a/arch/arm/dts/en7523-u-boot.dtsi b/arch/arm/dts/en7523-u-boot.dtsi index 9eadaccc500..62d1a724678 100644 --- a/arch/arm/dts/en7523-u-boot.dtsi +++ b/arch/arm/dts/en7523-u-boot.dtsi @@ -37,6 +37,19 @@ <&scu EN7523_HSI_MAC_RST>; reset-names = "fe", "pdma", "qdma", "hsi0-mac", "hsi1-mac", "hsi-mac"; + + gdm1: ethernet@1 { + compatible = "airoha,eth-mac"; + reg = <1>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; }; switch: switch@1fb58000 { diff --git a/arch/arm/dts/en7581-evb-u-boot.dtsi b/arch/arm/dts/en7581-evb-u-boot.dtsi index ebd3b8b4958..9a02122fbfa 100644 --- a/arch/arm/dts/en7581-evb-u-boot.dtsi +++ b/arch/arm/dts/en7581-evb-u-boot.dtsi @@ -9,3 +9,21 @@ }; #include "an7581-u-boot.dtsi" + +&gdm1 { + status = "okay"; +}; + +&gdm2 { + status = "okay"; + + managed = "in-band-status"; + phy-mode = "10gbase-r"; +}; + +&gdm4 { + status = "okay"; + + managed = "in-band-status"; + phy-mode = "usxgmii"; +}; diff --git a/arch/arm/dts/imx23-olinuxino-u-boot.dtsi b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi index dee8433696f..3f2f117b953 100644 --- a/arch/arm/dts/imx23-olinuxino-u-boot.dtsi +++ b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi @@ -1,5 +1,20 @@ // SPDX-License-Identifier: GPL-2.0+ +/ { + leds { + user_led: user { + default-state = "on"; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&user_led>; + }; + }; +}; + &ssp0 { non-removable; }; diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts index 2f8597579f3..b40410b2b6f 100644 --- a/arch/arm/dts/imx8-capricorn-cxg3.dts +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -102,6 +102,26 @@ pinctrl-0 = <&pinctrl_gpio_keys>; muxcgrp: imx8qxp-som { + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 + + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 @@ -127,3 +147,27 @@ >; }; }; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rmii"; + + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/dts/imx8-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi index 3734a9d21f1..f640daa775f 100644 --- a/arch/arm/dts/imx8-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -63,41 +63,6 @@ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 - SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 - SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 - SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 - SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 - SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 - SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 - SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 - //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 - >; - }; - - pinctrl_fec2: fec2grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - - SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 - SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 - - SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ >; }; }; @@ -126,6 +91,7 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; + max-frequency = <52000000>; clock-frequency=<52000000>; no-1-8-v; bus-width = <8>; @@ -160,27 +126,3 @@ &fec1 { status ="disabled"; }; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rmii"; - - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi index cf2a87a9b90..13e1070c28e 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi @@ -22,6 +22,18 @@ bootph-pre-ram; }; +&pca9450 { + bootph-all; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + &pinctrl_uart2 { bootph-pre-ram; }; @@ -63,7 +75,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &i2c2 { @@ -118,3 +130,7 @@ phy-reset-duration = <15>; phy-reset-post-delay = <100>; }; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi index 1320f1540ed..f917b71be90 100644 --- a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -33,6 +33,18 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { bootph-pre-ram; }; @@ -78,11 +90,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pmic { - bootph-pre-ram; + bootph-all; }; /* USB1 Type-C */ @@ -120,6 +132,12 @@ &usdhc2 { bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 4804a204e92..e9403d9ea82 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -34,6 +34,18 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { bootph-pre-ram; }; @@ -83,11 +95,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pmic { - bootph-pre-ram; + bootph-all; }; &usb_dwc3_0 { @@ -96,6 +108,12 @@ &usdhc2 { bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 7b45a87450b..3b0af5bc0a0 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -70,7 +70,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; eeprom_module: eeprom@50 { compatible = "i2c-eeprom"; @@ -104,7 +104,7 @@ }; &pca9450 { - bootph-pre-ram; + bootph-all; }; &pinctrl_ctrl_sleep_moci { @@ -112,7 +112,11 @@ }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; }; &pinctrl_usdhc2_pwr_en { @@ -159,6 +163,12 @@ sd-uhs-ddr50; sd-uhs-sdr104; bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { @@ -173,3 +183,7 @@ &wdog1 { bootph-pre-ram; }; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; diff --git a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi new file mode 100644 index 00000000000..64ed7af9946 --- /dev/null +++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <[email protected]> + * + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc0", "mmc1", "ethernet"; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_default { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&wdog3 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi new file mode 100644 index 00000000000..5d788854de5 --- /dev/null +++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <[email protected]> + * + */ + +#include "imx91-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" + +/ { + /* + * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as + * reference, but does only make use of its SoM (phyCORE) contained + * periphery. + */ + model = "PHYTEC phyCORE-i.MX91"; +}; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 646b617949d..b80ce20e942 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -9,6 +9,7 @@ */ #include "imx93-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" / { /* @@ -17,224 +18,4 @@ * periphery. */ model = "PHYTEC phyCORE-i.MX93"; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog3>; - bootph-pre-ram; - bootph-some-ram; - }; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - }; - - bootstd { - bootph-verify; - compatible = "u-boot,boot-std"; - - filename-prefixes = "/", "/boot/"; - bootdev-order = "mmc0", "mmc1", "ethernet"; - - rauc { - compatible = "u-boot,distro-rauc"; - }; - - script { - compatible = "u-boot,script"; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&{/soc@0} { - bootph-all; - bootph-pre-ram; -}; - -&aips1 { - bootph-pre-ram; - bootph-all; -}; - -&aips2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&aips3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&iomuxc { - bootph-pre-ram; - bootph-some-ram; -}; - -®_usdhc2_vmmc { - u-boot,off-on-delay-us = <20000>; - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_lpi2c3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_pmic { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_reg_usdhc2_vmmc { - bootph-pre-ram; -}; - -&pinctrl_uart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_cd { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_default { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio4 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpuart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc2 { - bootph-pre-ram; - bootph-some-ram; - fsl,signal-voltage-switch-extra-delay-ms = <8>; -}; - -&lpi2c1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - - regulators { - bootph-pre-ram; - bootph-some-ram; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - }; -}; - -&s4muap { - bootph-pre-ram; - bootph-some-ram; - status = "okay"; -}; - -&clk { - bootph-all; - bootph-pre-ram; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; - /delete-property/ assigned-clock-parents; -}; - -&osc_32k { - bootph-all; - bootph-pre-ram; -}; - -&osc_24m { - bootph-all; - bootph-pre-ram; -}; - -&clk_ext1 { - bootph-all; - bootph-pre-ram; -}; - -&wdog3 { - bootph-all; - bootph-pre-ram; }; diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi index 528b3b02a3f..247a7ed6838 100644 --- a/arch/arm/dts/imx943-evk-u-boot.dtsi +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -157,6 +157,24 @@ status = "disabled"; }; +&xspi1 { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1>; + status = "okay"; + + mt35xu512aba: flash@0 { + bootph-pre-ram; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &scmi_iomuxc { pinctrl_emdio: emdiogrp { fsl,pins = < @@ -205,6 +223,22 @@ IMX94_PAD_GPIO_IO17__LPI2C3_SCL 0x40000b9e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe + IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe + IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe + IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe + IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe + IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe + IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe + IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe + IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe + IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe + IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe + >; + }; }; &pinctrl_reg_usdhc2_vmmc { diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi index 2b93ba9a38b..3457442a3b0 100644 --- a/arch/arm/dts/imx943-u-boot.dtsi +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -141,6 +141,22 @@ &aips3 { bootph-all; + + xspi1: spi@42b90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx94-xspi"; + reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>; + reg-names = "xspi_base", "xspi_mmap"; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, // EENV0 + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, // EENV1 + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, // EENV2 + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, // EENV3 + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; // EENV4 + clocks = <&scmi_clk IMX94_CLK_XSPI1>; + clock-names = "xspi"; + status = "disabled"; + }; }; &clk_ext1 { diff --git a/arch/arm/dts/imx95-toradex-smarc-dev.dts b/arch/arm/dts/imx95-toradex-smarc-dev.dts deleted file mode 100644 index 5b05f256fd5..00000000000 --- a/arch/arm/dts/imx95-toradex-smarc-dev.dts +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 - * https://www.toradex.com/products/carrier-board/smarc-development-board-kit - */ - -/dts-v1/; - -#include <dt-bindings/pwm/pwm.h> -#include "imx95-toradex-smarc.dtsi" - -/ { - model = "Toradex SMARC iMX95 on Toradex SMARC Development Board"; - compatible = "toradex,smarc-imx95-dev", - "toradex,smarc-imx95", - "fsl,imx95"; - - reg_carrier_1p8v: regulator-carrier-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-carrier 1V8"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "tdx-smarc-wm8904"; - simple-audio-card,routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Microphone Jack", "MICBIAS", - "IN1L", "Microphone Jack"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - - codec_dai: simple-audio-card,codec { - clocks = <&scmi_clk IMX95_CLK_SAI3>; - sound-dai = <&wm8904_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - }; -}; - -/* SMARC GBE0 */ -&enetc_port0 { - status = "okay"; -}; - -/* SMARC GBE1 */ -&enetc_port1 { - status = "okay"; -}; - -/* SMARC CAN0 */ -&flexcan1 { - status = "okay"; -}; - -/* SMARC CAN1 */ -&flexcan2 { - status = "okay"; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio12>, <&pinctrl_gpio13>; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio10>, <&pinctrl_gpio11>; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio2>, - <&pinctrl_gpio3>, - <&pinctrl_gpio4>, - <&pinctrl_gpio6>, - <&pinctrl_gpio8>, - <&pinctrl_gpio9>; -}; - -/* SMARC I2C_CAM0 */ -&i2c_cam0 { - status = "okay"; -}; - -/* SMARC I2C_CAM1 */ -&i2c_cam1 { - status = "okay"; -}; - -/* SMARC I2C_GP */ -&lpi2c2 { - status = "okay"; - - wm8904_1a: audio-codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_sai3_mclk>; - #sound-dai-cells = <0>; - clocks = <&scmi_clk IMX95_CLK_SAI3>; - clock-names = "mclk"; - AVDD-supply = <®_carrier_1p8v>; - CPVDD-supply = <®_carrier_1p8v>; - DBVDD-supply = <®_carrier_1p8v>; - DCVDD-supply = <®_carrier_1p8v>; - MICVDD-supply = <®_carrier_1p8v>; - }; - - temperature-sensor@4f { - compatible = "ti,tmp1075"; - reg = <0x4f>; - }; - - eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; - -}; - -/* SMARC I2C_PM */ -&lpi2c3 { - clock-frequency = <100000>; - status = "okay"; - - fan_controller: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #pwm-cells = <2>; - - fan { - cooling-levels = <255>; - pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; - }; - }; - - /* Current measurement into module VCC */ - hwmon@40 { - compatible = "ti,ina226"; - reg = <0x40>; - shunt-resistor = <5000>; - }; -}; - -/* SMARC I2C_LCD */ -&lpi2c5 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - i2c-mux-idle-disconnect; - #address-cells = <1>; - #size-cells = <0>; - - /* I2C on DSI Connector Pins 4/6 */ - i2c_dsi_0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* I2C on DSI Connector Pins 52/54 */ - i2c_dsi_1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* SMARC SPI0 */ -&lpspi6 { - status = "okay"; -}; - -/* SMARC SER1, used as the Linux Console */ -&lpuart1 { - status = "okay"; -}; - -/* SMARC SER0, RS485 */ -&lpuart2 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* SMARC SER3, RS232 */ -&lpuart3 { - status = "okay"; -}; - -/* SMARC MDIO, shared between all ethernet ports */ -&netc_emdio { - status = "okay"; - - ethphy3: ethernet-phy@4 { - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio7>; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* SMARC PCIE_A / M2 Key B */ -&pcie0 { - status = "okay"; -}; - -/* SMARC PCIE_B / M2 Key E */ -&pcie1 { - status = "okay"; -}; - -/* SMARC I2S0 */ -&sai3 { - status = "okay"; -}; - -/* SMARC LCD0_BKLT_PWM */ -&tpm3 { - status = "okay"; -}; - -/* SMARC LCD1_BKLT_PWM */ -&tpm4 { - status = "okay"; -}; - -/* SMARC GPIO5 as PWM */ -&tpm5 { - status = "okay"; -}; - -/* SMARC USB0 */ -&usb2 { - status = "okay"; -}; - -/* SMARC USB1..4 */ -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -/* SMARC SDIO */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx95-toradex-smarc.dtsi b/arch/arm/dts/imx95-toradex-smarc.dtsi deleted file mode 100644 index e99f1a57af8..00000000000 --- a/arch/arm/dts/imx95-toradex-smarc.dtsi +++ /dev/null @@ -1,1153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "imx95.dtsi" - -/ { - aliases { - can0 = &flexcan1; - can1 = &flexcan2; - ethernet0 = &enetc_port0; - ethernet1 = &enetc_port1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - rtc0 = &rtc_i2c; - rtc1 = &scmi_bbm; - serial0 = &lpuart2; - serial1 = &lpuart1; - serial3 = &lpuart3; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - clk_dsi2dp_bridge: clock-dsi2dp-bridge { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - clk_serdes_eth_ref: clock-eth-ref { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - /* CTRL_ETH_REF_CLK_STBY# */ - enable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>; - }; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - /* SMARC P64 - USB0_OTG_ID */ - id-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; - label = "USB0"; - self-powered; - type = "micro"; - vbus-supply = <®_usb0_vbus>; - - port { - usb_dr_connector: endpoint { - remote-endpoint = <&usb0_otg_id>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - smarc_key_sleep: key-sleep { - gpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>; - label = "SMARC_SLEEP#"; - wakeup-source; - linux,code = <KEY_SLEEP>; - }; - - smarc_switch_lid: switch-lid { - gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; - label = "SMARC_LID#"; - linux,code = <SW_LID>; - linux,input-type = <EV_SW>; - }; - }; - - reg_module_1p8v: regulator-module-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8"; - }; - - /* Non PMIC On-module Supplies */ - reg_module_dp_1p2v: regulator-module-dp-1p2v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1200000>; - regulator-min-microvolt = <1200000>; - regulator-name = "On-module +V1.2_DP"; - vin-supply = <®_module_1p8v>; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - /* SMARC P62 - USB0_EN_OC# */ - gpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "USB0_EN_OC#"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - /* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */ - gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "CTRL_V_BUS_USB_HUB"; - }; - - reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - enable-active-high; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "SDIO_PWR_EN"; - startup-delay-us = <20000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vsel>; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - states = <1800000 0x1>, - <3300000 0x0>; - regulator-name = "PMIC_SD2_VSEL"; - }; - - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - /* CTRL_EN_WIFI */ - gpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "CTRL_EN_WIFI"; - startup-delay-us = <2000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux_cma: linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x3c000000>; - alloc-ranges = <0 0x80000000 0 0x7F000000>; - linux,cma-default; - }; - }; -}; - -/* SMARC GBE0 */ -&enetc_port0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>; - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -/* SMARC GBE1 */ -&enetc_port1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>; - phy-handle = <ðphy2>; - phy-mode = "rgmii-id"; -}; - -/* SMARC CAN0 */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -/* SMARC CAN1 */ -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&gpio1 { - gpio-line-names = "", /* 0 */ - "", - "SMARC_I2C_GP_CK", - "SMARC_I2C_GP_DAT", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "CTRL_IO_EXP_INT_B"; - status = "okay"; -}; - -&gpio2 { - gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */ - "", - "", - "", - "", - "", - "SMARC_GPIO5", - "", - "I2C_CAM_DAT", - "I2C_CAM_CK", - "SMARC_GPIO12", /* 10 */ - "SMARC_GPIO13", - "", - "", - "", - "", - "", - "", - "SMARC_SPI1_CS0#", - "", - "", /* 20 */ - "", - "SMARC_I2C_LCD_DAT", - "SMARC_I2C_LCD_CK", - "SMARC_SPI0_CS1#", - "", - "", - "", - "SMARC_I2C_PM_DAT", - "SMARC_I2C_PM_CK", - "I2C_SOM_DAT", /* 30 */ - "I2C_SOM_CK"; - status = "okay"; -}; - -&gpio3 { - gpio-line-names = "SMARC_SDIO_CD#", /* 0 */ - "", - "", - "", - "", - "", - "", - "SMARC_SDIO_PWR_EN", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "PMIC_SD2_VSEL"; - status = "okay"; -}; - -&gpio4 { - gpio-line-names = "", /* 0 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "SMARC_GPIO11", - "SMARC_GPIO10", - "", - "", - "", - "", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "SMARC_SMB_ALERT#"; - status = "okay"; -}; - -&gpio5 { - gpio-line-names = "SMARC_GPIO2", /* 0 */ - "SMARC_GPIO3", - "SMARC_GPIO4", - "SMARC_GPIO6", - "", - "", - "", - "", - "SMARC_GPIO9", - "SMARC_GPIO7", - "SMARC_GPIO8", /* 10 */ - "SMARC_SPI1_CS1#", - "", - "SPI1_TPM_CS#"; - status = "okay"; -}; - -/* SMARC I2C_GP */ -&lpi2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-1 = <&pinctrl_lpi2c2_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@50 { - compatible = "st,24c32", "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -/* SMARC I2C_PM */ -&lpi2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-1 = <&pinctrl_lpi2c3_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* I2C_SOM */ -&lpi2c4 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>; - pinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - som_gpio_expander_0: gpio@20 { - compatible = "nxp,pcal6408"; - reg = <0x20>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_PCIE_WAKE#", /* 0 */ - "SMARC_PCIE_B_RST#", - "SMARC_PCIE_A_RST#", - "SMARC_USB0_OTG_ID", - "SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */ - "SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */ - "", - "SMARC_PCIE_C_RST#"; - }; - - som_gpio_expander_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_GPIO0", /* 0 */ - "SMARC_GPIO1", - "SMARC_LCD0_VDD_EN", - "SMARC_LCD0_BKLT_EN", - "SMARC_LCD1_VDD_EN", - "SMARC_LCD1_BKLT_EN", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "SMARC_SDIO_WP"; - }; - - embedded-controller@28 { - compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; - reg = <0x28>; - }; - - som_ec_gpio_expander: gpio@29 { - compatible = "toradex,ecgpiol16", "nxp,pcal6416"; - reg = <0x29>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ec_int>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_CHARGER_PRSNT#", - "SMARC_CHARGING#", - "SMARC_LID#", - "SMARC_BATLOW#", - "SMARC_SLEEP#"; - }; - - /* SMARC DP0 */ - som_dsi2dp_bridge: bridge@2c { - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - clocks = <&clk_dsi2dp_bridge>; - clock-names = "refclk"; - vcc-supply = <®_module_dp_1p2v>; - vcca-supply = <®_module_dp_1p2v>; - vccio-supply = <®_module_1p8v>; - vpll-supply = <®_module_1p8v>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - data-lanes = <3 2 1 0>; - }; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - temperature-sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* SMARC I2C_LCD */ -&lpi2c5 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c5>; - pinctrl-1 = <&pinctrl_lpi2c5_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* I2C_CAM */ -&lpi2c7 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c7>; - pinctrl-1 = <&pinctrl_lpi2c7_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - /* SMARC I2C_CAM0 */ - i2c_cam0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* SMARC I2C_CAM1 */ - i2c_cam1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* SMARC SPI1 */ -&lpspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi4>; - cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, - <&gpio5 11 GPIO_ACTIVE_LOW>, - <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - som_tpm: tpm@2 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0x2>; - spi-max-frequency = <18500000>; - }; -}; - -/* SMARC SPI0 */ -&lpspi6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi6>; - cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, - <&gpio2 24 GPIO_ACTIVE_LOW>; -}; - -/* SMARC SER1, used as the Linux Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -/* SMARC SER0 */ -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* SMARC SER3 */ -&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -/* SMARC MDIO, shared between all ethernet ports */ -&netc_emdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emdio>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&som_gpio_expander_1>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; -}; - -&netcmix_blk_ctrl { - status = "okay"; -}; - -&netc_blk_ctrl { - status = "okay"; -}; - -&netc_timer { - status = "okay"; -}; - -/* SMARC PCIE_A */ -&pcie0 { - pinctrl-0 = <&pinctrl_pcie0>; - pinctrl-names = "default"; - reset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>; -}; - -/* SMARC PCIE_B */ -&pcie1 { - pinctrl-0 = <&pinctrl_pcie1>; - pinctrl-names = "default"; - reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; -}; - -/* SMARC I2S0 */ -&sai3 { - #sound-dai-cells = <0>; - assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>, - <&scmi_clk IMX95_CLK_AUDIOPLL2>, - <&scmi_clk IMX95_CLK_SAI3>; - assigned-clock-parents = <0>, <0>, <0>, <0>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>; - assigned-clock-rates = <3932160000>, - <3612672000>, <393216000>, - <361267200>, <12288000>; - fsl,sai-mclk-direction-output; -}; - -&thermal_zones { - /* PF09 Main PMIC */ - pf09-thermal { - polling-delay = <2000>; - polling-delay-passive = <250>; - thermal-sensors = <&scmi_sensor 2>; - - trips { - trip0 { - hysteresis = <2000>; - temperature = <155000>; - type = "critical"; - }; - }; - }; - - /* PF53 VDD_ARM PMIC */ - pf53-arm-thermal { - polling-delay = <2000>; - polling-delay-passive = <250>; - thermal-sensors = <&scmi_sensor 4>; - - trips { - trip0 { - hysteresis = <2000>; - temperature = <155000>; - type = "critical"; - }; - }; - }; - - /* PF53 VDD_SOC PMIC */ - pf53-soc-thermal { - polling-delay = <2000>; - polling-delay-passive = <250>; - thermal-sensors = <&scmi_sensor 3>; - - trips { - trip0 { - hysteresis = <2000>; - temperature = <155000>; - type = "critical"; - }; - }; - }; -}; - -/* SMARC LCD0_BKLT_PWM */ -&tpm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_bklt_pwm>; -}; - -/* SMARC LCD1_BKLT_PWM */ -&tpm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_bklt_pwm>; -}; - -/* SMARC GPIO5 as PWM */ -&tpm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5_pwm>; -}; - -/* SMARC USB0 */ -&usb2 { - adp-disable; - dr_mode = "otg"; - hnp-disable; - srp-disable; - usb-role-switch; - vbus-supply = <®_usb0_vbus>; - - port { - usb0_otg_id: endpoint { - remote-endpoint = <&usb_dr_connector>; - }; - }; -}; - -&usb3 { - fsl,disable-port-power-control; -}; - -/* SMARC USB1..4 */ -&usb3_dwc3 { - dr_mode = "host"; -}; - -&usb3_phy { - vbus-supply = <®_usb1_vbus>; -}; - -/* On-module eMMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -/* SMARC SDIO */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - wp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>; -}; - -/* On-module Wi-Fi */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - keep-power-in-suspend; - non-removable; - vmmc-supply = <®_wifi_en>; -}; - -&scmi_bbm { - linux,code = <KEY_POWER>; -}; - -&wdog3 { - fsl,ext-reset-output; - status = "okay"; -}; - -&scmi_iomuxc { - /* SMARC CAM_MCK */ - pinctrl_cam_mck: cammckgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SMARC S6 - CAM_MCK */ - }; - - pinctrl_ec_int: ecintgrp { - fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x31e>; /* SAI1_TXFS - EC_MCU_INT# */ - }; - - /* SMARC MDIO, shared between all ethernet ports */ - pinctrl_emdio: emdiogrp { - fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* SMARC S45 - MDIO_CLK */ - <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* SMARC S46 - MDIO_DAT */ - }; - - /* SMARC GBE0 */ - pinctrl_enetc0: enetc0grp { - fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ - <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ - <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ - <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ - <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ - <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ - <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ - <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ - <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ - <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ - <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ - <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ - }; - - /* SMARC GBE0_SDP */ - pinctrl_enetc0_1588_tmr: enetc01588tmrgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x51e>; /* SMARC P6 - GBE0_SDP */ - }; - - /* SMARC GBE1 */ - pinctrl_enetc1: enetc1grp { - fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ - <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ - <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ - <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ - <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ - <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ - <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ - <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ - <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ - <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ - <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ - <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ - }; - - /* SMARC GBE1_SDP */ - pinctrl_enetc1_1588_tmr: enetc11588tmrgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x51e>; /* SMARC P5 - GBE1_SDP */ - }; - - /* SMARC CAN0 */ - pinctrl_flexcan1: flexcan1grp { - fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SMARC P143 - CAN0_TX */ - <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SMARC P144 - CAN0_RX */ - }; - - /* SMARC CAN1 */ - pinctrl_flexcan2: flexcan2grp { - fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SMARC P145 - CAN1_TX */ - <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SMARC P146 - CAN1_RX */ - }; - - /* SMARC GPIO2 */ - pinctrl_gpio2: gpio2grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x31e>; /* SMARC P110 - GPIO2 */ - }; - - /* SMARC GPIO3 */ - pinctrl_gpio3: gpio3grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x31e>; /* SMARC P111 - GPIO3 */ - }; - - /* SMARC GPIO4 */ - pinctrl_gpio4: gpio4grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x31e>; /* SMARC P112 - GPIO4 */ - }; - - /* SMARC GPIO5 */ - pinctrl_gpio5: gpio5grp { - fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x31e>; /* SMARC P113 - GPIO5 */ - }; - - /* SMARC GPIO5 as PWM */ - pinctrl_gpio5_pwm: gpio5pwmgrp { - fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SMARC P113 - PWM_OUT */ - }; - - /* SMARC GPIO6 */ - pinctrl_gpio6: gpio6grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e>; /* SMARC P114 - GPIO6 */ - }; - - /* SMARC GPIO7 */ - pinctrl_gpio7: gpio7grp { - fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */ - }; - - /* SMARC GPIO8 */ - pinctrl_gpio8: gpio8grp { - fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x31e>; /* SMARC P116 - GPIO8 */ - }; - - /* SMARC GPIO9 */ - pinctrl_gpio9: gpio9grp { - fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e>; /* SMARC P117 - GPIO9 */ - }; - - /* SMARC GPIO10 */ - pinctrl_gpio10: gpio10grp { - fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x31e>; /* SMARC P118 - GPIO10 */ - }; - - /* SMARC GPIO11 */ - pinctrl_gpio11: gpio11grp { - fsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x31e>; /* SMARC P119 - GPIO11 */ - }; - - /* SMARC GPIO12 */ - pinctrl_gpio12: gpio12grp { - fsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e>; /* SMARC S142 - GPIO12 */ - }; - - /* SMARC GPIO13 */ - pinctrl_gpio13: gpio13grp { - fsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>; /* SMARC S123 - GPIO13 */ - }; - - pinctrl_ctrl_io_exp_int_b: ioexpintgrp { - fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */ - }; - - /* SMARC LCD0_BKLT_PWM */ - pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp { - fsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */ - }; - - /* SMARC LCD1_BKLT_PWM */ - pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp { - fsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2 0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */ - }; - - /* SMARC I2C_GP */ - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ - <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ - }; - - /* SMARC I2C_GP as GPIOs */ - pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { - fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ - <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ - }; - - /* SMARC I2C_PM */ - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ - <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ - }; - - /* SMARC I2C_PM as GPIOs */ - pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ - <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ - }; - - /* I2C_SOM */ - pinctrl_lpi2c4: lpi2c4grp { - fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* I2C_SOM_CK */ - <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* I2C_SOM_DAT */ - }; - - /* I2C_SOM as GPIOs */ - pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* I2C_SOM_CK */ - <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* I2C_SOM_DAT */ - }; - - /* SMARC I2C_LCD */ - pinctrl_lpi2c5: lpi2c5grp { - fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ - <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ - }; - - /* SMARC I2C_LCD as GPIOs */ - pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ - <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ - }; - - /* I2C_CAM */ - pinctrl_lpi2c7: lpi2c7grp { - fsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40001b9e>, /* I2C_CAM_DAT */ - <IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40001b9e>; /* I2C_CAM_CK */ - }; - - /* I2C_CAM as GPIOs */ - pinctrl_lpi2c7_gpio: lpi2c7gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x40001b9e>, /* I2C_CAM_DAT */ - <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x40001b9e>; /* I2C_CAM_CK */ - }; - - /* SMARC SPI1 */ - pinctrl_lpspi4: lpspi4grp { - fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe>, /* SMARC P56 - SPI1_CK */ - <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe>, /* SMARC P58 - SPI1_DO */ - <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* SMARC P57 - SPI1_DIN */ - <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x3fe>, /* SPI1_TPM_CS# */ - <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* SMARC P54 - SPI1_CS0# */ - <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>; /* SMARC P55 - SPI1_CS1# */ - }; - - /* SMARC SPI0 */ - pinctrl_lpspi6: lpspi6grp { - fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* SMARC P43 - SPI0_CS0# */ - <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x3fe>, /* SMARC P31 - SPI0_CS1# */ - <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SMARC P45 - SPI0_DIN */ - <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SMARC P46 - SPI0_DO */ - <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SMARC P44 - SPI0_CK */ - }; - - /* SMARC PCIE_A */ - pinctrl_pcie0: pcie0grp { - fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */ - }; - - /* SMARC PCIE_B */ - pinctrl_pcie1: pcie1grp { - fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */ - }; - - /* SMARC I2S0 */ - pinctrl_sai3: sai3grp { - fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SMARC S38 - I2S0_CK */ - <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SMARC S41 - I2S0_SDIN */ - <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SMARC S40 - I2S0_SDOUT */ - <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SMARC S39 - I2S0_LRCK */ - }; - - /* SMARC AUDIO_MCK */ - pinctrl_sai3_mclk: sai3mclkgrp { - fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SMARC S42 - AUDIO_MCK */ - }; - - /* SMARC I2S2 */ - pinctrl_sai5: sai5grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SMARC S53 - I2S2_CK */ - <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SMARC S51 - I2S2_SDOUT */ - <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>, /* SMARC S52 - I2S2_SDIN */ - <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>; /* SMARC S50 - I2S2_LRCK */ - }; - - /* SMARC SMB_ALERT# */ - pinctrl_smb_alert_gpio: smbalertgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>; /* SMARC P1 - SMB_ALERT# */ - }; - - /* SMARC SER1, used as the Linux Console */ - pinctrl_uart1: uart1grp { - fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* SMARC P134 - SER1_TX */ - <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* SMARC P135 - SER1_RX */ - }; - - /* SMARC SER0 */ - pinctrl_uart2: uart2grp { - fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x31e>, /* SMARC P132 - SER0_CTS# */ - <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x31e>, /* SMARC P131 - SER0_RTS# */ - <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SMARC P130 - SER0_RX */ - <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SMARC P129 - SER0_TX */ - }; - - /* SMARC SER3 */ - pinctrl_uart3: uart3grp { - fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* SMARC P140 - SER3_TX */ - <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */ - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ - <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ - <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ - <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ - <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ - <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ - <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ - <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ - <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ - <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ - <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ - <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ - <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ - <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ - <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ - <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ - <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ - <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ - <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ - <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ - <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SMARC P36 - SDIO_CK */ - <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SMARC P34 - SDIO_CMD */ - <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SMARC P39 - SDIO_D0 */ - <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SMARC P40 - SDIO_D1 */ - <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SMARC P41 - SDIO_D2 */ - <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SMARC P36 - SDIO_CK */ - <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SMARC P34 - SDIO_CMD */ - <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SMARC P39 - SDIO_D0 */ - <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SMARC P40 - SDIO_D1 */ - <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SMARC P41 - SDIO_D2 */ - <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2_sleep: usdhc2-sleepgrp { - fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SMARC P36 - SDIO_CK */ - <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SMARC P34 - SDIO_CMD */ - <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SMARC P39 - SDIO_D0 */ - <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SMARC P40 - SDIO_D1 */ - <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SMARC P41 - SDIO_D2 */ - <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO_CD# */ - pinctrl_usdhc2_cd: usdhc2-cdgrp { - fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SMARC P35 - SDIO_CD# */ - }; - - /* SMARC SDIO_PWR_EN */ - pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { - fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SMARC P37 - SDIO_PWR_EN */ - }; - - pinctrl_usdhc2_vsel: usdhc2-vselgrp { - fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ - <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ - <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ - <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ - <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ - <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ - <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ - <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ - <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ - <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ - <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ - }; -}; diff --git a/arch/arm/dts/imx952-evk-u-boot.dtsi b/arch/arm/dts/imx952-evk-u-boot.dtsi new file mode 100644 index 00000000000..b872c3a7273 --- /dev/null +++ b/arch/arm/dts/imx952-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "imx952-u-boot.dtsi" + +&wdog3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi new file mode 100644 index 00000000000..e977014992e --- /dev/null +++ b/arch/arm/dts/imx952-u-boot.dtsi @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +/ { + binman { + multiple-images; + + m33-oei-ddrfw { + pad-byte = <0x00>; + align-size = <0x8>; + filename = "m33-oei-ddrfw.bin"; + + oei-m33-ddr { + align-size = <0x4>; + filename = "oei-m33-ddr.bin"; + type = "blob-ext"; + }; + + imx-lpddr { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem { + filename = "lpddr4x_imem_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem { + filename = "lpddr4x_dmem_v202409.bin"; + type = "blob-ext"; + }; + }; + + imx-lpddr-qb { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem-qb { + filename = "lpddr4x_imem_qb_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem-qb { + filename = "lpddr4x_dmem_qb_v202409.bin"; + type = "blob-ext"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + type = "nxp-imx9image"; + cfg-path = "spl/u-boot-spl.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + append = "mx952a0-ahab-container.img"; + container; + dummy-ddr; + image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; + hold = <0x10000>; + image1 = "m33", "m33_image.bin", "0x1ffc0000"; + image2 = "a55", "spl/u-boot-spl.bin", "0x20480000"; + dummy-v2x = <0x8b000000>; + }; + + u-boot { + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "u-boot.bin", "0x90200000"; + }; + }; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + }; +}; + +&A55_0 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_1 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_2 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_3 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&aips1 { + bootph-all; +}; + +&aips2 { + bootph-all; +}; + +&aips3 { + bootph-all; +}; + +&clk_ext1 { + bootph-all; +}; + +&clk_dummy { + bootph-all; +}; + +&clk_osc_24m { + bootph-all; +}; + +&elemu1 { + status = "okay"; + bootph-all; +}; + +&elemu3 { + status = "okay"; + bootph-all; +}; + +&{/firmware} { + bootph-all; +}; + +&{/firmware/scmi} { + bootph-all; +}; + +&{/firmware/scmi/protocol@11} { + bootph-all; +}; + +&{/firmware/scmi/protocol@13} { + bootph-all; +}; + +&{/firmware/scmi/protocol@14} { + bootph-all; +}; + +&{/firmware/scmi/protocol@15} { + bootph-all; +}; + +&{/firmware/scmi/protocol@19} { + bootph-all; +}; + +&gpio1 { + reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; +}; + +&gpio2 { + reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>; + bootph-pre-ram; + /* + * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2 + * is assigned to M7, disable gpio2 here + */ + status = "disabled"; +}; + +&gpio3 { + reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>; + bootph-pre-ram; +}; + +&gpio4 { + reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>; + bootph-pre-ram; +}; + +&gpio5 { + reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>; + bootph-pre-ram; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&mu2 { + bootph-all; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&scmi_buf0 { + reg = <0x0 0x400>; + bootph-all; +}; + +&scmi_buf1 { + bootph-all; +}; + +&{/soc} { + bootph-all; +}; + +&sram0 { + bootph-all; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&scmi_iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + bootph-pre-ram; + + fsl,pins = < + IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x3fe + IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e + IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x3fe + IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x3fe + >; + }; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 46b621242b5..ac6f1022a55 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -21,11 +21,6 @@ }; }; -&a53_0 { - clock-names = "gtc"; - clocks = <&k3_clks 61 0>; -}; - &main_pktdma { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 8d6015e44a9..ba29a047406 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -7,6 +7,10 @@ #ifdef CONFIG_TARGET_AM625_R5_EVM +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62x-hs-evm.bin { filename = "tiboot3-am62x-hs-evm.bin"; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index dfd960aaf3c..971bb752052 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -24,7 +24,6 @@ }; &a53_0 { - clocks = <&k3_clks 61 0>; /* * FIXME: Currently only the SPL running on the R5 has a clock * driver. As a workaround therefore move the assigned-clock diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index b54cd9d48a4..c949485017e 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -22,11 +22,6 @@ }; }; -&a53_0 { - clocks = <&k3_clks 61 0>; - clock-names = "gtc"; -}; - &cbass_main { bootph-pre-ram; sa3_secproxy: secproxy@44880000 { diff --git a/arch/arm/dts/k3-am62d2-r5.dtsi b/arch/arm/dts/k3-am62d2-r5.dtsi index 23dfc49c2ea..4a58711bfbc 100644 --- a/arch/arm/dts/k3-am62d2-r5.dtsi +++ b/arch/arm/dts/k3-am62d2-r5.dtsi @@ -73,3 +73,21 @@ clock-frequency = <25000000>; bootph-pre-ram; }; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 603487341d2..cca56b76d69 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -7,6 +7,10 @@ #if IS_ENABLED(CONFIG_TARGET_AM62P5_R5_EVM) +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62px-hs-fs-evm.bin { filename = "tiboot3-am62px-hs-fs-evm.bin"; diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts index 4b7a63db4ce..6f3a2628353 100644 --- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts @@ -21,8 +21,3 @@ ethernet0 = &cpsw3g; }; }; - -&a53_0 { - clock-names = "gtc"; - clocks = <&k3_clks 61 0>; -}; diff --git a/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts b/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts index a2674a3e1f8..c641a2b59d6 100644 --- a/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts +++ b/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts @@ -14,6 +14,15 @@ #include "k3-am68-phyboard-izar-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" +&pmic { + bootph-pre-ram; + + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; +}; + &wkup_vtm0 { bootph-pre-ram; vdd-supply-2 = <&vdd_cpu_avs>; diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 0fd93f9536a..ad127663d03 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -477,7 +477,7 @@ FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD)>; start_address = <0x0 CONFIG_K3_ATF_LOAD_ADDR>; - end_address = <0x0 (CONFIG_K3_ATF_LOAD_ADDR + 0x1ffff)>; + end_address = <0x0 (CONFIG_K3_ATF_LOAD_ADDR + CONFIG_K3_ATF_RESERVED_SIZE - 1)>; }; firewall_armv8_optee_fg: template-8 { control = <(FWCTRL_EN | FWCTRL_LOCK | @@ -486,7 +486,7 @@ FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD)>; start_address = <0x0 CONFIG_K3_OPTEE_LOAD_ADDR>; - end_address = <0x0 (CONFIG_K3_OPTEE_LOAD_ADDR + 0x17fffff)>; + end_address = <0x0 (CONFIG_K3_OPTEE_LOAD_ADDR + CONFIG_K3_OPTEE_RESERVED_SIZE - 1)>; }; ti_falcon_template: template-9 { diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 54eb9b4072c..8d51fea72b8 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -107,10 +107,6 @@ }; }; -&ospi1 { - status = "disabled"; -}; - &usbss0 { bootph-all; }; diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index c1c12e217d2..7d4a6dc5301 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -90,6 +90,11 @@ <0x0 0x50000000 0x0 0x8000000>; }; +&ospi1 { + reg = <0x0 0x47050000 0x0 0x100>, + <0x0 0x58000000 0x0 0x8000000>; +}; + &fss { /* fss node has 64 bit address regions mapped to it and since the ospi * nodes is being override, override the fss node ranges as well diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 2d89fa08b4d..d75a4e4be87 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -37,7 +37,7 @@ }; }; - snfi: snfi@1100d000 { + snfi: spi@1100d000 { compatible = "mediatek,mtk-snfi-spi"; reg = <0x1100d000 0x2000>; clocks = <&pericfg CLK_PERI_NFI_PD>, @@ -53,7 +53,7 @@ #size-cells = <0>; }; - snor: snor@11014000 { + snor: spi@11014000 { compatible = "mediatek,mtk-snor"; reg = <0x11014000 0x1000>; clocks = <&pericfg CLK_PERI_FLASH_PD>, @@ -86,7 +86,7 @@ clock-names = "system-clk"; }; - infracfg: infracfg@10000000 { + infracfg: clock-controller@10000000 { compatible = "mediatek,mt7622-infracfg", "syscon"; reg = <0x10000000 0x1000>; @@ -94,13 +94,13 @@ #reset-cells = <1>; }; - pericfg: pericfg@10002000 { + pericfg: clock-controller@10002000 { compatible = "mediatek,mt7622-pericfg", "syscon"; reg = <0x10002000 0x1000>; #clock-cells = <1>; }; - scpsys: scpsys@10006000 { + scpsys: power-controller@10006000 { compatible = "mediatek,mt7622-scpsys", "syscon"; #power-domain-cells = <1>; @@ -122,13 +122,13 @@ interrupt-parent = <&gic>; }; - apmixedsys: apmixedsys@10209000 { + apmixedsys: clock-controller@10209000 { compatible = "mediatek,mt7622-apmixedsys"; reg = <0x10209000 0x1000>; #clock-cells = <1>; }; - topckgen: topckgen@10210000 { + topckgen: clock-controller@10210000 { compatible = "mediatek,mt7622-topckgen"; reg = <0x10210000 0x1000>; #clock-cells = <1>; @@ -198,7 +198,7 @@ status = "disabled"; }; - ssusbsys: ssusbsys@1a000000 { + ssusbsys: clock-controller@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon"; reg = <0x1a000000 0x1000>; @@ -206,7 +206,7 @@ #reset-cells = <1>; }; - pciesys: pciesys@1a100800 { + pciesys: clock-controller@1a100800 { compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0x1a100800 0x1000>; #clock-cells = <1>; @@ -364,7 +364,7 @@ }; }; - ethsys: syscon@1b000000 { + ethsys: clock-controller@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>; #clock-cells = <1>; @@ -399,7 +399,7 @@ status = "disabled"; }; - sgmiisys: sgmiisys@1b128000 { + sgmiisys: syscon@1b128000 { compatible = "mediatek,mt7622-sgmiisys", "syscon"; reg = <0x1b128000 0x3000>; #clock-cells = <1>; @@ -424,7 +424,7 @@ status = "disabled"; }; - soft_i2c: soft_i2c@0 { + soft_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi index 686ed2cd5de..686ed2cd5de 100644 --- a/arch/arm/dts/rk3288-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts deleted file mode 100644 index bb24a96cddf..00000000000 --- a/arch/arm/dts/rk3288-evb.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - model = "Evb-RK3288"; - compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi deleted file mode 100644 index 0e347beb154..00000000000 --- a/arch/arm/dts/rk3288-evb.dtsi +++ /dev/null @@ -1,476 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - button@0 { - gpio-key,wakeup = <1>; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = <116>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_sys>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <50>; - pwms = <&pwm0 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - pwm-delay-us = <10000>; - status = "disabled"; - }; - - panel: panel { - compatible = "simple-panel"; - power-supply = <&vcc_io>; - backlight = <&backlight>; - enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - status = "okay"; -}; - -&gmac { - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "vcca_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_tp: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_pmu: REG9 { - regulator-name = "vccio_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vcc_18>; - status = "disabled"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&mipi_dsi { - status = "disabled"; - rockchip,panel = <&panel>; - display-timings { - timing0 { - bits-per-pixel = <24>; - clock-frequency = <160000000>; - hfront-porch = <120>; - hsync-len = <20>; - hback-porch = <21>; - hactive = <1200>; - vfront-porch = <21>; - vsync-len = <3>; - vback-porch = <18>; - vactive = <1920>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts deleted file mode 100644 index 736dc51e261..00000000000 --- a/arch/arm/dts/rk3288-popmetal.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-popmetal.dtsi" - -/ { - model = "PopMetal-RK3288"; - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi deleted file mode 100644 index ecff641b109..00000000000 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ /dev/null @@ -1,547 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/input/input.h> -#include "rk3288.dtsi" - -/ { - memory{ - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = <KEY_POWER>; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc18_dvp: vcc18-dvp-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc18-dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lan: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - ldo5: LDO_REG5 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ldo5"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_33: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vccio_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - ak8963: ak8963@0d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio8>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - }; - - l3g4200d: l3g4200d@68 { - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x6b>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio8>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - status = "okay"; -}; - -&pinctrl { - ak8963 { - comp_int: comp-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usb_host1 { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-rock-pi-n8.dts b/arch/arm/dts/rk3288-rock-pi-n8.dts deleted file mode 100644 index c9894a60e70..00000000000 --- a/arch/arm/dts/rk3288-rock-pi-n8.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -/dts-v1/; -#include "rk3288.dtsi" -#include <rockchip-radxa-dalang-carrier.dtsi> -#include "rk3288-vmarc-som.dtsi" - -/ { - model = "Radxa ROCK Pi N8"; - compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", - "rockchip,rk3288"; -}; diff --git a/arch/arm/dts/rk3288-rock2-som.dtsi b/arch/arm/dts/rk3288-rock2-som.dtsi deleted file mode 100644 index 58e32fbb80f..00000000000 --- a/arch/arm/dts/rk3288-rock2-som.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/pwm/pwm.h> -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - mmc-pwrseq = <&emmc_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vccio_pmu>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - rx_delay = <0x10>; - tx_delay = <0x30>; -}; - -&i2c0 { - status = "okay"; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - system-power-controller; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts deleted file mode 100644 index 41676696ba3..00000000000 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-rock2-som.dtsi" - -/ { - model = "Radxa Rock 2 Square"; - compatible = "radxa,rock2-square", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_usb_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - /* Always on as the rockchip usb phy doesn't have a vbus-supply - * property - */ - regulator-always-on; - regulator-name = "vcc_host"; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart2 { - status = "okay"; - reg-shift = <2>; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi deleted file mode 100644 index 143eaae26db..00000000000 --- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2014 Google, Inc - */ - -#include <dt-bindings/clock/rockchip,rk808.h> -#include <dt-bindings/input/input.h> -#include "rk3288-veyron.dtsi" - -/ { - aliases { - i2c20 = &i2c_tunnel; - video0 = &vopl; - video1 = &vopb; - }; - - gpio_keys: gpio-keys { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - lid { - label = "Lid"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - linux,code = <0>; /* SW_LID */ - linux,input-type = <5>; /* EV_SW */ - debounce-interval = <1>; - gpio-key,wakeup; - }; - }; - - gpio-charger { - compatible = "gpio-charger"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ac_present_ap>; - charger-type = "mains"; - }; - - /* A non-regulated voltage from power supply or battery */ - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc33_sys: vcc33-sys { - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - vin-supply = <&vccsys>; - }; - - /* This turns on vbus for host1 (dwc2) */ - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_pwren_h>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&rk808 { - regulators { - vcc33_ccd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_ccd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&spi0 { - status = "okay"; - spi-activate-delay = <100>; - spi-max-frequency = <3000000>; - spi-deactivate-delay = <200>; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - ec-interrupt = <&gpio7 7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_int>; - reg = <0>; - google,cros-ec-spi-pre-delay = <30>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c4 { - trackpad@15 { - compatible = "elan,i2c_touchpad"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int>; - reg = <0x15>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&pinctrl { - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - buttons { - ap_lid_int_l: ap-lid-int-l { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - charger { - ac_present_ap: ac-present-ap { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - cros-ec { - ec_int: ec-int { - rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - suspend { - suspend_l_wake: suspend-l-wake { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>; - }; - - suspend_l_sleep: suspend-l-sleep { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - trackpad { - trackpad_int: trackpad-int { - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-host { - host1_pwr_en: host1-pwr-en { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbotg_pwren_h: usbotg-pwren-h { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts deleted file mode 100644 index 40fee55c750..00000000000 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron Jerry Rev 3+ board device tree source - * - * Copyright 2014 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jerry"; - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - sound { - compatible = "rockchip,audio-max98090-jerry"; - - cpu { - sound-dai = <&i2s 0>; - }; - - codec { - sound-dai = <&max98090 0>; - }; - }; -}; - -&gpio_keys { - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&panel { - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "mic_vcc"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&sdmmc { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; - disable-wp; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&edp { - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - emmc { - /* Make sure eMMC is not in reset */ - emmc_deassert_reset: emmc-deassert-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&i2c4 { - status = "okay"; - - /* - * Trackpad pin control is shared between Elan and Synaptics devices - * so we have to pull it up to the bus level. - */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer &trackpad_int>; - - trackpad@15 { - compatible = "elan,i2c_touchpad"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - /* - * Remove the inherited pinctrl settings to avoid clashing - * with bus-wide ones. - */ - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - reg = <0x15>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; - - trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts deleted file mode 100644 index 0521d9e0e9a..00000000000 --- a/arch/arm/dts/rk3288-veyron-mickey.dts +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Google Veyron Mickey Rev 0 board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" - -/ { - model = "Google Mickey"; - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - - vcc_5v: vcc-5v { - vin-supply = <&vcc33_sys>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - }; -}; - -&cpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - cpu_alert_almost_warm: cpu_alert_almost_warm { - temperature = <63000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_warm: cpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_almost_hot: cpu_alert_almost_hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hot: cpu_alert_hot { - temperature = <82000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hotter: cpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_very_hot: cpu_alert_very_hot { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * After 1st level, throttle the CPU down to as low as 1.4 GHz - * and don't let the GPU go faster than 400 MHz. Note that we - * won't throttle the GPU lower than 400 MHz due to CPU - * heat--we'll let the GPU do the rest itself. - */ - cpu_warm_limit_cpu { - trip = <&cpu_alert_warm>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 4>; - }; - - /* - * Add some discrete steps to help throttling system deal - * with the fact that there are two passive cooling devices: - * the CPU and the GPU. - * - * - 1.2 GHz - 1.0 GHz (almost hot) - * - 800 MHz (hot) - * - 800 MHz - 696 MHz (hotter) - * - 696 MHz - min (very hot) - * - * Note: - * - 800 MHz appears to be a "sweet spot" for me. I can run - * some pretty serious workload here and be happy. - * - After 696 MHz we stop lowering voltage, so throttling - * past there is less effective. - */ - cpu_almost_hot_limit_cpu { - trip = <&cpu_alert_almost_hot>; - cooling-device = - <&cpu0 5 6>; - }; - cpu_hot_limit_cpu { - trip = <&cpu_alert_hot>; - cooling-device = - <&cpu0 7 7>; - }; - cpu_hotter_limit_cpu { - trip = <&cpu_alert_hotter>; - cooling-device = - <&cpu0 7 8>; - }; - cpu_very_hot_limit_cpu { - trip = <&cpu_alert_very_hot>; - cooling-device = - <&cpu0 8 THERMAL_NO_LIMIT>; - }; - }; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&i2s { - status = "okay"; - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - /delete-property/ vcc12-supply; - - vcc11-supply = <&vcc33_sys>; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - /delete-node/ LDO_REG7; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&pinctrl { - hdmi { - power_hdmi_on: power-hdmi-on { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&sdmmc { - status = "disabled"; -}; - -&sdio0 { - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&spi0 { - status = "disabled"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host1 { - status = "disabled"; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&power_hdmi_on>; -}; diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts deleted file mode 100644 index b56a3f4f51a..00000000000 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Google Veyron Minnie Rev 0+ board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" - -/ { - model = "Google Minnie"; - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - sound { - compatible = "rockchip,audio-max98090-jerry"; - - cpu { - sound-dai = <&i2s 0>; - }; - - codec { - sound-dai = <&max98090 0>; - }; - }; -}; - -&backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = < - 0 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - power-supply = <&backlight_regulator>; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&gpio_keys { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>; - - volum_down { - label = "Volum_down"; - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <100>; - }; - - volum_up { - label = "Volum_up"; - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <100>; - }; -}; - -&i2c_tunnel { - battery: bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_touch>; - vccio-supply = <&vcc33_touch>; - }; -}; - -&panel { - compatible = "auo,b101ean01", "simple-panel"; - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - regulators { - vcc33_touch: LDO_REG2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v_touch: SWITCH_REG2 { - regulator-name = "vcc5v_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - volum_down_l: volum-down-l { - rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - volum_up_l: volum-up-l { - rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - prochot { - gpio_prochot: gpio-prochot { - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts deleted file mode 100644 index 58c1fe96eea..00000000000 --- a/arch/arm/dts/rk3288-veyron-speedy.dts +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Speedy Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" -#include "rk3288-veyron-speedy-u-boot.dtsi" - -/ { - model = "Google Speedy"; - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&panel { - power-supply = <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi deleted file mode 100644 index 99406151bf5..00000000000 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ /dev/null @@ -1,795 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2014 Google, Inc - */ - -#include <dt-bindings/clock/rockchip,rk808.h> -#include <dt-bindings/input/input.h> -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - chosen { - stdout-path = &uart2; - }; - - firmware { - chromeos { - pinctrl-names = "default"; - pinctrl-0 = <&fw_wp_ap>; - write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - backlight-boot-off; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 0>; - }; - - panel: panel { - compatible ="cnm,n116bgeea2","simple-panel"; - status = "okay"; - power-supply = <&vcc33_lcd>; - backlight = <&backlight>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_h>; - power { - label = "Power"; - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_POWER>; - debounce-interval = <100>; - gpio-key,wakeup; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_warm_reset_h>; - priority = /bits/ 8 <200>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "rockchip,rockchip-audio-max98090"; - rockchip,model = "ROCKCHIP-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&max98090>; - rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - rockchip,headset-codec = <&headsetcodec>; - pinctrl-names = "default"; - pinctrl-0 = <&mic_det>, <&hp_det>; - }; - - vdd_logic: pwm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 2000 0>; - - voltage-table = <1350000 0>, - <1300000 10>, - <1250000 20>, - <1200000 31>, - <1150000 41>, - <1100000 52>, - <1050000 62>, - <1000000 72>, - < 950000 83>; - - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_logic"; - regulator-ramp-delay = <4000>; - }; - - vcc33_sys: vcc33-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc33_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_5v>; - }; - - bt_regulator: bt-regulator { - /* - * On the module itself this is one of these (depending - * on the actual card pouplated): - * - BT_I2S_WS_BT_RFDISABLE_L - * - No connect - */ - - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_enable_l>; - regulator-name = "bt_regulator"; - }; - - wifi_regulator: wifi-regulator { - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - regulator-name = "wifi_regulator"; - - /* Faux input supply. See bt_regulator description. */ - vin-supply = <&bt_regulator>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&efuse { - status = "okay"; -}; - -&emmc { - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - cap-sdio-irq; - card-external-vcc-supply = <&wifi_regulator>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, - <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock"; - keep-power-in-suspend; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - status = "okay"; - vmmc-supply = <&vcc33_sys>; - vqmmc-supply = <&vcc18_wl>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - card-detect-delay = <200>; - cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - num-slots = <1>; - status = "okay"; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&spi2 { - status = "okay"; - - spi_flash: spiflash@0 { - compatible = "spidev", "jedec,spi-nor"; - spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - reg = <0x1b>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc33_sys>; - vcc2-supply = <&vcc33_sys>; - vcc3-supply = <&vcc33_sys>; - vcc4-supply = <&vcc33_sys>; - vcc6-supply = <&vcc_5v>; - vcc7-supply = <&vcc33_sys>; - vcc8-supply = <&vcc33_sys>; - vcc9-supply = <&vcc_5v>; - vcc10-supply = <&vcc33_sys>; - vcc11-supply = <&vcc_5v>; - vcc12-supply = <&vcc_18>; - - vddio-supply = <&vcc33_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd_arm"; - regulator-ramp-delay = <6001>; - regulator-suspend-mem-disabled; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <6001>; - regulator-suspend-mem-disabled; - }; - - vcc135_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc135_ddr"; - regulator-suspend-mem-enabled; - }; - - /* - * vcc_18 has several aliases. (vcc18_flashio and - * vcc18_wl). We'll add those aliases here just to - * make it easier to follow the schematic. The signals - * are actually hooked together and only separated for - * power measurement purposes). - */ - vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-suspend-mem-microvolt = <1800000>; - }; - - /* - * Note that both vcc33_io and vcc33_pmuio are always - * powered together. To simplify the logic in the dts - * we just refer to vcc33_io every time something is - * powered from vcc33_pmuio. In fact, on later boards - * (such as danger) they're the same net. - */ - vcc33_io: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_io"; - regulator-suspend-mem-microvolt = <3300000>; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-suspend-mem-microvolt = <1000000>; - }; - - vccio_sd: LDO_REG4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-suspend-mem-disabled; - }; - - vcc33_sd: LDO_REG5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_sd"; - regulator-suspend-mem-disabled; - }; - - vcc18_codec: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_codec"; - regulator-suspend-mem-disabled; - }; - - vdd10_lcd_pwren_h: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd10_lcd_pwren_h"; - regulator-suspend-mem-disabled; - }; - - vcc33_lcd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lcd"; - regulator-suspend-mem-disabled; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 40ns measured */ - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&i2c2 { - status = "okay"; - - /* 100kHz since 4.7k resistors don't rise fast enough */ - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <50>; /* 10ns measured */ - i2c-scl-rising-time-ns = <800>; /* 600ns measured */ - - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - #sound-dai-cells = <0>; - interrupt-parent = <&gpio6>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&int_codec>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 11ns measured */ - i2c-scl-rising-time-ns = <300>; /* 225ns measured */ - - headsetcodec: ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ts3a227e_int_l>; - ti,micbias = <7>; /* MICBIAS = 2.8V */ - }; -}; - -&i2c5 { - status = "okay"; - - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <300>; - i2c-scl-rising-time-ns = <1000>; -}; - -&i2s { - status = "okay"; - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; -}; - -&io_domains { - audio-supply = <&vcc18_codec>; - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc18_wl>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - - /* Pins don't include flow control by default; add that in */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - reg-shift = <2>; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&edp { - status = "okay"; - rockchip,panel = <&panel>; -}; - -&hdmi { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&tsadc { - tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &bt_dev_wake_sleep - >; - - /* Add this for sdmmc pins to SD card */ - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwr_key_h: pwr-key-h { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - codec { - hp_det: hp-det { - rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - int_codec: int-codec { - rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - mic_det: mic-det { - rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - }; - - headset { - ts3a227e_int_l: ts3a227e-int-l { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - /* - * Causes jerry to hang when probing bus 0 - * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; - */ - }; - }; - - reboot { - ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio0 { - wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* NOTE: mislabelled on schematic; should be bt_enable_h */ - bt_enable_l: bt-enable-l { - rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run sdio0 at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * These pins are only present on very new veyron boards; on - * older boards bt_dev_wake is simply always high. Note that - * gpio4_26 is a NC on old veyron boards, so it doesn't hurt - * to map this pin everywhere - */ - bt_dev_wake_sleep: bt-dev-wake-sleep { - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>; - }; - - bt_dev_wake_awake: bt-dev-wake-awake { - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * Builtin CD line is hooked to ground to prevent JTAG at boot - * (and also to get the voltage rail correct). Make we - * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't - * think there's a card inserted - */ - sdmmc_cd_disabled: sdmmc-cd-disabled { - rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD */ - sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tpm { - tpm_int_h: tpm-int-h { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - write-protect { - fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; - needs-reset-on-resume; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&cru SCLK_OTGPHY0>; -}; diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi deleted file mode 100644 index 793951655b7..00000000000 --- a/arch/arm/dts/rk3288-vmarc-som.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> - -/ { - compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; - - vccio_flash: vccio-flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_codec: LDO_REG2 { - regulator-name = "vcca_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_wl: LDO_REG4 { - regulator-name = "vcc_wl"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-name = "vcc_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio5>; - interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - bb-supply = <&vcc_io>; - flash0-supply = <&vccio_flash>; - gpio1830-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_wl>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - }; - - vbus_host { - usb1_en_oc: usb1-en-oc { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - vbus_typec { - usb0_en_oc: usb0-en-oc { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdio_pwrseq { - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vbus_host { - enable-active-high; - gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ -}; - -&vbus_typec { - enable-active-high; - gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ -}; diff --git a/arch/arm/dts/rk3288-vyasa.dts b/arch/arm/dts/rk3288-vyasa.dts deleted file mode 100644 index 4193f7208cd..00000000000 --- a/arch/arm/dts/rk3288-vyasa.dts +++ /dev/null @@ -1,473 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Jagan Teki <[email protected]> - */ - -/dts-v1/; -#include "rk3288.dtsi" - -/ { - model = "Amarula Vyasa-RK3288"; - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - dc12_vbat: dc12-vbat { - compatible = "regulator-fixed"; - regulator-name = "dc12_vbat"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vboot_3v3: vboot-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vboot_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vboot_5v: vboot-5v { - compatible = "regulator-fixed"; - regulator-name = "vboot_sv"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - v3g_3v3: v3g-3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3g_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vsus_5v: vsus-5v { - compatible = "regulator-fixed"; - regulator-name = "vsus_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - enable-active-high; - gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - vusb1_5v: vusb1-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb1_5v"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - vusb2_5v: vusb2-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb2_5v"; - enable-active-high; - gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_codec: LDO_REG2 { - regulator-name = "vcc_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_gps: LDO_REG4 { - regulator-name = "vcc_gps"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&phy_pwr_en>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb_host { - phy_pwr_en: phy-pwr-en { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - }; -}; diff --git a/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi b/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi new file mode 100644 index 00000000000..3e2fbd81da1 --- /dev/null +++ b/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index dc3771b556a..018c9cc8d69 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -118,13 +118,11 @@ &sdhci { bootph-pre-ram; bootph-some-ram; - u-boot,spl-fifo-mode; }; &sdmmc { bootph-pre-ram; bootph-some-ram; - u-boot,spl-fifo-mode; }; &sdmmc0_bus4 { @@ -154,12 +152,10 @@ &sfc0 { bootph-some-ram; - u-boot,spl-sfc-no-dma; }; &sfc1 { bootph-some-ram; - u-boot,spl-sfc-no-dma; }; &sys_grf { diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 6740f9866f1..04144e2ad12 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled + * Minimal generic DT for RK3582/RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled */ /dts-v1/; #include "rk3588s.dtsi" / { - model = "Generic RK3588S/RK3588"; + model = "Generic RK3582/RK3588S/RK3588"; compatible = "rockchip,rk3588"; aliases { diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi deleted file mode 100644 index da1d548b733..00000000000 --- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include <dt-bindings/pwm/pwm.h> - -/ { - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vbus_host: vbus-host { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_en_oc>; - regulator-name = "vbus_host"; /* HOST-5V */ - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_en_oc>; - regulator-name = "vbus_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&gmac { - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 71d7623fe2c..4ba6a87e78a 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -246,16 +246,18 @@ pad-byte = <0x00>; u-boot-spl { - no-write-symbols; }; + payload { + type = "section"; + align = <CONFIG_SYS_CACHELINE_SIZE>; #ifdef HAS_FIT fit { insert-template = <&fit_template>; #else u-boot-img { #endif - offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>; + }; }; }; #endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */ diff --git a/arch/arm/dts/sc594-som-ezkit.dts b/arch/arm/dts/sc594-som-ezkit.dts index afc16df577a..dea9a6e27f2 100644 --- a/arch/arm/dts/sc594-som-ezkit.dts +++ b/arch/arm/dts/sc594-som-ezkit.dts @@ -22,7 +22,7 @@ eeprom { gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; + gpios = <0 GPIO_ACTIVE_LOW>; output-low; line-name = "eeprom-en"; bootph-pre-ram; @@ -30,7 +30,7 @@ pushbutton { gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; + gpios = <1 GPIO_ACTIVE_LOW>; output-low; line-name = "pushbutton-en"; bootph-pre-ram; @@ -70,7 +70,7 @@ octal { gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; + gpios = <8 GPIO_ACTIVE_LOW>; output-low; line-name = "octal-spi-cs-en"; bootph-pre-ram; diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi index fc168317c9e..fe16037fc20 100644 --- a/arch/arm/dts/smbios_generic.dtsi +++ b/arch/arm/dts/smbios_generic.dtsi @@ -77,6 +77,18 @@ SMBIOS_CACHE_OP_WB)>; }; }; + + system-slot { + }; + + memory-array { + }; + + memory-device { + }; + + memory-array-mapped-address { + }; }; }; }; diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi index 695242bec21..ddef9a2896d 100644 --- a/arch/arm/dts/socfpga-common-u-boot.dtsi +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2019 Simon Goldschmidt */ /{ - memory { + memory@0 { bootph-all; }; diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 770f6cad292..c0f932d0e11 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -264,7 +264,7 @@ }; #endif -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M &sdr { compatible = "intel,sdr-ctl-agilex7m"; reg = <0xf8020000 0x100>; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 5a7aa5841e3..c03f78b2fdf 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -110,26 +110,49 @@ status = "okay"; no-mmc; - no-1-8-v; disable-wp; cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; vmmc-supply = <&sd_emmc_power>; vqmmc-supply = <&sd_io_1v8_reg>; max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0000c800>; + sdhci-caps-mask = <0x00002000 0x0000ff00>; /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; - cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; /* SD card high speed and UHS-I SDR25 mode timing configuration */ cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; - cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + /* SD card UHS-I SDR50 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>; + + /* SD card UHS-I SDR104 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + bootph-all; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts index f6848c373cd..c06781064ca 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts @@ -25,11 +25,14 @@ disable-wp; non-removable; cap-mmc-highspeed; - + mmc-hs200-1_8v; + mmc-hs400-1_8v; bus-width = <8>; vmmc-supply = <&sd_emmc_power>; vqmmc-supply = <&emmc_io_1v8_reg>; max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0004c800>; /* SDHCI_CAN_DO_8BIT */ + sdhci-caps-mask = <0x00000000 0x0000ff00>; /* eMMC legacy mode timing configuration */ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; @@ -46,4 +49,26 @@ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>; cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>; + + /* eMMC HS200 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-dq-timing-delay-emmc-hs200 = <0x10000001>; + cdns,phy-dll-master-ctrl-emmc-hs200 = <0x4>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + + /* eMMC HS400 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-hs400 = <0x680004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400 = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-hs400 = <0x4d4b40>; + cdns,phy-dq-timing-delay-emmc-hs400 = <0x10000001>; + cdns,phy-dll-master-ctrl-emmc-hs400 = <0x4>; + cdns,ctrl-hrs09-timing-delay-emmc-hs400 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>; + cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6f2fe7bf746..f2150b7eb7b 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -8,7 +8,7 @@ #include "socfpga_agilex-u-boot.dtsi" -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX /{ chosen { stdout-path = "serial0:115200n8"; @@ -27,7 +27,7 @@ }; #endif -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M /{ model = "SoCFPGA Agilex7-M SoCDK"; chosen { @@ -181,3 +181,41 @@ }; }; }; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&fdt_0_blob { + filename = "dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dtb"; +}; + +&images { + fdt-1 { + description = "socfpga_socdk_nand"; + type = "flat_dt"; + compression = "none"; + fdt_1_blob: blob-ext { + filename = "dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dtb"; + }; + hash { + algo = "crc32"; + }; + }; +}; + +&board_config { + board-1 { + description = "board_1"; + firmware = "atf"; + loadables = "uboot"; + fdt = "fdt-1"; + signature { + algo = "crc32"; + key-name-hint = "dev"; + sign-images = "atf", "uboot", "fdt-1"; + }; + }; +}; + +&binman { + /delete-node/ kernel; +}; +#endif diff --git a/arch/arm/dts/socfpga_arria5_secu1.dts b/arch/arm/dts/socfpga_arria5_secu1.dts index 8e9c3bbdf9d..dfc04cc2d7a 100644 --- a/arch/arm/dts/socfpga_arria5_secu1.dts +++ b/arch/arm/dts/socfpga_arria5_secu1.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x20000000>; /* 512MB */ diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi new file mode 100644 index 00000000000..8d2caf69dd1 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi" + +/{ + aliases { + udc0 = &usb1; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + bootph-all; +}; + +&uart0 { + clock-frequency = <100000000>; + bootph-all; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc.dts b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts new file mode 100644 index 00000000000..6b02fa63c7c --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025, Brian Sune + * + * based on socfpga_cyclone5_socdk.dts + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "CoreCourse AC501SoC"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi new file mode 100644 index 00000000000..8d2caf69dd1 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi" + +/{ + aliases { + udc0 = &usb1; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + bootph-all; +}; + +&uart0 { + clock-frequency = <100000000>; + bootph-all; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc.dts b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts new file mode 100644 index 00000000000..cc841e85560 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025, Brian Sune + * + * based on socfpga_cyclone5_socdk.dts + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "CoreCourse AC550SoC,AC802-CVA6"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 6 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&porta 9 1>; + }; + }; + + buttons { + compatible = "gpio-keys"; + hps0 { + label = "HPS GPIO0"; + gpios = <&porta 0 0>; + }; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <100000>; + + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index ca030c8c41b..094db1cb7d4 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -20,7 +20,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index 34886ec1ad8..346b2ef9e2d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -22,7 +22,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts index b38f0723823..37203b63410 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts @@ -22,7 +22,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index e9de72429f2..264ca3dd53f 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -20,7 +20,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 58a5faf6ea2..b26248b023e 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x10000000>; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 93a8e0697d6..88f0154463d 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -28,7 +28,7 @@ os = "U-Boot"; arch = "arm64"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x80200000>; #else load = <0x00200000>; @@ -47,7 +47,7 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x80000000>; entry = <0x80000000>; #else @@ -106,7 +106,7 @@ arch = "arm64"; os = "linux"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x86000000>; entry = <0x86000000>; #else diff --git a/arch/arm/dts/tegra114-asus-tf701t.dts b/arch/arm/dts/tegra114-asus-tf701t.dts index 2505b9bb726..bd43a80a208 100644 --- a/arch/arm/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/dts/tegra114-asus-tf701t.dts @@ -1151,7 +1151,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; @@ -1165,7 +1165,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index 18bcb75fafa..48708f37246 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000400"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; }; @@ -57,13 +57,13 @@ spi-max-frequency = <25000000>; }; - sdhci@78000400 { + mmc@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; bus-width = <4>; status = "okay"; }; - sdhci@78000600 { + mmc@78000600 { bus-width = <8>; status = "okay"; non-removable; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi index f8f71262538..f735f5060ce 100644 --- a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi +++ b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi @@ -35,7 +35,7 @@ compatible = "samsung,ltl106hl02-001"; reg = <0>; - vdd-supply = <&tps65090_fet4>; + power-supply = <&tps65090_fet4>; backlight = <&backlight>; }; @@ -814,7 +814,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; @@ -827,7 +827,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra114-nvidia-tegratab.dts b/arch/arm/dts/tegra114-nvidia-tegratab.dts index f65772a8e01..6ff2850b911 100644 --- a/arch/arm/dts/tegra114-nvidia-tegratab.dts +++ b/arch/arm/dts/tegra114-nvidia-tegratab.dts @@ -953,7 +953,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; @@ -967,7 +967,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 250d692f6bf..0a783fbc95d 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -631,7 +631,7 @@ #nvidia,mipi-calibrate-cells = <1>; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -641,7 +641,7 @@ status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -651,7 +651,7 @@ status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -661,7 +661,7 @@ status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts index 08184ab3ac2..5ac08037a92 100644 --- a/arch/arm/dts/tegra124-apalis.dts +++ b/arch/arm/dts/tegra124-apalis.dts @@ -54,9 +54,9 @@ i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; - mmc2 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; + mmc2 = "/mmc@700b0400"; rtc0 = "/i2c@7000c000/rtc@68"; rtc1 = "/i2c@7000d000/pmic@40"; rtc2 = "/rtc@7000e000"; @@ -1958,7 +1958,7 @@ }; /* Apalis MMC1 */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; /* MMC1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; @@ -1967,7 +1967,7 @@ }; /* Apalis SD1 */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; /* SD1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; @@ -1976,7 +1976,7 @@ }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts b/arch/arm/dts/tegra124-cei-tk1-som.dts index e5b41f3183c..59901a3439b 100644 --- a/arch/arm/dts/tegra124-cei-tk1-som.dts +++ b/arch/arm/dts/tegra124-cei-tk1-som.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -297,7 +297,7 @@ }; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -305,7 +305,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; }; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 59e080a8af6..7d19a25e278 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -301,7 +301,7 @@ }; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -309,7 +309,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index f1c97052a84..b942d92e900 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -16,8 +16,8 @@ i2c5 = "/i2c@7000d100"; rtc0 = "/i2c@7000d000/pmic@40"; rtc1 = "/rtc@7000e000"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -59,7 +59,7 @@ ddc-i2c-bus = <&dpaux>; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 2b28fe14970..7b465c601af 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -370,7 +370,7 @@ reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - sdhci@700b0000 { /* WiFi/BT on this bus */ + mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; bus-width = <4>; @@ -382,7 +382,7 @@ keep-power-in-suspend; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -392,7 +392,7 @@ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { /* eMMC on this bus */ + mmc@700b0600 { /* eMMC on this bus */ status = "okay"; bus-width = <8>; no-1-8-v; diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts index 7e9c6aa1839..0e855d8bc30 100644 --- a/arch/arm/dts/tegra124-venice2.dts +++ b/arch/arm/dts/tegra124-venice2.dts @@ -17,8 +17,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -70,7 +70,7 @@ spi-max-frequency = <25000000>; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -78,7 +78,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts index 64386f2b7b7..09b5c1eea05 100644 --- a/arch/arm/dts/tegra124-xiaomi-mocha.dts +++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts @@ -476,7 +476,7 @@ }; }; - sdmmc3: sdhci@700b0400 { + sdmmc3: mmc@700b0400 { status = "okay"; bus-width = <4>; @@ -487,7 +487,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@700b0600 { + sdmmc4: mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index cac9b112302..1c62d1f6e7b 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -717,7 +717,7 @@ #phy-cells = <1>; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -727,7 +727,7 @@ status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -737,7 +737,7 @@ status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -747,7 +747,7 @@ status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/tegra186-p2771-0000-000.dts b/arch/arm/dts/tegra186-p2771-0000-000.dts index 84e850d6fca..39076058bfb 100644 --- a/arch/arm/dts/tegra186-p2771-0000-000.dts +++ b/arch/arm/dts/tegra186-p2771-0000-000.dts @@ -6,7 +6,7 @@ model = "NVIDIA P2771-0000-000"; compatible = "nvidia,p2771-0000-000", "nvidia,p2771-0000", "nvidia,tegra186"; - sdhci@3400000 { + mmc@3400000 { cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>; power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra186-p2771-0000-500.dts b/arch/arm/dts/tegra186-p2771-0000-500.dts index 1ac8ab431e9..cb36dae80e5 100644 --- a/arch/arm/dts/tegra186-p2771-0000-500.dts +++ b/arch/arm/dts/tegra186-p2771-0000-500.dts @@ -6,7 +6,7 @@ model = "NVIDIA P2771-0000-500"; compatible = "nvidia,p2771-0000-500", "nvidia,p2771-0000", "nvidia,tegra186"; - sdhci@3400000 { + mmc@3400000 { cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi index 7cda0b41f74..7bbf81fe2bf 100644 --- a/arch/arm/dts/tegra186-p2771-0000.dtsi +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -10,8 +10,8 @@ aliases { ethernet = "/ethernet@2490000"; - mmc0 = "/sdhci@3460000"; - mmc1 = "/sdhci@3400000"; + mmc0 = "/mmc@3460000"; + mmc1 = "/mmc@3400000"; i2c0 = "/bpmp/i2c"; i2c1 = "/i2c@3160000"; i2c2 = "/i2c@c240000"; @@ -48,13 +48,13 @@ status = "okay"; }; - sdhci@3400000 { + mmc@3400000 { status = "okay"; wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@3460000 { + mmc@3460000 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index edcb7aacb8e..0cabf608a9e 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -136,7 +136,7 @@ status = "disabled"; }; - sdhci@3400000 { + mmc@3400000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x200>; resets = <&bpmp TEGRA186_RESET_SDMMC1>; @@ -146,7 +146,7 @@ status = "disabled"; }; - sdhci@3460000 { + mmc@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; resets = <&bpmp TEGRA186_RESET_SDMMC4>; diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts index 4afde766330..d8d2d10a48a 100644 --- a/arch/arm/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -400,7 +400,7 @@ nvidia,xcvr-lsrslew = <2>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -412,7 +412,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-asus-transformer.dtsi b/arch/arm/dts/tegra20-asus-transformer.dtsi index df078a6fcdc..db6bed3e5d2 100644 --- a/arch/arm/dts/tegra20-asus-transformer.dtsi +++ b/arch/arm/dts/tegra20-asus-transformer.dtsi @@ -437,7 +437,7 @@ status = "okay"; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -449,7 +449,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index 11023968f41..776491a515e 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -14,7 +14,7 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; /* On-module only, for ASIX */ usb2 = "/usb@c5008000"; @@ -106,7 +106,7 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 7fe7d52096c..60cc7b32bb0 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -18,8 +18,8 @@ usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; usb2 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000200"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000200"; }; memory { @@ -645,7 +645,7 @@ status = "okay"; }; - sdhci@c8000200 { + mmc@c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -653,7 +653,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra20-lg-star.dts b/arch/arm/dts/tegra20-lg-star.dts index 083598b1b92..912c0b6051b 100644 --- a/arch/arm/dts/tegra20-lg-star.dts +++ b/arch/arm/dts/tegra20-lg-star.dts @@ -327,13 +327,7 @@ pmic: max8907@3c { compatible = "maxim,max8907"; reg = <0x3c>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; maxim,system-power-controller; @@ -419,7 +413,7 @@ vbus-supply = <&avdd_3v3_usb>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -429,7 +423,7 @@ vqmmc-supply = <&vdd_1v8_vio>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts index 1c79d757467..00e9272541a 100644 --- a/arch/arm/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi index db2cce1cc0d..b3c0e36340d 100644 --- a/arch/arm/dts/tegra20-motorola-mot.dtsi +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -330,7 +330,7 @@ backlight_led: led@0 { reg = <0>; - led-sources = <2>; + led-sources = <0>; led-max-microamp = <26600>; ti,led-mode = <0>; @@ -425,7 +425,7 @@ vbus-supply = <&avdd_3v3_periph>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -435,7 +435,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index f851767a55f..91799518412 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -19,8 +19,8 @@ usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; usb2 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000000"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000000"; }; memory { @@ -485,7 +485,7 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -493,7 +493,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts index 1b642be9928..8d8672da23d 100644 --- a/arch/arm/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-samsung-bose.dts b/arch/arm/dts/tegra20-samsung-bose.dts index 5bb9a33adf2..64cf8489707 100644 --- a/arch/arm/dts/tegra20-samsung-bose.dts +++ b/arch/arm/dts/tegra20-samsung-bose.dts @@ -92,7 +92,7 @@ }; }; - sdhci@c8000400 { + mmc@c8000400 { broken-cd; }; diff --git a/arch/arm/dts/tegra20-samsung-n1-common.dtsi b/arch/arm/dts/tegra20-samsung-n1-common.dtsi index 8223c5ece54..b82e6464248 100644 --- a/arch/arm/dts/tegra20-samsung-n1-common.dtsi +++ b/arch/arm/dts/tegra20-samsung-n1-common.dtsi @@ -319,13 +319,7 @@ pmic: max8907@3c { compatible = "maxim,max8907"; reg = <0x3c>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; maxim,system-power-controller; @@ -371,7 +365,7 @@ vbus-supply = <&usb_phy_reg>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -379,7 +373,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-samsung-n1.dts b/arch/arm/dts/tegra20-samsung-n1.dts index 930a3195aa0..82b337973b9 100644 --- a/arch/arm/dts/tegra20-samsung-n1.dts +++ b/arch/arm/dts/tegra20-samsung-n1.dts @@ -151,7 +151,7 @@ }; }; - sdhci@c8000400 { + mmc@c8000400 { /* battery blocks the sdcard slot and the device lacks CD pin */ non-removable; }; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 341c7f35836..dbb2e49962e 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -19,8 +19,8 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000400"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000400"; }; chosen { @@ -803,14 +803,14 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -818,7 +818,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi index f13ef4d05a8..98fa51bed30 100644 --- a/arch/arm/dts/tegra20-tamonten.dtsi +++ b/arch/arm/dts/tegra20-tamonten.dtsi @@ -476,7 +476,7 @@ status = "okay"; }; - sdhci@c8000600 { + mmc@c8000600 { cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts index 4733c813490..b26979496c6 100644 --- a/arch/arm/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index fa942d26078..9542eb6c41b 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -12,8 +12,8 @@ aliases { usb0 = "/usb@c5000000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000000"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000000"; spi0 = "/spi@7000c380"; }; @@ -55,12 +55,12 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 85cd1e39bda..50cf78e4170 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -18,8 +18,8 @@ usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; usb2 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000400"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000400"; }; memory { @@ -576,14 +576,14 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -591,7 +591,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 4a40edfdfbe..430df19b8b7 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -766,7 +766,7 @@ status = "disabled"; }; - sdhci@c8000000 { + mmc@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -776,7 +776,7 @@ status = "disabled"; }; - sdhci@c8000200 { + mmc@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -786,7 +786,7 @@ status = "disabled"; }; - sdhci@c8000400 { + mmc@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -796,7 +796,7 @@ status = "disabled"; }; - sdhci@c8000600 { + mmc@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts index 539e7cef93b..e5e9d68651a 100644 --- a/arch/arm/dts/tegra210-p2371-0000.dts +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -12,8 +12,8 @@ aliases { i2c0 = "/i2c@7000d000"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; usb0 = "/usb@7d000000"; }; @@ -21,14 +21,14 @@ reg = <0x0 0x80000000 0x0 0xc0000000>; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index 649c163152e..a619b2475eb 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -14,8 +14,8 @@ i2c0 = "/i2c@7000d000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; usb0 = "/usb@7d000000"; }; @@ -73,7 +73,7 @@ }; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; @@ -81,7 +81,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts index 16370c596e0..f48ce4d662f 100644 --- a/arch/arm/dts/tegra210-p2571.dts +++ b/arch/arm/dts/tegra210-p2571.dts @@ -17,8 +17,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; spi2 = "/spi@70410000"; @@ -74,14 +74,14 @@ spi-max-frequency = <24000000>; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts index ddeeb232de2..333060a4ec7 100644 --- a/arch/arm/dts/tegra210-p3450-0000.dts +++ b/arch/arm/dts/tegra210-p3450-0000.dts @@ -20,8 +20,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; spi0 = "/spi@70410000"; usb0 = "/usb@7d000000"; }; @@ -89,14 +89,14 @@ }; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index 92eb4f67bf5..45b1ca9a041 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -696,7 +696,7 @@ #phy-cells = <1>; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -709,7 +709,7 @@ status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -722,7 +722,7 @@ status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -735,7 +735,7 @@ status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 77502dfdb47..19553d14fb1 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -15,9 +15,9 @@ i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c500"; i2c3 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000400"; - mmc2 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000400"; + mmc2 = "/mmc@78000000"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000dc00"; spi2 = "/spi@7000de00"; @@ -246,21 +246,21 @@ spi-max-frequency = <25000000>; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; }; - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index ddacdbb85c8..8eb36eb8164 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -773,7 +773,7 @@ clock-frequency = <400000>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 31cbef1b93c..2d6b4aba016 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -1100,7 +1100,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1111,7 +1111,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 5135b8c666c..498c398baad 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -1065,7 +1065,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1076,7 +1076,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 47a44fbc9dd..e58414dc4b0 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -1093,7 +1093,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1104,7 +1104,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 9bb097b0813..b78982edd1a 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000000"; spi0 = "/spi@7000da00"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; @@ -191,7 +191,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; @@ -199,7 +199,7 @@ bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index 7534861e40d..299ba7ef371 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000000"; spi0 = "/spi@7000da00"; usb0 = "/usb@7d008000"; }; @@ -183,7 +183,7 @@ spi-max-frequency = <25000000>; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; @@ -191,7 +191,7 @@ bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index 38afe7819c7..075a35f1c9a 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -14,8 +14,8 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000200"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000200"; spi0 = "/spi@7000d400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d004000"; /* on module only, for ASIX */ @@ -61,13 +61,13 @@ spi-max-frequency = <25000000>; }; - sdhci@78000200 { + mmc@78000200 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index 79f423bd22a..e67d335f73c 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -1246,7 +1246,7 @@ }; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts index 53f42089d30..2d96d6867e6 100644 --- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts +++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts @@ -1119,7 +1119,7 @@ >; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1129,7 +1129,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts index ab5993150b2..84b6dc1f95a 100644 --- a/arch/arm/dts/tegra30-lg-p880.dts +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -126,7 +126,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts index 988e772172c..a45d57b3e71 100644 --- a/arch/arm/dts/tegra30-lg-p895.dts +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -120,7 +120,7 @@ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; renesas,gamma = <3>; - renesas,inversion; + renesas,column-inversion; renesas,contrast; vcc-supply = <&vcc_3v0_lcd>; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 09c5d04a225..9c074f3c553 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -1031,7 +1031,7 @@ }; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts index 2d22d3e0bb1..77cd79cb0d6 100644 --- a/arch/arm/dts/tegra30-microsoft-surface-rt.dts +++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts @@ -946,7 +946,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -956,7 +956,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts index e6b2824d783..4911c802a51 100644 --- a/arch/arm/dts/tegra30-ouya.dts +++ b/arch/arm/dts/tegra30-ouya.dts @@ -1970,7 +1970,7 @@ }; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-pegatron-chagall.dts b/arch/arm/dts/tegra30-pegatron-chagall.dts index 98eb369f7a8..1ff53b7c54b 100644 --- a/arch/arm/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/dts/tegra30-pegatron-chagall.dts @@ -1121,7 +1121,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1131,7 +1131,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi index 33da1754d30..0240568cd94 100644 --- a/arch/arm/dts/tegra30-tamonten.dtsi +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -18,9 +18,9 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000d000"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000400"; - mmc2 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000400"; + mmc2 = "/mmc@78000000"; usb0 = "/usb@7d008000"; }; @@ -54,14 +54,14 @@ }; /* SD slot on the base board */ - sdhci@78000400 { + mmc@78000400 { cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; /* EMMC on the COM module */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-tec-ng.dts b/arch/arm/dts/tegra30-tec-ng.dts index f2a49b8cbe2..444a390ba58 100644 --- a/arch/arm/dts/tegra30-tec-ng.dts +++ b/arch/arm/dts/tegra30-tec-ng.dts @@ -16,7 +16,7 @@ }; /* SD card slot */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; }; }; diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts index ededbf579fd..c310a22f56f 100644 --- a/arch/arm/dts/tegra30-wexler-qc750.dts +++ b/arch/arm/dts/tegra30-wexler-qc750.dts @@ -985,7 +985,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -996,7 +996,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 82e843d05be..cf772338b55 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -803,7 +803,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -813,7 +813,7 @@ status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -823,7 +823,7 @@ status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; @@ -833,7 +833,7 @@ status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 832dc5ab245..8342479b108 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -3,7 +3,7 @@ * dts file for KD240 revA Carrier Card * * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -43,6 +43,13 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &can0 { @@ -116,7 +123,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -125,7 +132,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 532f6bf92bc..db042ffb4f3 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -77,6 +77,14 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, + <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -187,7 +195,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -196,7 +204,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; @@ -224,7 +232,7 @@ reg = <1>; peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -233,7 +241,7 @@ reg = <2>; peer-hub = <&hub1_2_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 458d79e8119..e3567d0abfe 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -78,6 +78,14 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, + <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -188,7 +196,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -197,7 +205,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; @@ -225,7 +233,7 @@ reg = <1>; peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -234,7 +242,7 @@ reg = <2>; peer-hub = <&hub1_2_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index e7417af8ae0..f93c7460a55 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -3,7 +3,7 @@ * dts file for KV260 revA Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * SD level shifter: * "A" - A01 board un-modified (NXP) @@ -78,6 +78,13 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -161,7 +168,7 @@ compatible = "usb424,2744"; reg = <1>; peer-hub = <&hub_3_0>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -169,7 +176,7 @@ compatible = "usb424,5744"; reg = <2>; peer-hub = <&hub_2_0>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 7a05180e58b..70de6933600 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -74,6 +74,13 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -148,7 +155,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -157,7 +164,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 1af9778f8ce..25d0f205fde 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -79,6 +79,7 @@ #define MXC_CPU_IMX95 0x1C1 /* dummy ID */ #define MXC_CPU_IMX94 0x1C2 /* dummy ID */ +#define MXC_CPU_IMX952 0x1C3 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 diff --git a/arch/arm/include/asm/arch-rk3506/boot0.h b/arch/arm/include/asm/arch-rk3506/boot0.h new file mode 100644 index 00000000000..8ae46f25a87 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3506/boot0.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3506/gpio.h b/arch/arm/include/asm/arch-rk3506/gpio.h new file mode 100644 index 00000000000..5516e649b80 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3506/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 3c204501f70..95b08bfd046 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -215,6 +215,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table, u32 reg_offset, u32 reg_number); /* + * rk3506_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3506 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device * using dedicated RK3528 lookup table * diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3506.h b/arch/arm/include/asm/arch-rockchip/cru_rk3506.h new file mode 100644 index 00000000000..2f79e5eaf09 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3506.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <[email protected]> + */ + +#ifndef _ASM_ARCH_CRU_RK3506_H +#define _ASM_ARCH_CRU_RK3506_H + +#include <linux/bitops.h> +#include <linux/bitfield.h> + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +/* RK3506 pll id */ +enum rk3506_pll_id { + GPLL, + V0PLL, + V1PLL, + PLL_COUNT, +}; + +struct rk3506_clk_priv { + unsigned long gpll_hz; + unsigned long gpll_div_hz; + unsigned long gpll_div_100mhz; + unsigned long v0pll_hz; + unsigned long v0pll_div_hz; + unsigned long v1pll_hz; + unsigned long v1pll_div_hz; +}; + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RK3506_CRU_BASE 0xff9a0000 +#define RK3506_MODE_CON 0x0280 +#define RK3506_CLKSEL_CON(x) (RK3506_CRU_BASE + 0x0300 + (x) * 0x4) +#define RK3506_SOFTRST_CON0 0x0a00 +#define RK3506_GLB_SRST_FST 0x0c08 +#define RK3506_GLB_SRST_SND 0x0c0c +#define RK3506_PLL_CON(x) (0x10000 + (x) * 0x4) +#define RK3506_SCRU_BASE 0xff9a8000 +#define RK3506_PMU_CRU_BASE 0xff9b0000 +#define RK3506_PMU_CLKSEL_CON(x) (RK3506_PMU_CRU_BASE + 0x0300 + (x) * 0x4) + +enum { + /* CRU_CLKSEL_CON00 */ + CLK_GPLL_DIV_MASK = GENMASK(9, 6), + CLK_GPLL_DIV_100M_MASK = GENMASK(13, 10), + + /* CRU_CLKSEL_CON01 */ + CLK_V0PLL_DIV_MASK = GENMASK(3, 0), + CLK_V1PLL_DIV_MASK = GENMASK(7, 4), + + /* CRU_CLKSEL_CON15 */ + CLK_CORE_SRC_DIV_MASK = GENMASK(4, 0), + CLK_CORE_SRC_SEL_MASK = GENMASK(6, 5), + CLK_CORE_SEL_GPLL = 0, + CLK_CORE_SEL_V0PLL, + CLK_CORE_SEL_V1PLL, + + ACLK_CORE_DIV_MASK = GENMASK(12, 9), + + /* CRU_CLKSEL_CON16 */ + PCLK_CORE_DIV_MASK = GENMASK(3, 0), + + /* CRU_CLKSEL_CON21 */ + ACLK_BUS_DIV_MASK = GENMASK(4, 0), + ACLK_BUS_SEL_MASK = GENMASK(6, 5), + ACLK_BUS_SEL_GPLL_DIV = 0, + ACLK_BUS_SEL_V0PLL_DIV, + ACLK_BUS_SEL_V1PLL_DIV, + + HCLK_BUS_DIV_MASK = GENMASK(11, 7), + HCLK_BUS_SEL_MASK = GENMASK(13, 12), + + /* CRU_CLKSEL_CON22 */ + PCLK_BUS_DIV_MASK = GENMASK(4, 0), + PCLK_BUS_SEL_MASK = GENMASK(6, 5), + + /* CRU_CLKSEL_CON29 */ + HCLK_LSPERI_DIV_MASK = GENMASK(4, 0), + HCLK_LSPERI_SEL_MASK = GENMASK(6, 5), + + /* CRU_CLKSEL_CON32 */ + CLK_I2C0_DIV_MASK = GENMASK(3, 0), + CLK_I2C0_SEL_MASK = GENMASK(5, 4), + CLK_I2C_SEL_GPLL = 0, + CLK_I2C_SEL_V0PLL, + CLK_I2C_SEL_V1PLL, + CLK_I2C1_DIV_MASK = GENMASK(9, 6), + CLK_I2C1_SEL_MASK = GENMASK(11, 10), + + /* CRU_CLKSEL_CON33 */ + CLK_I2C2_DIV_MASK = GENMASK(3, 0), + CLK_I2C2_SEL_MASK = GENMASK(5, 4), + CLK_PWM1_DIV_MASK = GENMASK(9, 6), + CLK_PWM1_SEL_MASK = GENMASK(11, 10), + CLK_PWM1_SEL_GPLL_DIV = 0, + CLK_PWM1_SEL_V0PLL_DIV, + CLK_PWM1_SEL_V1PLL_DIV, + + /* CRU_CLKSEL_CON34 */ + CLK_SPI0_DIV_MASK = GENMASK(7, 4), + CLK_SPI0_SEL_MASK = GENMASK(9, 8), + CLK_SPI_SEL_24M = 0, + CLK_SPI_SEL_GPLL_DIV, + CLK_SPI_SEL_V0PLL_DIV, + CLK_SPI_SEL_V1PLL_DIV, + CLK_SPI1_DIV_MASK = GENMASK(13, 10), + CLK_SPI1_SEL_MASK = GENMASK(15, 14), + + /* CRU_CLKSEL_CON49 */ + ACLK_HSPERI_DIV_MASK = GENMASK(4, 0), + ACLK_HSPERI_SEL_MASK = GENMASK(6, 5), + ACLK_HSPERI_SEL_GPLL_DIV = 0, + ACLK_HSPERI_SEL_V0PLL_DIV, + ACLK_HSPERI_SEL_V1PLL_DIV, + + CCLK_SDMMC_DIV_MASK = GENMASK(12, 7), + CCLK_SDMMC_SEL_MASK = GENMASK(14, 13), + CCLK_SDMMC_SEL_24M = 0, + CCLK_SDMMC_SEL_GPLL, + CCLK_SDMMC_SEL_V0PLL, + CCLK_SDMMC_SEL_V1PLL, + + /* CRU_CLKSEL_CON50 */ + SCLK_FSPI_DIV_MASK = GENMASK(4, 0), + SCLK_FSPI_SEL_MASK = GENMASK(6, 5), + SCLK_FSPI_SEL_24M = 0, + SCLK_FSPI_SEL_GPLL, + SCLK_FSPI_SEL_V0PLL, + SCLK_FSPI_SEL_V1PLL, + CLK_MAC_DIV_MASK = GENMASK(11, 7), + + /* CRU_CLKSEL_CON54 */ + CLK_SARADC_DIV_MASK = GENMASK(3, 0), + CLK_SARADC_SEL_MASK = GENMASK(5, 4), + CLK_SARADC_SEL_24M = 0, + CLK_SARADC_SEL_400K, + CLK_SARADC_SEL_32K, + + /* CRU_CLKSEL_CON60 */ + DCLK_VOP_DIV_MASK = GENMASK(7, 0), + DCLK_VOP_SEL_MASK = GENMASK(10, 8), + DCLK_VOP_SEL_24M = 0, + DCLK_VOP_SEL_GPLL, + DCLK_VOP_SEL_V0PLL, + DCLK_VOP_SEL_V1PLL, + DCLK_VOP_SEL_FRAC_VOIC1, + DCLK_VOP_SEL_FRAC_COMMON0, + DCLK_VOP_SEL_FRAC_COMMON1, + DCLK_VOP_SEL_FRAC_COMMON2, + + /* CRU_CLKSEL_CON61 */ + CLK_TSADC_DIV_MASK = GENMASK(7, 0), + CLK_TSADC_TSEN_DIV_MASK = GENMASK(10, 8), + + /* PMUCRU_CLKSEL_CON00 */ + CLK_PWM0_DIV_MASK = GENMASK(9, 6), + CLK_MAC_OUT_DIV_MASK = GENMASK(15, 10), + + /* SCRU_CLKSEL_CON104 */ + CLK_PKA_CRYPTO_DIV_MASK = GENMASK(11, 7), + CLK_PKA_CRYPTO_SEL_MASK = GENMASK(13, 12), + CLK_PKA_CRYPTO_SEL_GPLL = 0, + CLK_PKA_CRYPTO_SEL_V0PLL, + CLK_PKA_CRYPTO_SEL_V1PLL, +}; + +#endif /* _ASM_ARCH_CRU_RK3506_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h index a5fc6ad3656..01f2214cd15 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h @@ -205,6 +205,8 @@ struct dram_para { uint32_t mr12; uint32_t mr13; uint32_t mr14; + uint32_t mr22; + uint32_t tpr0; uint32_t tpr1; uint32_t tpr2; uint32_t tpr3; diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index a399c94213b..8c38c71c93a 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -68,6 +68,7 @@ struct timerus { /* These are the available SKUs (product types) for Tegra */ enum { + SKU_ID_T20_A04 = 0x4, /* Sony Tablet P value */ SKU_ID_AP20 = 0x7, SKU_ID_T20 = 0x8, SKU_ID_AP20H = 0xf, diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index 439e43c2d01..762f00e6900 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -8,8 +8,6 @@ #ifndef ARM_BOOTM_H #define ARM_BOOTM_H -extern void udc_disconnect(void); - #ifdef CONFIG_SUPPORT_PASSING_ATAGS # define BOOTM_ENABLE_TAGS 1 #else diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 4e1afc42bd8..04e7f20a2a6 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -49,6 +49,7 @@ #define ELE_ATTEST_REQ (0xDB) #define ELE_RELEASE_PATCH_REQ (0xDC) #define ELE_OTP_SEQ_SWITH_REQ (0xDD) +#define ELE_SET_GMID_REQ (0xE4) #define ELE_WRITE_SHADOW_REQ (0xF2) #define ELE_READ_SHADOW_REQ (0xF3) @@ -162,6 +163,7 @@ int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); int ele_start_rng(void); int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response); int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); +int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); #endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 46da7a1eff5..ab573413128 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -99,6 +99,7 @@ struct bd_info; #define is_imx94() (is_cpu_type(MXC_CPU_IMX94)) #define is_imx95() (is_cpu_type(MXC_CPU_IMX95)) +#define is_imx952() (is_cpu_type(MXC_CPU_IMX952)) #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121)) #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111)) @@ -254,6 +255,43 @@ struct scmi_rom_passover_get_out { u32 passover[(sizeof(rom_passover_t) + 8) / 4]; }; +/** + * struct scmi_ddr_info_out - Get DDR memory region info + * @status: Error code + * @attributes: Region attributes: + * Bit[31] ECC enable. + * Set to 1 if ECC enabled. + * Set to 0 if ECC disabled or not configured. + * Bits[30:18] Reserved, must be zero. + * Bits[17:16] Number of DDR memory regions. + * Bits[15:11] Reserved, must be zero. + * Bits[10:8] Width. + * Bus width is 16 << this field. + * So 0=16, 1=32, 2=64, etc. + * Bits[7:5] Reserved, must be zero. + * Bits[4:0] DDR type. + * Set to 0 if LPDDR5. + * Set to 1 if LPDDR5X. + * Set to 2 if LPDDR4. + * Set to 3 if LPDDR4X + * @mts: DDR speed in megatransfers per second + * @startlow: The lower 32 bits of the physical start address of the region + * @starthigh: The upper 32 bits of the physical start address of the region + * @endlow: The lower 32 bits of the physical end address of the region. This + * excludes any DDR used to store ECC data + * @endhigh: The upper 32 bits of the physical end address of the region. This + * excludes any DDR used to store ECC data + */ +struct scmi_ddr_info_out { + s32 status; + u32 attributes; + u32 mts; + u32 startlow; + u32 starthigh; + u32 endlow; + u32 endhigh; +}; + #endif /* For i.MX ULP */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index ee79a19c05c..dd462ea6ad8 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_XIP, BOOT_DEVICE_BOOTROM, BOOT_DEVICE_SMH, + BOOT_DEVICE_UFS, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4c1b81483c9..9e3ad57073d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -171,6 +171,12 @@ static inline unsigned int current_el(void) return 3 & (el >> 2); } +static inline unsigned int current_pl(void) +{ + /* Aarch32 compatibility */ + return current_el(); +}; + static inline unsigned long get_sctlr(void) { unsigned int el; @@ -466,6 +472,39 @@ static inline int is_hyp(void) #endif } +static inline int is_usr(void) +{ + return (get_cpsr() & 0x1f) == 0x10; +} + +static inline unsigned int current_pl(void) +{ + /* + * ARM DDI 0406C.d ID040418 , page 140 chapter A3.6.1 "Processor + * privilege levels, execution privilege, and access privilege", + * clarifies the PLx levels as follows (abbreviated): + * The characteristics of the privilege levels are: + * - PL0 - The privilege level of application software, that + * executes in User mode. + * - PL1 - Software execution in all modes other than User mode + * and Hyp mode is at PL1. + * - PL2 - Software executing in Hyp mode executes at PL2. + */ + if (is_hyp()) /* HYP */ + return 2; + + if (is_usr()) /* USR */ + return 0; + + return 1; /* The rest */ +} + +static inline unsigned int current_el(void) +{ + /* Aarch64 compatibility */ + return current_pl(); +}; + static inline unsigned int get_cr(void) { unsigned int val; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 019eca95780..727b9c5ca5b 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -42,42 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; -__weak void board_quiesce_devices(void) -{ -} - -/** - * announce_and_cleanup() - Print message and prepare for kernel boot - * - * @fake: non-zero to do everything except actually boot - */ -static void announce_and_cleanup(int fake) -{ - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_FDT - bootstage_fdt_add_report(); -#endif - bootstage_stash_default(); -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif - - board_quiesce_devices(); - - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - /* - * Call remove function of all devices with a removal flag set. - * This may be useful for last-stage operations, like cancelling - * of DMA operation or releasing device internal buffers. - * dm_remove_devices_active() ensures that vital devices are removed in - * a second round. - */ - dm_remove_devices_active(); - - cleanup_before_linux(); -} - static void setup_start_tag (struct bd_info *bd) { params = (struct tag *)bd->bi_boot_params; @@ -294,8 +258,6 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*kernel_entry)(void *fdt_addr, void *res0, void *res1, void *res2); - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = (void (*)(void *fdt_addr, void *res0, void *res1, void *res2))images->ep; @@ -303,9 +265,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) (ulong) kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - announce_and_cleanup(fake); + bootm_final(flag); + cleanup_before_linux(); - if (!fake) { + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) { #ifdef CONFIG_ARMV8_PSCI armv8_setup_psci(); #endif @@ -340,8 +303,6 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) char *s; void (*kernel_entry)(int zero, int arch, uint params); unsigned long r2; - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = (void (*)(int, int, uint))images->ep; #ifdef CONFIG_CPU_V7M ulong addr = (ulong)kernel_entry | 1; @@ -366,14 +327,15 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) debug("## Transferring control to Linux (at address %08lx)" \ "...\n", (ulong) kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - announce_and_cleanup(fake); + bootm_final(flag); + cleanup_before_linux(); if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) r2 = (unsigned long)images->ft_addr; else r2 = gd->bd->bi_boot_params; - if (fake) + if (flag & BOOTM_STATE_OS_FAKE_GO) return; #ifdef CONFIG_ARMV7_NONSEC diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index d10c129705d..f2c5aa37a8f 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -157,7 +157,11 @@ ENTRY(_main) orr lr, #1 /* As required by Thumb-only */ #endif ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ +#if defined(CONFIG_SKIP_RELOCATE_CODE) + bl relocate_code +#else b relocate_code +#endif here: /* * now relocate vectors diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index bffadfecba1..b6a648708f4 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -79,6 +79,15 @@ ENDPROC(relocate_vectors) ENTRY(relocate_code) relocate_base: adr r3, relocate_base + +#ifdef CONFIG_SKIP_RELOCATE_CODE + mov r4, #CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET + + ldr r1, _data_start_ofs + add r5, r1, r3 /* r5 <- Run &__data_start */ + ldr r1, _data_end_ofs + add r6, r1, r3 /* r6 <- Run &__data_end */ +#else ldr r1, _image_copy_start_ofs add r1, r3 /* r1 <- Run &__image_copy_start */ subs r4, r0, r1 /* r4 <- Run to copy offset */ @@ -90,6 +99,7 @@ copy_loop: stmia r0!, {r10-r11} /* copy to target address [r0] */ cmp r1, r2 /* until source end address [r2] */ blo copy_loop +#endif /* * fix .rel.dyn relocations @@ -107,6 +117,15 @@ fixloop: /* relative fix: increase location by offset */ add r0, r0, r4 ldr r1, [r0] + +#ifdef CONFIG_SKIP_RELOCATE_CODE + /* Test whether this is data, if not, do not relocate. */ + cmp r1, r5 + blt fixnext + cmp r1, r6 + bgt fixnext +#endif + add r1, r1, r4 str r1, [r0] fixnext: @@ -114,16 +133,6 @@ fixnext: blo fixloop relocate_done: - -#ifdef __XSCALE__ - /* - * On xscale, icache must be invalidated and write buffers drained, - * even with cache disabled - 4.2.7 of xscale core developer's manual - */ - mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ -#endif - ret lr ENDPROC(relocate_code) @@ -136,3 +145,9 @@ _rel_dyn_start_ofs: .word __rel_dyn_start - relocate_code _rel_dyn_end_ofs: .word __rel_dyn_end - relocate_code +#ifdef CONFIG_SKIP_RELOCATE_CODE +_data_start_ofs: + .word __data_start - relocate_code +_data_end_ofs: + .word __data_end - relocate_code +#endif diff --git a/arch/arm/mach-airoha/Kconfig b/arch/arm/mach-airoha/Kconfig index b9cd0a413e1..4b0374001d0 100644 --- a/arch/arm/mach-airoha/Kconfig +++ b/arch/arm/mach-airoha/Kconfig @@ -10,6 +10,7 @@ config TARGET_EN7523 bool "Airoha EN7523 SoC" select CPU_V7A select ARMV7_SET_CORTEX_SMPEN + select REGMAP help The Airoha EN7523 family (en7523/en7529/en7562) is an ARM-based SoCs with a dual-core CPU. It comes with Wi-Fi 5/6 support and diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 9cf60378c11..c88b1e59366 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -18,6 +18,7 @@ config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" select CPU_ARM1176 select DM_RESET + select REGMAP help The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. It is used as Board Management Controller on many server boards, diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 0c5a82ed094..60f2c5d291e 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -9,9 +9,6 @@ #include <linux/err.h> #include <asm/io.h> #include <asm/arch/scu_ast2600.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0f6e737c0b9..bf6820de655 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,7 +223,7 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94),$(CONFIG_IMX952))),) SPL: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 20c741283cd..8af45e14707 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -310,7 +310,8 @@ void arch_preboot_os(void) /* disable video before launching O/S */ rc = uclass_find_first_device(UCLASS_VIDEO, &dev); while (!rc && dev) { - ipuv3_fb_shutdown(dev); + if (device_active(dev)) + ipuv3_fb_shutdown(dev); uclass_find_next_device(&dev); } #endif diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 4d4620dcafd..9794391fb35 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -412,7 +412,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } -#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) +#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) || IS_ENABLED(CONFIG_IMX952) #define FSB_LC_OFFSET 0x414 #define LC_OEM_OPEN 0x10 static void display_life_cycle(u32 lc) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 78f2488cf6d..7bfcc9d7e9d 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type) debug("seco container size 0x%x\n", value_container[0]); - if (is_imx95() || is_imx94()) { + if (is_imx95() || is_imx94() || is_imx952()) { offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw); @@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type) value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL); if (value_container[2] < 0) { debug("Parse scu container image failed %d, only seco container\n", value_container[2]); - if (is_imx95() || is_imx94()) + if (is_imx95() || is_imx94() || is_imx952()) return value_container[1] + offset[1]; /* return seco + v2x container total size */ else return value_container[0] + offset[0]; /* return seco container total size */ diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 4e49b5bf375..e37d3bf31e4 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -3,12 +3,9 @@ * Copyright 2018 NXP */ -#include <asm/global_data.h> #include <linux/errno.h> #include <asm/arch/clock.h> -DECLARE_GLOBAL_DATA_PTR; - u32 mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0e112af661c..f4738e3fda8 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -899,3 +899,24 @@ bool m4_parts_booted(void) return false; } + +#ifdef CONFIG_IMX8QXP +#include <blk.h> + +/* + * On B0 revision SoCs the bootloader is on 32k offset + * and at offset 0x0 is the U-Boot Environment stored + * + * So we cannot flash bootloader images to offset 0x0 + * + * On C0 revisions of the SoC bootloader image starts + * at offset 0x0 ... + */ +lbaint_t fb_mmc_get_boot_offset(void) +{ + if ((get_cpu_rev() & 0xF) < CHIP_REV_C) + return 0x40; + + return 0; +} +#endif diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index ce78c8ce919..8337edc2f62 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -6,7 +6,6 @@ #include <log.h> #include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <dm/ofnode.h> #include <fdt_support.h> #include <linux/libfdt.h> @@ -14,8 +13,6 @@ #include <cpu.h> #include <dm.h> -DECLARE_GLOBAL_DATA_PTR; - static bool check_owned_resource(sc_rsrc_t rsrc_id) { bool owned; diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index 3e27d75827a..b6175a50226 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -4,13 +4,10 @@ */ #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/iomux.h> #include <firmware/imx/sci/sci.h> -DECLARE_GLOBAL_DATA_PTR; - /* * configures a single pad in the iomuxer */ diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index c77104d0338..22d6959f74f 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <command.h> +#include <env.h> #include <log.h> #include <firmware/imx/sci/sci.h> #include <asm/mach-imx/sys_proto.h> @@ -62,3 +64,34 @@ void build_info(void) printf("Build: SCFW %08x, SECO-FW %08x, ATF %s\n", sc_commit, seco_commit, (char *)&atf_commit); } + +int do_boottype(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + sc_misc_bt_t boot_type; + + if (argc > 2) + return CMD_RET_USAGE; + + if (sc_misc_get_boot_type(-1, &boot_type) != 0) { + puts("boottype cannot be retrieved\n"); + return CMD_RET_FAILURE; + } + + if (argc > 1) + printf("Boottype: %d\n", boot_type); + + env_set_ulong("boottype", boot_type); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(boottype, CONFIG_SYS_MAXARGS, 2, do_boottype, + "save current boot-container in env variable 'boottype'", + "possible values for boottype:\n" + "0: SC_MISC_BT_PRIMARY\n" + "1: SC_MISC_BT_SECONDARY\n" + "2: SC_MISC_BT_RECOVERY\n" + "3: SC_MISC_BT_MANUFACTURE\n" + "4: SC_MISC_BT_SERIAL\n" + "[print] - print current boottype" +); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 77c8efc7899..b7b3702041e 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -8,7 +8,6 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <div64.h> #include <errno.h> @@ -16,8 +15,6 @@ #include <linux/delay.h> #include <phy.h> -DECLARE_GLOBAL_DATA_PTR; - static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; static u32 get_root_clk(enum clk_root_index clock_id); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index f9d8ed5b048..69585a3605b 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -10,12 +10,9 @@ #include <asm/arch/cgc.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <hang.h> -DECLARE_GLOBAL_DATA_PTR; - static struct cgc1_regs *cgc1_regs = (struct cgc1_regs *)0x292C0000UL; static struct cgc2_regs *cgc2_regs = (struct cgc2_regs *)0x2da60000UL; diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index c390f20d769..1b5cbd56f50 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -12,11 +12,8 @@ #include <asm/arch/pcc.h> #include <asm/arch/cgc.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - #define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) #define PLL_USB_PWR_MASK (0x01 << 12) #define PLL_USB_ENABLE_MASK (0x01 << 13) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index d9f97e4328c..2308457df23 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -47,6 +47,15 @@ config IMX94 select SCMI_FIRMWARE select SPL_IMX_CONTAINER_USE_TRAMPOLINE +config IMX952 + bool + select ARMV8_SPL_EXCEPTION_VECTORS + select DM_MAILBOX + select IMX9 + select IMX_PQC_SUPPORT + select SCMI_FIRMWARE + select SPL_IMX_CONTAINER_USE_TRAMPOLINE + config SYS_SOC default "imx9" @@ -120,6 +129,14 @@ config TARGET_KONTRON_MX93 Kontron Electronics BL i.MX93 using SoM module conformant to OSM standard 1.1 size S. +config TARGET_PHYCORE_IMX91 + bool "phycore_imx91" + select IMX91 + select IMX9_LPDDR4X + imply OF_UPSTREAM + select OF_BOARD_FIXUP + select OF_BOARD_SETUP + config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 @@ -152,6 +169,18 @@ config TARGET_IMX943_EVK config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 + imply OF_UPSTREAM + +config TARGET_IMX952_EVK + bool "imx952_evk" + select IMX_SM_CPU + select IMX_SM_LMM + select IMX952 + select REGMAP + select SYSCON + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM endchoice @@ -161,10 +190,11 @@ source "board/nxp/imx93_evk/Kconfig" source "board/nxp/imx93_frdm/Kconfig" source "board/nxp/imx93_qsb/Kconfig" source "board/kontron/osm-s-mx93/Kconfig" -source "board/phytec/phycore_imx93/Kconfig" +source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" source "board/toradex/smarc-imx95/Kconfig" +source "board/nxp/imx952_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index e65cabef2c9..14a2bdf5762 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -10,7 +10,6 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/ccm_regs.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <div64.h> #include <errno.h> @@ -19,8 +18,6 @@ #include <log.h> #include <phy.h> -DECLARE_GLOBAL_DATA_PTR; - static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; static struct imx_intpll_rate_table imx9_intpll_tbl[] = { diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 5dbc398e97f..acf79a40584 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -11,11 +11,8 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <linux/iopoll.h> -DECLARE_GLOBAL_DATA_PTR; - static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; static enum ccm_clk_src clk_root_mux[][4] = { diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h index dd4675402c7..c3610127dce 100644 --- a/arch/arm/mach-imx/imx9/scmi/common.h +++ b/arch/arm/mach-imx/imx9/scmi/common.h @@ -21,6 +21,16 @@ #define IMX95_PD_M70 IMX95_PD_M7 #endif +#ifdef CONFIG_IMX952 +#define IMX_PLAT 952 +#include <imx952-clock.h> +#include <imx952-power.h> + +#define IMX952_CLK_SEL_A55C0 IMX952_CLK_GPR_SEL_A55C0 +#define IMX952_PD_M70 IMX952_PD_M7 +#define IMX952_CLK_FLEXSPI1 IMX952_CLK_XSPI1 +#define IMX952_CLK_24M IMX952_CLK_OSC24M +#endif #define IMX_PLAT_STR__(plat) # plat #define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index c1458ccca3c..fbee435786c 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -58,6 +58,34 @@ uint32_t scmi_get_rom_data(rom_passover_t *rom_data) return 0; } +int scmi_misc_ddrinfo(u32 ddrc_id, struct scmi_ddr_info_out *out) +{ + u32 in = ddrc_id; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_MISC_DDR_INFO_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)out, + .out_msg_sz = sizeof(*out), + }; + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret != 0 || out->status != 0) { + printf("Failed to get ddr cfg, scmi_err = %d\n", + out->status); + return -EINVAL; + } + + return 0; +} + #if IS_ENABLED(CONFIG_ENV_IS_IN_MMC) __weak int board_mmc_get_env_dev(int devno) { @@ -125,6 +153,8 @@ u32 get_cpu_speed_grade_hz(void) if (is_imx95()) max_speed = 2000000000; + if (is_imx952()) + max_speed = 1700000000; /* In case the fuse of speed grade not programmed */ if (speed > max_speed) @@ -335,25 +365,44 @@ void enable_caches(void) __weak int board_phys_sdram_size(phys_size_t *size) { + struct scmi_ddr_info_out ddr_info = {0}; + int ret; + u32 ddrc_id = 0, ddrc_num = 1; phys_size_t start, end; - phys_size_t val; if (!size) return -EINVAL; - val = readl(REG_DDR_CS0_BNDS); - start = (val >> 16) << 24; - end = (val & 0xFFFF); - end = end ? end + 1 : 0; - end = end << 24; - *size = end - start; + *size = 0; + do { + ret = scmi_misc_ddrinfo(ddrc_id++, &ddr_info); + if (ret) { + /* if get DDR info failed, fall to default config */ + *size = PHYS_SDRAM_SIZE; +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; + } else { + ddrc_num = ((ddr_info.attributes >> 16) & 0x3); + start = ddr_info.starthigh; + start <<= 32; + start += ddr_info.startlow; - val = readl(REG_DDR_CS1_BNDS); - start = (val >> 16) << 24; - end = (val & 0xFFFF); - end = end ? end + 1 : 0; - end = end << 24; - *size += end - start; + end = ddr_info.endhigh; + end <<= 32; + end += ddr_info.endlow; + + *size += end + 1 - start; + + debug("ddr info attr 0x%x, start 0x%x 0x%x, end 0x%x 0x%x, mts %u\n", + ddr_info.attributes, ddr_info.starthigh, ddr_info.startlow, + ddr_info.endhigh, ddr_info.endlow, ddr_info.mts); + } + } while (ddrc_id < ddrc_num); + + /* SM reports total DDR size, need remove secure memory */ + *size -= PHYS_SDRAM - 0x80000000; return 0; } @@ -737,8 +786,10 @@ static void gpio_reset(ulong gpio_base) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { - disable_wdog((void __iomem *)WDG3_BASE_ADDR); - disable_wdog((void __iomem *)WDG4_BASE_ADDR); + if (!IS_ENABLED(CONFIG_IMX952)) { + disable_wdog((void __iomem *)WDG3_BASE_ADDR); + disable_wdog((void __iomem *)WDG4_BASE_ADDR); + } gpio_reset(GPIO2_BASE_ADDR); gpio_reset(GPIO3_BASE_ADDR); @@ -820,7 +871,7 @@ int timer_init(void) return 0; } -enum env_location env_get_location(enum env_operation op, int prio) +enum env_location arch_env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); enum env_location env_loc = ENVL_UNKNOWN; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 583c3a5a464..44b3e0f5310 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob) return 0; } -#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) +#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \ + !defined(CONFIG_TARGET_PHYCORE_IMX91) #ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 7452b82f110..90d91b2300a 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -6,14 +6,11 @@ #include <lmb.h> #include <log.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/mach-imx/regs-common.h> -DECLARE_GLOBAL_DATA_PTR; - /* 1 second delay should be plenty of time for block reset. */ #define RESET_MAX_TIMEOUT 1000000 diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f64bebfc14b..d198d9932f4 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -120,7 +120,7 @@ config TARGET_APALIS_IMX6 select DM_THERMAL select SUPPORT_SPL imply CMD_DM - imply CMD_SATA + imply SATA config TARGET_ARISTAINETOS2C bool "Support aristainetos2-revC" @@ -130,7 +130,7 @@ config TARGET_ARISTAINETOS2C select MXC_UART select FEC_MXC select DM - imply CMD_SATA + imply SATA imply CMD_DM config TARGET_ARISTAINETOS2CCSLB @@ -141,7 +141,7 @@ config TARGET_ARISTAINETOS2CCSLB select MXC_UART select FEC_MXC select DM - imply CMD_SATA + imply SATA imply CMD_DM config TARGET_CM_FX6 @@ -230,7 +230,7 @@ config TARGET_GW_VENTANA select SUPPORT_SPL select GATEWORKS_SC select MISC - imply CMD_SATA + imply SATA imply CMD_SPL config TARGET_KONTRON_MX6UL @@ -419,7 +419,6 @@ config TARGET_MX6SXSABRESD config TARGET_MX6SXSABREAUTO bool "mx6sxsabreauto" depends on MX6SX - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM select DM_THERMAL diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index b7008df8e35..d36536e600e 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -7,13 +7,10 @@ #include <image.h> #include <imx_container.h> #include <log.h> -#include <asm/global_data.h> #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/sys_proto.h> -DECLARE_GLOBAL_DATA_PTR; - /* Caller need ensure the offset and size to align with page size */ ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf) { diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 1b8c0b1eb96..a32ed3a9683 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -130,6 +130,15 @@ config K3_ATF_LOAD_ADDR The load address for the ATF image. This value is used to build the FIT image header that places ATF in memory where it will run. +config K3_ATF_RESERVED_SIZE + hex "Reserved memory size for ATF" + default 0x80000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S) + default 0x20000 + help + The runtime memory size reserved for ATF. This value is used to fixup the + kernel device-tree's reserved-memory node for ATF and configure the + firewall. + config K3_OPTEE_LOAD_ADDR hex "Load address of OPTEE image" default 0x9e800000 @@ -137,6 +146,14 @@ config K3_OPTEE_LOAD_ADDR The load address for the OPTEE image. This value defaults to 0x9e800000 if not provided in the board defconfig file. +config K3_OPTEE_RESERVED_SIZE + hex "Reserved memory size for OPTEE" + default 0x1800000 + help + The runtime memory size reserved for OPTEE. This value is used to fixup + the kernel device-tree's reserved-memory node for OPTEE and configure the + firewall. + config K3_DM_FW bool "Separate DM firmware image" depends on CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 2f3df5519c5..b0a75988714 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -457,6 +457,83 @@ static __maybe_unused void k3_dma_remove(void) pr_warn("DMA Device not found (err=%d)\n", rc); } +static int k3_falcon_fdt_add_bootargs(void *fdt) +{ + struct disk_partition info; + struct blk_desc *dev_desc; + char bootmedia[32]; + char bootpart[32]; + char str[256]; + int ret; + + strlcpy(bootmedia, env_get("boot"), sizeof(bootmedia)); + strlcpy(bootpart, env_get("bootpart"), sizeof(bootpart)); + ret = blk_get_device_part_str(bootmedia, bootpart, &dev_desc, &info, 0); + if (ret < 0) { + printf("%s: Failed to get part details for %s %s [%d]\n", + __func__, bootmedia, bootpart, ret); + return ret; + } + + if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) { + printf("ERROR: Failed to find rootfs PARTUUID\n"); + printf("%s: CONFIG_SPL_PARTITION_UUIDS not enabled\n", + __func__); + return -EOPNOTSUPP; + } + + snprintf(str, sizeof(str), "console=%s root=PARTUUID=%s rootwait", + env_get("console"), disk_partition_uuid(&info)); + + ret = fdt_find_and_setprop(fdt, "/chosen", "bootargs", str, + strlen(str) + 1, 1); + if (ret) { + printf("%s: Could not set bootargs: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + + debug("%s: Set bootargs to: %s\n", __func__, str); + return 0; +} + +int k3_falcon_fdt_fixup(void *fdt) +{ + int ret; + + if (!fdt) + return -EINVAL; + + fdt_set_totalsize(fdt, fdt_totalsize(fdt) + CONFIG_SYS_FDT_PAD); + + if (fdt_path_offset(fdt, "/chosen/bootargs") < 0) { + ret = k3_falcon_fdt_add_bootargs(fdt); + + if (ret) + return ret; + } + + if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) { + ret = ft_board_setup(fdt, gd->bd); + if (ret) { + printf("%s: Failed in board setup: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + } + + if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) { + ret = ft_system_setup(fdt, gd->bd); + if (ret) { + printf("%s: Failed in system setup: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + } + + return 0; +} + void spl_perform_arch_fixups(struct spl_image_info *spl_image) { void *fdt = spl_image_fdt_addr(spl_image); @@ -465,6 +542,9 @@ void spl_perform_arch_fixups(struct spl_image_info *spl_image) return; fdt_fixup_reserved(fdt); + + if (IS_ENABLED(CONFIG_SPL_OS_BOOT)) + k3_falcon_fdt_fixup(fdt); } void spl_board_prepare_for_boot(void) diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index e970076d08e..466ad22f895 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -61,10 +61,13 @@ void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); int shutdown_mcu_r5_core1(void); -#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) +int k3_falcon_fdt_fixup(void *fdt); +#if !IS_ENABLED(CONFIG_ARM64) int k3_r5_falcon_bootmode(void); int k3_r5_falcon_prep(void); #endif +#endif #if (IS_ENABLED(CONFIG_K3_QOS)) void setup_qos(void); diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index cb0fb8274a5..39cb00c3f43 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -173,12 +173,13 @@ int fdt_fixup_reserved(void *blob) int ret; ret = fdt_fixup_reserved_memory(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, - 0x80000); + CONFIG_K3_ATF_RESERVED_SIZE); if (ret) return ret; return fdt_fixup_reserved_memory(blob, "optee", - CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); + CONFIG_K3_OPTEE_LOAD_ADDR, + CONFIG_K3_OPTEE_RESERVED_SIZE); } static int fdt_fixup_critical_trips(void *blob, int zoneoffset, int maxc) diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 03638366046..484d96f9536 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -406,83 +406,6 @@ int k3_r5_falcon_bootmode(void) return BOOT_DEVICE_NOBOOT; } -static int k3_falcon_fdt_add_bootargs(void *fdt) -{ - struct disk_partition info; - struct blk_desc *dev_desc; - char bootmedia[32]; - char bootpart[32]; - char str[256]; - int ret; - - strlcpy(bootmedia, env_get("boot"), sizeof(bootmedia)); - strlcpy(bootpart, env_get("bootpart"), sizeof(bootpart)); - ret = blk_get_device_part_str(bootmedia, bootpart, &dev_desc, &info, 0); - if (ret < 0) { - printf("%s: Failed to get part details for %s %s [%d]\n", - __func__, bootmedia, bootpart, ret); - return ret; - } - - if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) { - printf("ERROR: Failed to find rootfs PARTUUID\n"); - printf("%s: CONFIG_SPL_PARTITION_UUIDS not enabled\n", - __func__); - return -EOPNOTSUPP; - } - - snprintf(str, sizeof(str), "console=%s root=PARTUUID=%s rootwait", - env_get("console"), disk_partition_uuid(&info)); - - ret = fdt_find_and_setprop(fdt, "/chosen", "bootargs", str, - strlen(str) + 1, 1); - if (ret) { - printf("%s: Could not set bootargs: %s\n", __func__, - fdt_strerror(ret)); - return ret; - } - - debug("%s: Set bootargs to: %s\n", __func__, str); - return 0; -} - -static int k3_falcon_fdt_fixup(void *fdt) -{ - int ret; - - if (!fdt) - return -EINVAL; - - fdt_set_totalsize(fdt, fdt_totalsize(fdt) + CONFIG_SYS_FDT_PAD); - - if (fdt_path_offset(fdt, "/chosen/bootargs") < 0) { - ret = k3_falcon_fdt_add_bootargs(fdt); - - if (ret) - return ret; - } - - if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) { - ret = ft_board_setup(fdt, gd->bd); - if (ret) { - printf("%s: Failed in board setup: %s\n", __func__, - fdt_strerror(ret)); - return ret; - } - } - - if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) { - ret = ft_system_setup(fdt, gd->bd); - if (ret) { - printf("%s: Failed in system setup: %s\n", __func__, - fdt_strerror(ret)); - return ret; - } - } - - return 0; -} - int k3_r5_falcon_prep(void) { struct spl_image_loader *loader, *drv; diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 24780eb6562..228b424d3f2 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <[email protected]>. * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -64,13 +64,13 @@ static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { "board_0_cpts0_rft_clk_out", "board_0_mcu_ext_refclk0_out", "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, - NULL, - NULL, - NULL, - NULL, - NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, "hsdiv4_16fft_mcu_2_hsdivout1_clk", "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", @@ -166,6 +166,31 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; +static const char * const usb0_serdes_refclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_refclk", + NULL, +}; + +static const char * const usb0_serdes_rxclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_rxclk", + NULL, +}; + +static const char * const usb0_serdes_rxfclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_rxfclk", + NULL, +}; + +static const char * const usb0_serdes_txfclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_txfclk", + NULL, +}; + +static const char * const usb0_serdes_txmclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_txmclk", + NULL, +}; + static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -197,18 +222,44 @@ static const char * const gtc_clk_mux_out0_parents[] = { "board_0_cpts0_rft_clk_out", "board_0_mcu_ext_refclk0_out", "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const pcien_cpts_rclk_mux_out1_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, - NULL, - NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, "hsdiv4_16fft_mcu_2_hsdivout1_clk", "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; +static const char * const serdes0_core_refclk_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", + "hsdiv4_16fft_main_3_hsdivout4_clk", + "hsdiv4_16fft_main_2_hsdivout4_clk", +}; + static const struct clk_data clk_list[] = { CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), @@ -270,11 +321,17 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_serdes0_refclk_n_out", 0, 0), + CLK_FIXED_RATE("board_0_serdes0_refclk_p_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane0_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane1_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane2_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane3_txclk", 0, 0), CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000), CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), @@ -294,8 +351,42 @@ static const struct clk_data clk_list[] = { CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_FIXED_RATE("usb3p0ss_16ffc_main_0_pipe_txclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_cmn_refclk_m", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_cmn_refclk_p", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip1_ln2_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_txmclk", 0, 0), CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_MUX("usb0_serdes_refclk_mux_out0", usb0_serdes_refclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_rxclk_mux_out0", usb0_serdes_rxclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_rxfclk_mux_out0", usb0_serdes_rxfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_txfclk_mux_out0", usb0_serdes_txfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_txmclk_mux_out0", usb0_serdes_txmclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0), @@ -310,14 +401,18 @@ static const struct clk_data clk_list[] = { CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682090, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683090, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0), CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("pcien_cpts_rclk_mux_out1", pcien_cpts_rclk_mux_out1_parents, 16, 0x108084, 0, 4, 0), + CLK_MUX("serdes0_core_refclk_out0", serdes0_core_refclk_out0_parents, 4, 0x108400, 0, 2, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), @@ -338,6 +433,11 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"), DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(61, 8, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(61, 9, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(61, 10, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(61, 13, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -349,6 +449,11 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 10, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(63, 11, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(63, 12, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(63, 13, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(63, 16, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), @@ -404,6 +509,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 324, "wiz16b8m4ct3_main_0_cmn_refclk_m"), + DEV_CLK(157, 326, "wiz16b8m4ct3_main_0_cmn_refclk_p"), DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 359, "dpi0_ext_clksel_out0"), DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"), @@ -461,6 +568,42 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"), DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(333, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(333, 2, "pcien_cpts_rclk_mux_out1"), + DEV_CLK(333, 3, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(333, 4, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(333, 5, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(333, 6, "board_0_cpts0_rft_clk_out"), + DEV_CLK(333, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(333, 8, "board_0_ext_refclk1_out"), + DEV_CLK(333, 9, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(333, 10, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(333, 11, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(333, 12, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(333, 15, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), + DEV_CLK(333, 17, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(333, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(333, 19, "wiz16b8m4ct3_main_0_ip2_ln0_refclk"), + DEV_CLK(333, 20, "wiz16b8m4ct3_main_0_ip2_ln0_rxclk"), + DEV_CLK(333, 21, "wiz16b8m4ct3_main_0_ip2_ln0_rxfclk"), + DEV_CLK(333, 23, "wiz16b8m4ct3_main_0_ip2_ln0_txfclk"), + DEV_CLK(333, 24, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(333, 25, "wiz16b8m4ct3_main_0_ip2_ln1_refclk"), + DEV_CLK(333, 26, "wiz16b8m4ct3_main_0_ip2_ln1_rxclk"), + DEV_CLK(333, 27, "wiz16b8m4ct3_main_0_ip2_ln1_rxfclk"), + DEV_CLK(333, 29, "wiz16b8m4ct3_main_0_ip2_ln1_txfclk"), + DEV_CLK(333, 30, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(333, 31, "wiz16b8m4ct3_main_0_ip2_ln2_refclk"), + DEV_CLK(333, 32, "wiz16b8m4ct3_main_0_ip2_ln2_rxclk"), + DEV_CLK(333, 33, "wiz16b8m4ct3_main_0_ip2_ln2_rxfclk"), + DEV_CLK(333, 35, "wiz16b8m4ct3_main_0_ip2_ln2_txfclk"), + DEV_CLK(333, 36, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(333, 37, "wiz16b8m4ct3_main_0_ip2_ln3_refclk"), + DEV_CLK(333, 38, "wiz16b8m4ct3_main_0_ip2_ln3_rxclk"), + DEV_CLK(333, 39, "wiz16b8m4ct3_main_0_ip2_ln3_rxfclk"), + DEV_CLK(333, 41, "wiz16b8m4ct3_main_0_ip2_ln3_txfclk"), + DEV_CLK(333, 42, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(333, 43, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"), DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"), @@ -473,11 +616,36 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"), DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 4, "usb0_serdes_refclk_mux_out0"), + DEV_CLK(398, 5, "wiz16b8m4ct3_main_0_ip3_ln3_refclk"), + DEV_CLK(398, 7, "usb0_serdes_rxclk_mux_out0"), + DEV_CLK(398, 8, "wiz16b8m4ct3_main_0_ip3_ln3_rxclk"), + DEV_CLK(398, 10, "usb0_serdes_rxfclk_mux_out0"), + DEV_CLK(398, 11, "wiz16b8m4ct3_main_0_ip3_ln3_rxfclk"), + DEV_CLK(398, 14, "usb0_serdes_txfclk_mux_out0"), + DEV_CLK(398, 15, "wiz16b8m4ct3_main_0_ip3_ln3_txfclk"), + DEV_CLK(398, 17, "usb0_serdes_txmclk_mux_out0"), + DEV_CLK(398, 18, "wiz16b8m4ct3_main_0_ip3_ln3_txmclk"), DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 21, "usb0_refclk_sel_out0"), DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"), DEV_CLK(398, 23, "board_0_hfosc1_clk_out"), DEV_CLK(398, 28, "board_0_tck_out"), + DEV_CLK(404, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(404, 3, "board_0_serdes0_refclk_n_out"), + DEV_CLK(404, 4, "board_0_serdes0_refclk_p_out"), + DEV_CLK(404, 5, "hsdiv4_16fft_main_3_hsdivout4_clk"), + DEV_CLK(404, 6, "serdes0_core_refclk_out0"), + DEV_CLK(404, 7, "gluelogic_hfosc0_clkout"), + DEV_CLK(404, 8, "board_0_hfosc1_clk_out"), + DEV_CLK(404, 9, "hsdiv4_16fft_main_3_hsdivout4_clk"), + DEV_CLK(404, 10, "hsdiv4_16fft_main_2_hsdivout4_clk"), + DEV_CLK(404, 39, "pcie_g3x4_128_main_1_pcie_lane0_txclk"), + DEV_CLK(404, 45, "pcie_g3x4_128_main_1_pcie_lane1_txclk"), + DEV_CLK(404, 51, "pcie_g3x4_128_main_1_pcie_lane2_txclk"), + DEV_CLK(404, 57, "pcie_g3x4_128_main_1_pcie_lane3_txclk"), + DEV_CLK(404, 81, "usb3p0ss_16ffc_main_0_pipe_txclk"), + DEV_CLK(404, 129, "board_0_tck_out"), }; const struct ti_k3_clk_platdata j784s4_clk_platdata = { diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index 19901821225..2bb1a88ab3b 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <[email protected]>. * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -21,10 +21,11 @@ static struct ti_pd soc_pd_list[] = { [1] = PSC_PD(3, &soc_psc_list[1], NULL), [2] = PSC_PD(0, &soc_psc_list[2], NULL), [3] = PSC_PD(1, &soc_psc_list[2], &soc_pd_list[2]), - [4] = PSC_PD(14, &soc_psc_list[2], NULL), - [5] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[4]), - [6] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[4]), - [7] = PSC_PD(38, &soc_psc_list[2], NULL), + [4] = PSC_PD(5, &soc_psc_list[2], NULL), + [5] = PSC_PD(14, &soc_psc_list[2], NULL), + [6] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[5]), + [7] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[5]), + [8] = PSC_PD(38, &soc_psc_list[2], NULL), }; static struct ti_lpsc soc_lpsc_list[] = { @@ -44,13 +45,15 @@ static struct ti_lpsc soc_lpsc_list[] = { [13] = PSC_LPSC(20, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [14] = PSC_LPSC(23, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), - [16] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), - [17] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), - [18] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[4], NULL), - [19] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[5], &soc_lpsc_list[18]), - [20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]), - [21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]), - [22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL), + [16] = PSC_LPSC(29, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), + [17] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), + [18] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), + [19] = PSC_LPSC(64, &soc_psc_list[2], &soc_pd_list[4], NULL), + [20] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[5], NULL), + [21] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[20]), + [22] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[20]), + [23] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[8], &soc_lpsc_list[24]), + [24] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[8], NULL), }; static struct ti_dev soc_dev_list[] = { @@ -78,14 +81,16 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(398, &soc_lpsc_list[13]), PSC_DEV(141, &soc_lpsc_list[14]), PSC_DEV(140, &soc_lpsc_list[15]), - PSC_DEV(146, &soc_lpsc_list[16]), - PSC_DEV(392, &soc_lpsc_list[17]), - PSC_DEV(395, &soc_lpsc_list[17]), - PSC_DEV(198, &soc_lpsc_list[18]), - PSC_DEV(202, &soc_lpsc_list[19]), - PSC_DEV(203, &soc_lpsc_list[20]), - PSC_DEV(133, &soc_lpsc_list[21]), - PSC_DEV(193, &soc_lpsc_list[22]), + PSC_DEV(333, &soc_lpsc_list[16]), + PSC_DEV(146, &soc_lpsc_list[17]), + PSC_DEV(392, &soc_lpsc_list[18]), + PSC_DEV(395, &soc_lpsc_list[18]), + PSC_DEV(404, &soc_lpsc_list[19]), + PSC_DEV(198, &soc_lpsc_list[20]), + PSC_DEV(202, &soc_lpsc_list[21]), + PSC_DEV(203, &soc_lpsc_list[22]), + PSC_DEV(133, &soc_lpsc_list[23]), + PSC_DEV(193, &soc_lpsc_list[24]), }; const struct ti_k3_pd_platdata j784s4_pd_platdata = { diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index d1d2605b2cc..671a6cb1cad 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -93,6 +93,15 @@ config TARGET_MT8188 USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. +config TARGET_MT8195 + bool "MediaTek MT8195 SoC" + select ARM64 + help + The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 dual role, + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 + and LPDDR4 options. + config TARGET_MT8365 bool "MediaTek MT8365 SoC" select ARM64 @@ -130,6 +139,33 @@ config TARGET_MT8518 endchoice +if ARM64 + +config MTK_MEM_MAP_DDR_BASE_PHY + hex "DDR physical base address" + default 0x40000000 + help + Target-specific DDR physical base address. + +config MTK_MEM_MAP_DDR_SIZE + hex "DDR .size in mem_map" + default 0x200000000 if TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8188 || TARGET_MT8195 + default 0xc0000000 if TARGET_MT8365 + default 0x80000000 if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT8183 + default 0x40000000 if TARGET_MT7622 || TARGET_MT8512 + default 0x20000000 + help + Target-specific DDR region size in mem_map. + +config MTK_MEM_MAP_MMIO_SIZE + hex "MMIO .size in mem_map" + default 0x40000000 if TARGET_MT7622 || TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8512 + default 0x20000000 + help + Target-specific MMIO region size in mem_map. + +endif + config SYS_BOARD string "Board name" default "mt7622" if TARGET_MT7622 @@ -165,7 +201,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8195 default "lk=1" if TARGET_MT7623 config MTK_TZ_MOVABLE diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 44591bed6fa..d1f64d61ab9 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_ARM64) += armv8-mem-map.o obj-y += cpu.o obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o obj-$(CONFIG_XPL_BUILD) += spl.o @@ -13,6 +14,7 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8188) += mt8188/ +obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ obj-$(CONFIG_TARGET_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ diff --git a/arch/arm/mach-mediatek/armv8-mem-map.c b/arch/arm/mach-mediatek/armv8-mem-map.c new file mode 100644 index 00000000000..cbaa9b4c267 --- /dev/null +++ b/arch/arm/mach-mediatek/armv8-mem-map.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/armv8/mmu.h> + +static struct mm_region mediatek_mem_map[] = { + { + /* DDR */ + .virt = CONFIG_MTK_MEM_MAP_DDR_BASE_PHY, + .phys = CONFIG_MTK_MEM_MAP_DDR_BASE_PHY, + .size = CONFIG_MTK_MEM_MAP_DDR_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = CONFIG_MTK_MEM_MAP_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + } +}; + +struct mm_region *mem_map = mediatek_mem_map; diff --git a/arch/arm/mach-mediatek/init.h b/arch/arm/mach-mediatek/init.h deleted file mode 100644 index 1d896fbbf7e..00000000000 --- a/arch/arm/mach-mediatek/init.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef __MEDIATEK_INIT_H_ -#define __MEDIATEK_INIT_H_ - -extern int mtk_soc_early_init(void); - -#endif /* __MEDIATEK_INIT_H_ */ diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 368f2916224..a043ca87398 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -36,23 +36,3 @@ void reset_cpu(void) { psci_system_reset(); } - -static struct mm_region mt7622_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; -struct mm_region *mem_map = mt7622_mem_map; diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 3d6ba3f383c..8713889b92d 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -16,11 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; struct boot_argument *preloader_param; -int mtk_soc_early_init(void) -{ - return 0; -} - int dram_init(void) { u32 i; diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index 7cb8b72c364..ff027ed03ef 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -int mtk_pll_early_init(void) +static int mtk_pll_early_init(void) { unsigned long pll_rates[] = { [CLK_APMIXED_ARMPLL] = 1250000000, diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index 07da5897190..79afd6ce6be 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -30,24 +30,3 @@ void reset_cpu(void) { psci_system_reset(); } - -static struct mm_region mt7981_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7981_mem_map; diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index a521c95bd9d..1fe56b3f145 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -30,24 +30,3 @@ void reset_cpu(void) { psci_system_reset(); } - -static struct mm_region mt7986_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7986_mem_map; diff --git a/arch/arm/mach-mediatek/mt7987/init.c b/arch/arm/mach-mediatek/mt7987/init.c index 8b268297809..6364ab497f7 100644 --- a/arch/arm/mach-mediatek/mt7987/init.c +++ b/arch/arm/mach-mediatek/mt7987/init.c @@ -39,24 +39,3 @@ void reset_cpu(ulong addr) { psci_system_reset(); } - -static struct mm_region mt7987_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x200000000ULL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7987_mem_map; diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 8bdd3848d26..7ff843585ec 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -38,24 +38,3 @@ void reset_cpu(ulong addr) { psci_system_reset(); } - -static struct mm_region mt7988_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x200000000ULL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7988_mem_map; diff --git a/arch/arm/mach-mediatek/mt8183/init.c b/arch/arm/mach-mediatek/mt8183/init.c index 37243547da8..8dbf9c3df7e 100644 --- a/arch/arm/mach-mediatek/mt8183/init.c +++ b/arch/arm/mach-mediatek/mt8183/init.c @@ -37,16 +37,6 @@ int dram_init_banksize(void) return 0; } -int mtk_pll_early_init(void) -{ - return 0; -} - -int mtk_soc_early_init(void) -{ - return 0; -} - void reset_cpu(void) { psci_system_reset(); @@ -57,23 +47,3 @@ int print_cpuinfo(void) printf("CPU: MediaTek MT8183\n"); return 0; } - -static struct mm_region mt8183_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; -struct mm_region *mem_map = mt8183_mem_map; diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c index ed67150e611..9743e39d582 100644 --- a/arch/arm/mach-mediatek/mt8188/init.c +++ b/arch/arm/mach-mediatek/mt8188/init.c @@ -45,11 +45,6 @@ int dram_init_banksize(void) return 0; } -int mtk_soc_early_init(void) -{ - return 0; -} - void reset_cpu(void) { struct udevice *wdt; diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile new file mode 100644 index 00000000000..886ab7e4eb9 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c new file mode 100644 index 00000000000..0f68c589e9a --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 MediaTek Inc. + * Copyright (C) 2026 BayLibre, SAS + * Author: Julien Stephan <[email protected]> + * Chris-QJ Chen <[email protected]> + */ + +#include <asm/armv8/mmu.h> +#include <asm/system.h> +#include <dm/uclass.h> +#include <linux/sizes.h> +#include <wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + fdtdec_setup_mem_size_base(); + + /* + * Limit gd->ram_top not exceeding SZ_4G. Some periphals like mmc + * requires DMA buffer allocated below SZ_4G. + * + * Note: SZ_1M is for adjusting gd->relocaddr, the reserved memory for + * u-boot itself. + */ + if (gd->ram_base + gd->ram_size >= SZ_4G) + gd->mon_len = (gd->ram_base + gd->ram_size + SZ_1M) - SZ_4G; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_soc_early_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct udevice *wdt; + + if (IS_ENABLED(CONFIG_PSCI_RESET)) { + psci_system_reset(); + } else { + uclass_first_device(UCLASS_WDT, &wdt); + if (wdt) + wdt_expire_now(wdt, 0); + } +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8195\n"); + return 0; +} diff --git a/arch/arm/mach-mediatek/mt8365/init.c b/arch/arm/mach-mediatek/mt8365/init.c index 8f03ed28763..fb14a5a1902 100644 --- a/arch/arm/mach-mediatek/mt8365/init.c +++ b/arch/arm/mach-mediatek/mt8365/init.c @@ -26,11 +26,6 @@ int dram_init_banksize(void) return 0; } -int mtk_soc_early_init(void) -{ - return 0; -} - void reset_cpu(void) { struct udevice *wdt; diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index 3b48caf5196..361c589cbc2 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -59,24 +59,3 @@ int print_cpuinfo(void) debug("CPU: MediaTek MT8512\n"); return 0; } - -static struct mm_region mt8512_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8512_mem_map; diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 892bd441a33..1d925dd478a 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -40,7 +40,7 @@ int dram_init_banksize(void) return 0; } -int mtk_pll_early_init(void) +static int mtk_pll_early_init(void) { unsigned long pll_rates[] = { [CLK_APMIXED_ARMPLL] = 1300000000, @@ -94,23 +94,3 @@ int print_cpuinfo(void) printf("CPU: MediaTek MT8516\n"); return 0; } - -static struct mm_region mt8516_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; -struct mm_region *mem_map = mt8516_mem_map; diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index c04bcb63517..8fa1346021a 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -51,24 +51,3 @@ int print_cpuinfo(void) printf("CPU: MediaTek MT8518\n"); return 0; } - -static struct mm_region mt8518_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8518_mem_map; diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index 247d7ee6f1d..6f1ec052b95 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -9,7 +9,10 @@ #include <init.h> #include <spl.h> -#include "init.h" +__weak int mtk_soc_early_init(void) +{ + return 0; +} void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index 6535539184c..542792cad1b 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -10,13 +10,10 @@ #include <asm/arch/eth.h> #include <asm/arch/axg.h> #include <asm/arch/mem.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index dc4abe1e107..17722cb897d 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -12,13 +12,10 @@ #include <asm/arch/g12a.h> #include <asm/arch/mem.h> #include <asm/arch/meson-vpu.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index 0370ed57e20..d5c506df22b 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -11,14 +11,11 @@ #include <asm/arch/gx.h> #include <asm/arch/mem.h> #include <asm/arch/meson-vpu.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/armv8/mmu.h> #include <linux/printk.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index b76510ab452..4afaee234ea 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -74,7 +74,7 @@ config MV78230 config MV78260 bool select ARMADA_XP - imply CMD_SATA + imply SATA config MV78460 bool @@ -204,7 +204,7 @@ config TARGET_THEADORABLE bool "Support theadorable Armada XP" select BOARD_LATE_INIT if USB select MV78260 - imply CMD_SATA + imply SATA config TARGET_CONTROLCENTERDC bool "Support CONTROLCENTERDC" diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index c07dd68e6ce..1e989ac48ac 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -156,6 +156,43 @@ config SYS_DEFAULT_LPDDR2_TIMINGS endchoice +config SPL_AM33XX_MMCSD_MULTIPLE + bool "Support multiple locations of next boot phase" + depends on AM33XX + depends on SPL_SYS_MMCSD_RAW_MODE + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + help + The boot ROM on the am33xx looks for the first stage + bootloader at several hard-coded offsets in the mmc device + (0, 128K, 256K, 384K) and uses the first location which has + a valid header. This can be used to implement failsafe + update of that first stage (SPL). But in order for the + update of the whole bootloader to be failsafe, SPL must load + U-Boot proper from a location dependent on where SPL itself + was loaded from. This option allows you to specify four + different offsets corresponding to the different places + where SPL could have been loaded from. + +if SPL_AM33XX_MMCSD_MULTIPLE + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_0K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 0K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_128K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 128K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_256K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 256K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_384K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 384K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +endif + source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap5/Kconfig" diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 95b44c8b1e5..88fa59feaf1 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -318,3 +318,34 @@ static void tee_image_process(ulong tee_image, size_t tee_size) } U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, tee_image_process); #endif + +#ifdef CONFIG_SPL_AM33XX_MMCSD_MULTIPLE + +#define AM335X_TRACE_VECTOR2 0x4030CE44 + +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) +{ + u32 bits = *(u32 *)AM335X_TRACE_VECTOR2; + + bits &= 0xf000; + + /* + * The ROM code sets the "trial bit 3", bit 15, first, when + * attempting offset 0, then "trial bit 2", bit 14, when + * attempting offset 128K, and so on. If the tracing vector + * has completely unexpected contents, fall back to the + * raw_sect we were given. + */ + switch (bits) { + case 0x8000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_0K; break; + case 0xc000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_128K; break; + case 0xe000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_256K; break; + case 0xf000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_384K; break; + default: + printf("Warning: Unexpected trial bits 0x%04x in trace vector 2, falling back to 0x%lx\n", + bits, raw_sect); + } + + return raw_sect; +} +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 92bb4aa62f1..108713488af 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -8,7 +8,6 @@ config ROCKCHIP_PX30 select SUPPORT_TPL select SPL select TPL - select TPL_TINY_FRAMEWORK if TPL select TPL_HAVE_INIT_STACK if TPL imply SPL_SEPARATE_BSS imply SPL_SERIAL @@ -132,6 +131,7 @@ config ROCKCHIP_RK3288 select SPL select SUPPORT_TPL select FDT_64BIT + imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD @@ -284,7 +284,7 @@ config ROCKCHIP_RK3399 imply OF_LIBFDT_OVERLAY imply OF_LIVE imply OF_UPSTREAM - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply PHY_GIGE if GMAC_ROCKCHIP imply PRE_CONSOLE_BUFFER imply RNG_ROCKCHIP @@ -317,6 +317,49 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3506 + bool "Support Rockchip RK3506" + select CPU_V7A + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply BOOTSTD_FULL + imply DM_RNG + imply ENV_RELOC_GD_ENV_ADDR + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ARMV7_SET_CORTEX_SMPEN + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_ARCH_TIMER + imply SYSRESET + help + The Rockchip RK3506 is a ARM-based SoC with a tri-core Cortex-A7. + config ROCKCHIP_RK3528 bool "Support Rockchip RK3528" select ARM64 @@ -745,6 +788,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3506/Kconfig" source "arch/arm/mach-rockchip/rk3528/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rk3576/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 06fb527b21a..d3bc0689f89 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3506) += rk3506/ obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/ diff --git a/arch/arm/mach-rockchip/rk3506/Kconfig b/arch/arm/mach-rockchip/rk3506/Kconfig new file mode 100644 index 00000000000..92f187458c6 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/Kconfig @@ -0,0 +1,15 @@ +if ROCKCHIP_RK3506 + +config ROCKCHIP_BOOT_MODE_REG + default 0xff910200 + +config ROCKCHIP_STIMER_BASE + default 0xff980000 + +config SYS_SOC + default "rk3506" + +config SYS_CONFIG_NAME + default "rk3506_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3506/Makefile b/arch/arm/mach-rockchip/rk3506/Makefile new file mode 100644 index 00000000000..a1760bd0f0a --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += rk3506.o +obj-y += clk_rk3506.o +obj-y += syscon_rk3506.o diff --git a/arch/arm/mach-rockchip/rk3506/clk_rk3506.c b/arch/arm/mach-rockchip/rk3506/clk_rk3506.c new file mode 100644 index 00000000000..96723f403cf --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/clk_rk3506.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <asm/arch-rockchip/cru_rk3506.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3506_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return (void *)RK3506_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3506/rk3506.c b/arch/arm/mach-rockchip/rk3506/rk3506.c new file mode 100644 index 00000000000..2ed1dcc128e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/rk3506.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <misc.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> + +#define SGRF_BASE 0xff210000 + +#define FIREWALL_DDR_BASE 0xff5f0000 +#define FW_DDR_MST1_REG 0x24 +#define FW_DDR_MST2_REG 0x28 +#define FW_DDR_MST3_REG 0x2c + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ff480000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@ff480000", +}; + +void board_debug_uart_init(void) +{ +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Select non-secure OTPC */ + rk_clrreg(SGRF_BASE + 0x100, BIT(1)); + + /* Set the sdmmc/emmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xffff00ff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the fspi to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xff00ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the mac0 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xf0ffffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the mac1 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST2_REG); + writel(val & 0xfffffff0, FIREWALL_DDR_BASE + FW_DDR_MST2_REG); + + /* Set the otg1 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST3_REG); + writel(val & 0xfff0ffff, FIREWALL_DDR_BASE + FW_DDR_MST3_REG); + + return 0; +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +#define RK3506_OTP_CPU_CODE_OFFSET 0x02 +#define RK3506_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x06 */ + ret = misc_read(dev, RK3506_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3506J */ + ret = misc_read(dev, RK3506_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3506J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c b/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c new file mode 100644 index 00000000000..2548b0fa2d3 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3506_syscon_ids[] = { + { .compatible = "rockchip,rk3506-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_syscon) = { + .name = "rockchip_rk3506_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3506_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS index ee840396e8b..111fe0270df 100644 --- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS @@ -4,6 +4,12 @@ S: Maintained F: arch/arm/dts/rk3528-generic* F: configs/generic-rk3528_defconfig +NANOPI-ZERO2-RK3528 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3528-nanopi-zero2* +F: configs/nanopi-zero2-rk3528_defconfig + RADXA-E20C M: Jonas Karlman <[email protected]> S: Maintained diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 57ead0006f1..f9bfc445b85 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -49,21 +49,6 @@ void board_debug_uart_init(void) { } -u32 read_brom_bootsource_id(void) -{ - u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); - - /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE - * enum value to avoid having to create a larger boot_devices table. - */ - if (bootsource_id == 0x81) - return BROM_BOOTSOURCE_USB; - else if (bootsource_id > BROM_LAST_BOOTSOURCE) - log_debug("Unknown bootsource %x\n", bootsource_id); - - return bootsource_id; -} - int arch_cpu_init(void) { u32 val; diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index c2b96902d2d..2b1eafee37c 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -72,9 +72,15 @@ static struct mm_region rk3568_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x300000000, - .phys = 0x300000000, - .size = 0x0c0c00000, + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x300000000UL, + .phys = 0x300000000UL, + .size = 0x0c0c00000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index a1e8a7572fa..c17ba418ced 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -26,6 +26,9 @@ #define SYS_SGRF_SOC_CON15 0x005C #define SYS_SGRF_SOC_CON20 0x0070 +#define FW_PMU1SGRF_BASE 0x26003000 +#define PMU1SGRF_SLV_LOOKUP0 0x80 + #define FW_SYS_SGRF_BASE 0x26005000 #define SGRF_DOMAIN_CON1 0x4 #define SGRF_DOMAIN_CON2 0x8 @@ -140,6 +143,9 @@ int arch_cpu_init(void) if (!IS_ENABLED(CONFIG_SPL_BUILD)) return 0; + /* Allow pmu sram access for non-secure masters */ + writel(0xffff3fff, FW_PMU1SGRF_BASE + PMU1SGRF_SLV_LOOKUP0); + /* Set the emmc to access ddr memory */ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 60c16d2f32d..675f13ab66d 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -286,14 +286,15 @@ config TARGET_ROCK_5_ITX_RK3588 Powered by either 12V, ATX power-supply or PoE config TARGET_ROCK_5C_RK3588S - bool "Radxa ROCK 5C RK3588S2 board" + bool "Radxa ROCK 5C/5C Lite" help - Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer. + Radxa ROCK 5C/5C Lite is a Rockchip RK3588S2/RK3582 based SBC (Single + Board Computer) by Radxa. Specification: - Quad A76 and Quad A55 CPU - 6 TOPS NPU + Quad/Dual A76 and Quad A55 CPU + 6/5 TOPS NPU up to 32GB LPDDR4x RAM eMMC / SPI flash connector Micro SD Card slot diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 55d2caab4fe..eedce7b9b08 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_ARCH #include <dm.h> +#include <fdt_support.h> #include <misc.h> #include <spl.h> #include <asm/armv8/mmu.h> @@ -87,6 +88,24 @@ static struct mm_region rk3588_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x2fc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x3fc500000UL, + .phys = 0x3fc500000UL, + .size = 0x3a00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { .virt = 0x900000000, .phys = 0x900000000, .size = 0x150000000, @@ -211,8 +230,45 @@ int arch_cpu_init(void) } #endif +/* + * RK3588 has two known memory gaps when using 16+ GiB DRAM, + * [0x3fc000000, 0x3fc500000) and [0x3fff00000, 0x400000000). + * + * Remove the [0x3fc000000, 0x400000000) range to ensure OS does not + * use memory from these gaps when a DDR_MEM tag cannot be found. + */ + +#define DRAM_GAP_START 0x3FC000000 +#define DRAM_GAP_END 0x400000000 + +int rockchip_dram_init_banksize_fixup(struct bd_info *bd) +{ + size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + + if (ram_top > DRAM_GAP_START) { + bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + + if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { + bd->bi_dram[2].start = DRAM_GAP_END; + bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + } + } + + return 0; +} + #define RK3588_OTP_CPU_CODE_OFFSET 0x02 #define RK3588_OTP_SPECIFICATION_OFFSET 0x06 +#define RK3588_OTP_IP_STATE_OFFSET 0x1d + +#define FAIL_CPU_CLUSTER0 GENMASK(3, 0) +#define FAIL_CPU_CLUSTER1 GENMASK(5, 4) +#define FAIL_CPU_CLUSTER2 GENMASK(7, 6) +#define FAIL_GPU GENMASK(4, 1) +#define FAIL_RKVDEC0 BIT(6) +#define FAIL_RKVDEC1 BIT(7) +#define FAIL_RKVENC0 BIT(0) +#define FAIL_RKVENC1 BIT(2) int checkboard(void) { @@ -258,3 +314,207 @@ int checkboard(void) return 0; } + +static int fdt_path_del_node(void *fdt, const char *path) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(fdt, path); + if (nodeoffset < 0) + return nodeoffset; + + return fdt_del_node(fdt, nodeoffset); +} + +static int fdt_path_set_name(void *fdt, const char *path, const char *name) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(fdt, path); + if (nodeoffset < 0) + return nodeoffset; + + return fdt_set_name(fdt, nodeoffset, name); +} + +/* + * RK3582 is a variant of the RK3588S with some IP blocks disabled. What blocks + * are disabled/non-working is indicated by ip-state in OTP. ft_system_setup() + * is used to mark any cpu, gpu and/or vdec/venc node with status=fail as + * indicated by ip-state. Apply same policy as vendor U-Boot for RK3582, i.e. + * two big cpu cores, the gpu and one vdec/venc core is always failed. Enable + * OF_SYSTEM_SETUP to use the required DT fixups for RK3582 board variants. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + static const char * const cpu_node_names[] = { + "cpu@0", "cpu@100", "cpu@200", "cpu@300", + "cpu@400", "cpu@500", "cpu@600", "cpu@700", + }; + int parent, node, i, comp_len, len, ret; + bool cluster1_removed = false; + u8 cpu_code[2], ip_state[3]; + struct udevice *dev; + char soc_comp[16]; + const char *comp; + void *data; + + if (!IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) + return 0; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return -ENOSYS; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return ret; + } + + /* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */ + ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return ret; + } + + log_debug("cpu-code: %02x %02x\n", cpu_code[0], cpu_code[1]); + + /* only fail cores on rk3582 */ + if (!(cpu_code[0] == 0x35 && cpu_code[1] == 0x82)) + return 0; + + ret = misc_read(dev, RK3588_OTP_IP_STATE_OFFSET, &ip_state, 3); + if (ret < 0) { + log_err("Could not read ip-state, ret=%d\n", ret); + return ret; + } + + log_debug("ip-state: %02x %02x %02x (otp)\n", + ip_state[0], ip_state[1], ip_state[2]); + + /* policy: fail entire big core cluster when one or more core is bad */ + if (ip_state[0] & FAIL_CPU_CLUSTER1) + ip_state[0] |= FAIL_CPU_CLUSTER1; + if (ip_state[0] & FAIL_CPU_CLUSTER2) + ip_state[0] |= FAIL_CPU_CLUSTER2; + + /* policy: always fail one big core cluster on rk3582 */ + if (!(ip_state[0] & (FAIL_CPU_CLUSTER1 | FAIL_CPU_CLUSTER2))) + ip_state[0] |= FAIL_CPU_CLUSTER2; + + /* policy: always fail gpu on rk3582 */ + ip_state[1] |= FAIL_GPU; + + /* policy: always fail one rkvdec core on rk3582 */ + if (!(ip_state[1] & (FAIL_RKVDEC0 | FAIL_RKVDEC1))) + ip_state[1] |= FAIL_RKVDEC1; + + /* policy: always fail one rkvenc core on rk3582 */ + if (!(ip_state[2] & (FAIL_RKVENC0 | FAIL_RKVENC1))) + ip_state[2] |= FAIL_RKVENC1; + + log_debug("ip-state: %02x %02x %02x (policy)\n", + ip_state[0], ip_state[1], ip_state[2]); + + /* cpu cluster1: ip_state[0]: bit4~5 */ + if ((ip_state[0] & FAIL_CPU_CLUSTER1) == FAIL_CPU_CLUSTER1) { + log_debug("remove cpu-map cluster1\n"); + fdt_path_del_node(blob, "/cpus/cpu-map/cluster1"); + cluster1_removed = true; + } + + /* cpu cluster2: ip_state[0]: bit6~7 */ + if ((ip_state[0] & FAIL_CPU_CLUSTER2) == FAIL_CPU_CLUSTER2) { + log_debug("remove cpu-map cluster2\n"); + fdt_path_del_node(blob, "/cpus/cpu-map/cluster2"); + } else if (cluster1_removed) { + /* cluster nodes must be named in a continuous series */ + log_debug("rename cpu-map cluster2\n"); + fdt_path_set_name(blob, "/cpus/cpu-map/cluster2", "cluster1"); + } + + /* gpu: ip_state[1]: bit1~4 */ + if (ip_state[1] & FAIL_GPU) { + log_debug("fail gpu\n"); + fdt_status_fail_by_pathf(blob, "/gpu@fb000000"); + } + + /* rkvdec: ip_state[1]: bit6,7 */ + if (ip_state[1] & FAIL_RKVDEC0) { + log_debug("fail rkvdec0\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdc38000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdc38700"); + } + if (ip_state[1] & FAIL_RKVDEC1) { + log_debug("fail rkvdec1\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdc40000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdc40700"); + } + + /* rkvenc: ip_state[2]: bit0,2 */ + if (ip_state[2] & FAIL_RKVENC0) { + log_debug("fail rkvenc0\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdbd0000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdbdf000"); + } + if (ip_state[2] & FAIL_RKVENC1) { + log_debug("fail rkvenc1\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdbe0000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdbef000"); + } + + parent = fdt_path_offset(blob, "/cpus"); + if (parent < 0) { + log_err("Could not find /cpus, parent=%d\n", parent); + return parent; + } + + /* cpu: ip_state[0]: bit0~7 */ + for (i = 0; i < 8; i++) { + /* fail any bad cpu core */ + if (!(ip_state[0] & BIT(i))) + continue; + + node = fdt_subnode_offset(blob, parent, cpu_node_names[i]); + if (node >= 0) { + log_debug("fail cpu %s\n", cpu_node_names[i]); + fdt_status_fail(blob, node); + } else { + log_err("Could not find %s, node=%d\n", + cpu_node_names[i], node); + return node; + } + } + + node = fdt_path_offset(blob, "/"); + if (node < 0) { + log_err("Could not find /, node=%d\n", node); + return node; + } + + snprintf(soc_comp, sizeof(soc_comp), "rockchip,rk35%x", cpu_code[1]); + + for (i = 0, comp_len = 0; + (comp = fdt_stringlist_get(blob, node, "compatible", i, &len)); + i++) { + /* stop at soc compatible */ + if (!strcmp(comp, soc_comp) || + !strcmp(comp, "rockchip,rk3588s") || + !strcmp(comp, "rockchip,rk3588")) + break; + + log_debug("compatible[%d]: %s\n", i, comp); + comp_len += len + 1; + } + + /* truncate to only include board compatible */ + fdt_setprop_placeholder(blob, node, "compatible", comp_len, &data); + + /* append soc compatible */ + fdt_appendprop_string(blob, node, "compatible", soc_comp); + fdt_appendprop_string(blob, node, "compatible", "rockchip,rk3588s"); + + return 0; +} diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index d560f90e873..ea0e3621af7 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -289,6 +289,11 @@ static int rockchip_dram_init_banksize(void) } #endif +__weak int rockchip_dram_init_banksize_fixup(struct bd_info *bd) +{ + return 0; +} + int dram_init_banksize(void) { size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE); @@ -342,7 +347,7 @@ int dram_init_banksize(void) #endif #endif - return 0; + return rockchip_dram_init_banksize_fixup(gd->bd); } u8 rockchip_sdram_type(phys_addr_t reg) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 1ce3a3b0554..e989c148079 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include <binman_sym.h> #include <cpu_func.h> #include <debug_uart.h> #include <dm.h> @@ -10,6 +11,7 @@ #include <image.h> #include <init.h> #include <log.h> +#include <mapmem.h> #include <ram.h> #include <spl.h> #include <asm/arch-rockchip/bootrom.h> @@ -33,7 +35,17 @@ __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { __weak u32 read_brom_bootsource_id(void) { - return readl(BROM_BOOTSOURCE_ID_ADDR); + u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); + + /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE + * enum value to avoid having to create a larger boot_devices table. + */ + if (bootsource_id == 0x81) + return BROM_BOOTSOURCE_USB; + else if (bootsource_id > BROM_LAST_BOOTSOURCE) + log_debug("Unknown bootsource %x\n", bootsource_id); + + return bootsource_id; } const char *board_spl_was_booted_from(void) @@ -140,3 +152,52 @@ void spl_board_prepare_for_boot(void) cleanup_before_linux(); } + +#if CONFIG_IS_ENABLED(RAM_DEVICE) && IS_ENABLED(CONFIG_SPL_LOAD_FIT) +binman_sym_declare_optional(ulong, payload, image_pos); +binman_sym_declare_optional(ulong, payload, size); + +static ulong ramboot_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + ulong addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT, + CONFIG_SPL_LOAD_FIT_ADDRESS); + + memcpy(buf, map_sysmem(addr + sector, 0), count); + return count; +} + +static int ramboot_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + struct legacy_img_hdr *header; + ulong addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT, + CONFIG_SPL_LOAD_FIT_ADDRESS); + ulong image_pos = binman_sym(ulong, payload, image_pos); + ulong size = binman_sym(ulong, payload, size); + + if (addr == CFG_SYS_SDRAM_BASE || addr == CONFIG_SPL_TEXT_BASE) + return -ENODEV; + + if (image_pos != BINMAN_SYM_MISSING && size != BINMAN_SYM_MISSING) { + header = map_sysmem(image_pos, 0); + if (image_get_magic(header) == FDT_MAGIC) { + memmove(map_sysmem(addr, 0), header, size); + memset(header, 0, sizeof(*header)); + } + } + + header = map_sysmem(addr, 0); + if (image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + spl_load_init(&load, ramboot_load_read, NULL, 1); + return spl_load_simple_fit(spl_image, &load, 0, header); + } + + return -ENODEV; +} + +/* Use priority and method name that sort before default spl_ram_load_image */ +SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, ramboot_load_image); +#endif diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index 1486656b36b..774c69091ee 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -41,7 +41,6 @@ config SC59X_64 select COMMON_CLK_ADI_SC598 select GICV3 select GICV3_SUPPORT_GIC600 - select GIC_600_CLEAR_RDPD select MMC_SDHCI_ADMA_FORCE_32BIT select NOP_PHY if PHY diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f2e959b5662..aec0fb7b1c8 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,15 +1,15 @@ if ARCH_SOCFPGA config ERR_PTR_OFFSET - default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range + default 0xfffec000 if ARCH_SOCFPGA_GEN5 # Boot ROM range config NR_DRAM_BANKS default 1 config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" - depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ - TARGET_SOCFPGA_AGILEX5 + depends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \ + ARCH_SOCFPGA_AGILEX5 select FIT_IMAGE_POST_PROCESS select SHA384 select SHA512 @@ -23,32 +23,32 @@ config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE depends on SOCFPGA_SECURE_VAB_AUTH config SPL_SIZE_LIMIT - default 0x10000 if TARGET_SOCFPGA_GEN5 + default 0x10000 if ARCH_SOCFPGA_GEN5 config SPL_SIZE_LIMIT_PROVIDE_STACK - default 0x200 if TARGET_SOCFPGA_GEN5 + default 0x200 if ARCH_SOCFPGA_GEN5 config SPL_STACK_R_ADDR - default 0x00800000 if TARGET_SOCFPGA_GEN5 + default 0x00800000 if ARCH_SOCFPGA_GEN5 config SPL_SYS_MALLOC_F - default y if TARGET_SOCFPGA_GEN5 + default y if ARCH_SOCFPGA_GEN5 config SPL_SYS_MALLOC_F_LEN - default 0x800 if TARGET_SOCFPGA_GEN5 + default 0x800 if ARCH_SOCFPGA_GEN5 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 config SYS_MALLOC_F_LEN - default 0x2000 if TARGET_SOCFPGA_ARRIA10 - default 0x2000 if TARGET_SOCFPGA_GEN5 + default 0x2000 if ARCH_SOCFPGA_ARRIA10 + default 0x2000 if ARCH_SOCFPGA_GEN5 config TEXT_BASE - default 0x01000040 if TARGET_SOCFPGA_ARRIA10 - default 0x01000040 if TARGET_SOCFPGA_GEN5 + default 0x01000040 if ARCH_SOCFPGA_ARRIA10 + default 0x01000040 if ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_AGILEX +config ARCH_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -58,9 +58,9 @@ config TARGET_SOCFPGA_AGILEX select GICV2 select NCORE_CACHE select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX7M +config ARCH_SOCFPGA_AGILEX7M bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -70,21 +70,21 @@ config TARGET_SOCFPGA_AGILEX7M select GICV2 select NCORE_CACHE select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX5 +config ARCH_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_ARRIA5 +config ARCH_SOCFPGA_ARRIA5 bool - select TARGET_SOCFPGA_GEN5 + select ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_ARRIA10 +config ARCH_SOCFPGA_ARRIA10 bool select GICV2 select SPL_ALTERA_SDRAM @@ -105,17 +105,17 @@ config TARGET_SOCFPGA_ARRIA10 config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM bool "Always reprogram Arria 10 FPGA" - depends on TARGET_SOCFPGA_ARRIA10 + depends on ARCH_SOCFPGA_ARRIA10 help Arria 10 FPGA is only programmed during the cold boot. This option forces the FPGA to be reprogrammed every reboot, allowing to change the bitstream and apply it with warm reboot. -config TARGET_SOCFPGA_CYCLONE5 +config ARCH_SOCFPGA_CYCLONE5 bool - select TARGET_SOCFPGA_GEN5 + select ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_GEN5 +config ARCH_SOCFPGA_GEN5 bool select SPL_ALTERA_SDRAM imply FPGA_SOCFPGA @@ -125,7 +125,7 @@ config TARGET_SOCFPGA_GEN5 imply SPL_SYS_MALLOC_SIMPLE imply SPL_USE_TINY_PRINTF -config TARGET_SOCFPGA_N5X +config ARCH_SOCFPGA_N5X bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -135,23 +135,23 @@ config TARGET_SOCFPGA_N5X select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 config TARGET_SOCFPGA_N5X_SOCDK bool "Intel eASIC SoCDK (N5X)" - select TARGET_SOCFPGA_N5X + select ARCH_SOCFPGA_N5X -config TARGET_SOCFPGA_SOC64 +config ARCH_SOCFPGA_SOC64 bool -config TARGET_SOCFPGA_STRATIX10 +config ARCH_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX select GICV2 - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 choice prompt "Altera SOCFPGA board select" @@ -159,85 +159,93 @@ choice config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" - select TARGET_SOCFPGA_AGILEX + select ARCH_SOCFPGA_AGILEX config TARGET_SOCFPGA_AGILEX7M_SOCDK bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" - select TARGET_SOCFPGA_AGILEX7M + select ARCH_SOCFPGA_AGILEX7M config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" - select TARGET_SOCFPGA_AGILEX5 + select ARCH_SOCFPGA_AGILEX5 config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" - select TARGET_SOCFPGA_ARRIA10 + select ARCH_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_ARRIA5_SECU1 bool "ABB SECU1 (Arria V)" - select TARGET_SOCFPGA_ARRIA5 + select ARCH_SOCFPGA_ARRIA5 select VENDOR_KM config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" - select TARGET_SOCFPGA_ARRIA5 + select ARCH_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_CHAMELEONV3 bool "Google Chameleon v3 (Arria 10)" - select TARGET_SOCFPGA_ARRIA10 + select ARCH_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 bool "Devboards DBM-SoC1 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_EBV_SOCRATES bool "EBV SoCrates (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_SOFTING_VINING_FPGA bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_SR1500 bool "SR1500 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_STRATIX10_SOCDK bool "Intel SOCFPGA SoCDK (Stratix 10)" - select TARGET_SOCFPGA_STRATIX10 + select ARCH_SOCFPGA_STRATIX10 config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE10_NANO bool "Terasic DE10-Nano (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE10_STANDARD bool "Terasic DE10-Standard (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE1_SOC bool "Terasic DE1-SoC (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_CORECOURSE_AC501SOC + bool "CoreCourse AC501SoC (Cyclone V)" + select ARCH_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_CORECOURSE_AC550SOC + bool "CoreCourse AC550SoC (Cyclone V)" + select ARCH_SOCFPGA_CYCLONE5 endchoice @@ -263,6 +271,8 @@ config SYS_BOARD default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK @@ -284,6 +294,8 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_SOC default "socfpga" @@ -310,5 +322,7 @@ config SYS_CONFIG_NAME default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "socfpga_ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 4e85bfb00d4..b6f35ddacc4 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,7 +10,7 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o obj-y += misc_gen5.o obj-y += reset_manager_gen5.o @@ -21,14 +21,14 @@ obj-y += wrap_pll_config.o obj-y += fpga_manager.o endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o endif -ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -41,7 +41,7 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX +ifdef CONFIG_ARCH_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -57,7 +57,7 @@ obj-y += wrap_pll_config_soc64.o obj-y += altera-sysmgr.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +ifdef CONFIG_ARCH_SOCFPGA_AGILEX5 obj-y += clock_manager_agilex5.o obj-y += mailbox_s10.o obj-y += misc_soc64.o @@ -73,7 +73,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M obj-y += clock_manager_agilex.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -89,7 +89,7 @@ obj-y += wrap_pll_config_soc64.o obj-y += altera-sysmgr.o endif -ifdef CONFIG_TARGET_SOCFPGA_N5X +ifdef CONFIG_ARCH_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -105,34 +105,34 @@ obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_XPL_BUILD -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 obj-y += spl_gen5.o obj-y += freeze_controller.o obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif -ifdef CONFIG_TARGET_SOCFPGA_SOC64 +ifdef CONFIG_ARCH_SOCFPGA_SOC64 obj-y += firewall.o obj-y += spl_soc64.o endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif -ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 obj-y += spl_s10.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX +ifdef CONFIG_ARCH_SOCFPGA_AGILEX obj-y += spl_agilex.o endif -ifdef CONFIG_TARGET_SOCFPGA_N5X +ifdef CONFIG_ARCH_SOCFPGA_N5X obj-y += spl_n5x.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +ifdef CONFIG_ARCH_SOCFPGA_AGILEX5 obj-y += spl_soc64.o obj-y += spl_agilex5.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M obj-y += spl_agilex7m.o endif else @@ -140,7 +140,7 @@ obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o endif -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 # QTS-generated config file wrappers CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7f65aed4540..4d7f0b9a79c 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -61,7 +61,7 @@ int board_init(void) int dram_init_banksize(void) { -#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #ifndef CONFIG_SPL_BUILD struct spl_handoff *ho; @@ -72,7 +72,7 @@ int dram_init_banksize(void) #endif #else fdtdec_setup_memory_banksize(); -#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ +#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */ return 0; } @@ -145,7 +145,7 @@ u8 socfpga_get_board_id(void) return board_id; } -#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64) int board_fit_config_name_match(const char *name) { char board_name[10]; diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 134eaf08e0a..da71f5759db 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -18,7 +18,7 @@ void cm_wait_for_lock(u32 mask) u32 inter_val; u32 retry = 0; do { -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) inter_val = readl(socfpga_get_clkmgr_addr() + CLKMGR_INTER) & mask; #else @@ -45,7 +45,7 @@ int cm_wait_for_fsm(void) int set_cpu_clk_info(void) { -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) /* Calculate the clock frequencies required for drivers */ cm_get_l4_sp_clk_hz(); cm_get_mmc_controller_clk_hz(); @@ -54,7 +54,7 @@ int set_cpu_clk_info(void) gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; #else gd->bd->bi_ddr_freq = 0; @@ -63,7 +63,7 @@ int set_cpu_clk_info(void) return 0; } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz) { u32 reg; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 9987d5bcee6..95c7f044952 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -10,12 +10,9 @@ #include <malloc.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dt-bindings/clock/agilex-clock.h> -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c index 7ec28d91ef3..fa068a9eeb1 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex5.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -14,7 +14,6 @@ #include <stdio.h> #include <time.h> #include <vsprintf.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/kernel.h> #include <linux/string.h> @@ -23,8 +22,6 @@ #include <asm/arch/system_manager.h> #include <dt-bindings/clock/agilex5-clock.h> -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c index c4c071330fc..8e47b4b8f5b 100644 --- a/arch/arm/mach-socfpga/clock_manager_n5x.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -6,15 +6,12 @@ #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <clk.h> #include <dm.h> #include <dt-bindings/clock/n5x-clock.h> #include <malloc.h> -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 1e148947a33..fd27470f967 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -4,15 +4,14 @@ * */ +#include <compiler.h> +#include <dm/device.h> #include <linux/errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> #include <asm/arch/handoff_soc64.h> #include <asm/arch/system_manager.h> -DECLARE_GLOBAL_DATA_PTR; - /* * function to write the bypass register which requires a poll of the * busy bit diff --git a/arch/arm/mach-socfpga/config.mk b/arch/arm/mach-socfpga/config.mk index 2290118f747..1ca1d33cb16 100644 --- a/arch/arm/mach-socfpga/config.mk +++ b/arch/arm/mach-socfpga/config.mk @@ -2,9 +2,9 @@ # # Brian Sune <[email protected]> -ifeq ($(CONFIG_TARGET_SOCFPGA_CYCLONE5),y) +ifeq ($(CONFIG_ARCH_SOCFPGA_CYCLONE5),y) archprepare: socfpga_g5_handoff_prepare -else ifeq ($(CONFIG_TARGET_SOCFPGA_ARRIA5),y) +else ifeq ($(CONFIG_ARCH_SOCFPGA_ARRIA5),y) archprepare: socfpga_g5_handoff_prepare endif @@ -23,7 +23,7 @@ socfpga_g5_handoff_prepare: if [ -z "$$VENDOR" ] || [ -z "$$BOARD" ]; then \ exit 0; \ fi; \ - BOARD_DIR=$(src)/board/$$VENDOR/$$BOARD; \ + BOARD_DIR=$(srctree)/board/$$VENDOR/$$BOARD; \ if [ "$$HANDOFF_PATH" ]; then \ echo "[INFO] Using manually specified handoff folder: $$HANDOFF_PATH"; \ else \ @@ -44,5 +44,5 @@ socfpga_g5_handoff_prepare: fi; \ echo "[INFO] Found hiof file: $$HIOF_FILE"; \ echo "[INFO] Running BSP generator..."; \ - python3 $(src)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \ + python3 $(srctree)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \ echo "[DONE] SoCFPGA QTS handoff conversion complete." diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 074b9691af8..61982c2d508 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -7,7 +7,7 @@ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ #define _SOCFPGA_SOC64_BASE_HARDWARE_H_ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOCFPGA_CCU_ADDRESS 0x1c000000 #define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000 #define SOCFPGA_SMMU_ADDRESS 0x16000000 @@ -47,9 +47,9 @@ #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 #define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 @@ -84,6 +84,6 @@ #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 #define GICD_BASE 0xfffc1000 #define GICC_BASE 0xfffc2000 -#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */ +#endif /* IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) */ #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index f0431c081d8..48001dbff21 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -17,22 +17,22 @@ void cm_print_clock_quick_summary(void); unsigned long cm_get_mpu_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); -#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +#if defined(CONFIG_ARCH_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz); #endif #endif -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include <asm/arch/clock_manager_gen5.h> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include <asm/arch/clock_manager_arria10.h> -#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#elif defined(CONFIG_ARCH_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #include <asm/arch/clock_manager_agilex.h> -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #include <asm/arch/clock_manager_agilex5.h> -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #include <asm/arch/clock_manager_n5x.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 2b436b64816..b47b577ae75 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -138,7 +138,7 @@ struct socfpga_firwall_l4_sys { #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index 481b66bbd86..fc084823b51 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -9,9 +9,9 @@ #include <altera.h> -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include <asm/arch/fpga_manager_gen5.h> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include <asm/arch/fpga_manager_arria10.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index b8f2f73e283..ae5af1f0100 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -19,7 +19,7 @@ #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 #else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 @@ -29,11 +29,11 @@ #define SOC64_HANDOFF_OFFSET_DATA 0x10 #define SOC64_HANDOFF_SIZE 4096 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634) /* DDR handoff */ #define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) @@ -43,9 +43,9 @@ #else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) #endif -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) @@ -76,17 +76,17 @@ #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) #define SOC64_HANDOFF_PERI_LEN 1 #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) #define SOC64_HANDOFF_SDRAM_LEN 5 #endif -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610) #else @@ -96,9 +96,9 @@ #define SOC64_HANDOFF_MUX_LEN 96 #define SOC64_HANDOFF_IOCTL_LEN 96 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 0b80e952131..5a6a76b5ace 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -24,7 +24,7 @@ void socfpga_fpga_add(void *fpga_desc); static inline void socfpga_fpga_add(void *fpga_desc) {} #endif -#ifdef CONFIG_TARGET_SOCFPGA_GEN5 +#ifdef CONFIG_ARCH_SOCFPGA_GEN5 void socfpga_sdram_remap_zero(void); static inline bool socfpga_is_booting_from_fpga(void) { @@ -35,14 +35,14 @@ static inline bool socfpga_is_booting_from_fpga(void) } #endif -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if defined(CONFIG_ARCH_SOCFPGA_STRATIX10) || \ + defined(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + defined(CONFIG_ARCH_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 1d68034cb55..97bb48474f3 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -39,11 +39,11 @@ void socfpga_per_reset_all(void); /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include <asm/arch/reset_manager_gen5.h> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include <asm/arch/reset_manager_arria10.h> -#elif defined(CONFIG_TARGET_SOCFPGA_SOC64) +#elif defined(CONFIG_ARCH_SOCFPGA_SOC64) #include <asm/arch/reset_manager_soc64.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 4b010be9ee8..5d72480dc13 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -39,7 +39,7 @@ void socfpga_bridges_reset(int enable, unsigned int mask); #define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ RSTMGR_STAT_L4WD0RST_BIT) diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 79cb9e6064a..9a261eb9383 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -7,9 +7,9 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include <asm/arch/sdram_gen5.h> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include <asm/arch/sdram_arria10.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 5603eaa3d02..3d5bd81e1b5 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -8,7 +8,7 @@ phys_addr_t socfpga_get_sysmgr_addr(void); -#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +#if defined(CONFIG_ARCH_SOCFPGA_SOC64) #include <asm/arch/system_manager_soc64.h> #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) @@ -85,9 +85,9 @@ phys_addr_t socfpga_get_sysmgr_addr(void); #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include <asm/arch/system_manager_gen5.h> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include <asm/arch/system_manager_arria10.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index f768a3a55cb..8be98d0ee46 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -12,7 +12,7 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SYSMGR_SOC64_SILICONID_1 0x00 #define SYSMGR_SOC64_SILICONID_2 0x04 #define SYSMGR_SOC64_MPU_STATUS 0x10 @@ -62,7 +62,7 @@ void populate_sysmgr_pinmux(void); #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE 0xb8 #else #define SYSMGR_SOC64_HMC_CLK 0xb4 @@ -73,7 +73,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 #define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) -#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ +#endif /*CONFIG_ARCH_SOCFPGA_AGILEX5*/ #define SYSMGR_SOC64_DMA 0x20 #define SYSMGR_SOC64_DMA_PERIPH 0x24 @@ -218,7 +218,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_WDDBG_PAUSE_ALL_CPU 0xFF0F0F0F -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE_MSK BIT(0) #endif diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index f9c34e85711..5e8768168d3 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -8,15 +8,12 @@ #include <asm/arch/mailbox_s10.h> #include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/secure.h> #include <asm/system.h> #include <hang.h> #include <wait_bit.h> -DECLARE_GLOBAL_DATA_PTR; - #define MBOX_READL(reg) \ readl(SOCFPGA_MAILBOX_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 07694107c8a..1eef7893e54 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,7 +54,7 @@ struct bsel bsel_str[] = { int dram_init(void) { -#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct spl_handoff *ho; ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); @@ -65,7 +65,7 @@ int dram_init(void) #else if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; -#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ +#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */ return 0; } @@ -261,21 +261,21 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) { ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); if (ret) hang(); } - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); - else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 5259ef54d73..ae33051c00f 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -6,7 +6,6 @@ #include <config.h> #include <cpu_func.h> #include <init.h> -#include <asm/global_data.h> #include <asm/io.h> #include <env.h> #include <errno.h> @@ -28,8 +27,6 @@ #include <dt-bindings/reset/altr,rst-mgr.h> -DECLARE_GLOBAL_DATA_PTR; - static struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 5222b384434..84f10844ee3 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -17,11 +17,8 @@ #include <asm/arch/system_manager.h> #include <asm/io.h> #include <asm/system.h> -#include <asm/global_data.h> #include <mach/clock_manager.h> -DECLARE_GLOBAL_DATA_PTR; - /* Agilex5 Sub Device Jtag ID List */ #define A3690_JTAG_ID 0x036090DD #define A3694_JTAG_ID 0x436090DD @@ -94,7 +91,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, int print_cpuinfo(void) { printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 1dc44ab4797..9f68d12351f 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -5,11 +5,8 @@ */ #include <asm/armv8/mmu.h> -#include <asm/global_data.h> -DECLARE_GLOBAL_DATA_PTR; - -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static struct mm_region socfpga_agilex5_mem_map[] = { { /* OCRAM 512KB */ diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index abb62a9b49f..b2b4077fd4b 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -7,7 +7,6 @@ #include <errno.h> #include <hang.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/secure.h> #include <asm/arch/reset_manager.h> @@ -20,8 +19,6 @@ #include <linux/intel-smc.h> #include <wait_bit.h> -DECLARE_GLOBAL_DATA_PTR; - #define TIMEOUT_300MS 300 /* F2S manager registers */ @@ -79,7 +76,7 @@ static void socfpga_f2s_bridges_reset(int enable, unsigned int mask) u32 flaginstatus_idleack = 0; u32 flaginstatus_respempty = 0; - if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + if (CONFIG_IS_ENABLED(ARCH_SOCFPGA_STRATIX10)) { /* Support fpga2soc and f2sdram */ brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | RSTMGR_BRGMODRST_F2SDRAM0_MASK | diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 48f258a37b4..53a9aa55f80 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -7,7 +7,6 @@ #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/utils.h> #include <hang.h> @@ -22,8 +21,6 @@ #include <wdt.h> #include <dm/uclass.h> -DECLARE_GLOBAL_DATA_PTR; - u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 1be347360f5..2c3e40b664a 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -6,7 +6,6 @@ */ #include <init.h> -#include <asm/global_data.h> #include <asm/io.h> #include <hang.h> #include <spl.h> @@ -19,8 +18,6 @@ #include <wdt.h> #include <dm/uclass.h> -DECLARE_GLOBAL_DATA_PTR; - u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ diff --git a/arch/arm/mach-socfpga/spl_agilex7m.c b/arch/arm/mach-socfpga/spl_agilex7m.c index 90065ccee6f..7371202a712 100644 --- a/arch/arm/mach-socfpga/spl_agilex7m.c +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -15,14 +15,11 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <dm/uclass.h> -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index df79cfe0f7f..08b756db2ca 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -6,7 +6,6 @@ #include <hang.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/utils.h> #include <image.h> @@ -25,8 +24,6 @@ #include <dm/uclass.h> #include <linux/bitops.h> -DECLARE_GLOBAL_DATA_PTR; - u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 81283ef7162..a49be837921 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -10,7 +10,6 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/utils.h> #include <dm/uclass.h> @@ -20,8 +19,6 @@ #include <spl.h> #include <watchdog.h> -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index fa83ff96adc..a0d3c96d456 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -7,7 +7,6 @@ #include <hang.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/utils.h> #include <debug_uart.h> @@ -22,8 +21,6 @@ #include <watchdog.h> #include <dm/uclass.h> -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 913f93c8f94..2f2ac9330ee 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -6,13 +6,11 @@ #include <asm/arch/handoff_soc64.h> #include <asm/arch/system_manager.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/bitfield.h> -DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) /* * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse * generation and setting PORT_OVERCURRENT bit so that until we turn on the @@ -39,7 +37,7 @@ void sysmgr_pinmux_init(void) populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sysmgr_config_usb3(); #endif } diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 7105cdc4905..ecde90f76f4 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -29,13 +29,13 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: case SOC64_HANDOFF_MAGIC_SDRAM: -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) case SOC64_HANDOFF_MAGIC_PERI: #else case SOC64_HANDOFF_MAGIC_MISC: #endif return BIG_ENDIAN; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: debug("%s: umctl2 handoff data\n", __func__); return LITTLE_ENDIAN; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 490097e98be..647e0a4c2bf 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -3,6 +3,7 @@ config CMD_STM32PROG select DFU select DFU_RAM select DFU_VIRT + select EFI_PARTITION select PARTITION_TYPE_GUID imply CMD_GPT if MMC imply CMD_MTD if MTD diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e979ee4a2cc..89f0e77bcdb 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -118,6 +118,13 @@ config DRAM_SUNXI_MR14 help MR14 value from vendor DRAM settings. +config DRAM_SUNXI_MR22 + hex "DRAM MR22 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + MR22 value from vendor DRAM settings. + config DRAM_SUNXI_TPR0 hex "DRAM TPR0 parameter" default 0x0 @@ -1232,6 +1239,24 @@ config CHIP_DIP_SCAN select W1_EEPROM_DS24XXX select CMD_EXTENSION +config SPL_SUNXI_LED_STATUS + bool "Control GPIO status LED within SPL" + depends on SPL_GPIO && SUNXI_GPIO + +if SPL_SUNXI_LED_STATUS + +config SPL_SUNXI_LED_STATUS_BIT + int "GPIO number for GPIO status LED" + help + GPIO number for the GPIO controlling the GPIO status LED in SPL. + +config SPL_SUNXI_LED_STATUS_STATE + bool "GPIO status LED initial state is on" + help + Whether the initial state of the status LED in SPL must be on or off. + +endif # SPL_SUNXI_LED_STATUS + source "board/sunxi/Kconfig" endif diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c index 1496f99624d..ca3e2513c69 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -426,8 +426,8 @@ static void mctl_drive_odt_config(const struct dram_para *para) writel_relaxed(val, base); if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { - if (para->tpr3 & 0x1f1f1f1f) - val = (para->tpr3 >> (i * 8)) & 0x1f; + if (para->tpr1 & 0x1f1f1f1f) + val = (para->tpr1 >> (i * 8)) & 0x1f; else val = 4; } @@ -468,7 +468,7 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para) u32 *ptr; if (para->tpr10 & BIT(31)) { - val = para->tpr2; + val = para->tpr0; } else { val = ((para->tpr10 << 1) & 0x1e) | ((para->tpr10 << 5) & 0x1e00) | @@ -781,7 +781,7 @@ static void mctl_dfi_init(const struct dram_para *para) mctl_mr_write_lpddr4(12, para->mr12); mctl_mr_write_lpddr4(13, para->mr13); mctl_mr_write_lpddr4(14, para->mr14); - mctl_mr_write_lpddr4(22, para->tpr1); + mctl_mr_write_lpddr4(22, para->mr22); break; } @@ -871,7 +871,24 @@ static inline void mctl_phy_dx_delay1_inner(u32 *base, u32 val1, u32 val2) writel_relaxed(val2, ptr + 48); } -static inline void mctl_phy_dx_delay0_inner(u32 *base1, u32 *base2, u32 val1, +static inline void mctl_phy_dx_delay0_inner0(u32 *base1, u32 *base2, u32 val1, + u32 val2) +{ + u32 *ptr = base1; + + for (int i = 0; i < 9; i++) { + writel_relaxed(val1, ptr); + writel_relaxed(val1, ptr + 0x30); + ptr += 2; + } + + writel_relaxed(val2, base2); + writel_relaxed(val2, base2 + 48); + writel_relaxed(val2, ptr); + writel_relaxed(val2, base2 + 24); +} + +static inline void mctl_phy_dx_delay0_inner1(u32 *base1, u32 *base2, u32 val1, u32 val2) { u32 *ptr = base1; @@ -915,6 +932,8 @@ static void mctl_phy_dx_delay_compensation(const struct dram_para *para) (para->tpr11 >> 24) & 0x3f, (para->para0 >> 24) & 0x3f); + dmb(); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); } @@ -922,25 +941,27 @@ static void mctl_phy_dx_delay_compensation(const struct dram_para *para) clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, BIT(7)); clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, BIT(2)); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), - para->tpr12 & 0x3f, - para->tpr14 & 0x3f); + mctl_phy_dx_delay0_inner0((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), + para->tpr12 & 0x3f, + para->tpr14 & 0x3f); + + mctl_phy_dx_delay0_inner1((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x52c), + (para->tpr12 >> 8) & 0x3f, + (para->tpr14 >> 8) & 0x3f); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x52c), - (para->tpr12 >> 8) & 0x3f, - (para->tpr14 >> 8) & 0x3f); + mctl_phy_dx_delay0_inner0((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6a8), + (para->tpr12 >> 16) & 0x3f, + (para->tpr14 >> 16) & 0x3f); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6a8), - (para->tpr12 >> 16) & 0x3f, - (para->tpr14 >> 16) & 0x3f); + mctl_phy_dx_delay0_inner1((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6ac), + (para->tpr12 >> 24) & 0x3f, + (para->tpr14 >> 24) & 0x3f); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6ac), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), - (para->tpr12 >> 24) & 0x3f, - (para->tpr14 >> 24) & 0x3f); + dmb(); setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, BIT(7)); } @@ -1161,7 +1182,6 @@ static const struct dram_para para = { #elif defined(CONFIG_SUNXI_DRAM_LPDDR4) .type = SUNXI_DRAM_TYPE_LPDDR4, #endif - /* TODO: Populate from config */ .dx_odt = CONFIG_DRAM_SUNXI_DX_ODT, .dx_dri = CONFIG_DRAM_SUNXI_DX_DRI, .ca_dri = CONFIG_DRAM_SUNXI_CA_DRI, @@ -1170,9 +1190,10 @@ static const struct dram_para para = { .mr12 = CONFIG_DRAM_SUNXI_MR12, .mr13 = CONFIG_DRAM_SUNXI_MR13, .mr14 = CONFIG_DRAM_SUNXI_MR14, + .mr22 = CONFIG_DRAM_SUNXI_MR22, + .tpr0 = CONFIG_DRAM_SUNXI_TPR0, .tpr1 = CONFIG_DRAM_SUNXI_TPR1, .tpr2 = CONFIG_DRAM_SUNXI_TPR2, - .tpr3 = CONFIG_DRAM_SUNXI_TPR3, .tpr6 = CONFIG_DRAM_SUNXI_TPR6, .tpr10 = CONFIG_DRAM_SUNXI_TPR10, .tpr11 = CONFIG_DRAM_SUNXI_TPR11, diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a7938ed7910..48617f3ea93 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -66,6 +66,7 @@ int tegra_get_chip_sku(void) switch (chip_id) { case CHIPID_TEGRA20: switch (sku_id) { + case SKU_ID_T20_A04: case SKU_ID_AP20: case SKU_ID_T20: case SKU_ID_AP20H: @@ -76,6 +77,9 @@ int tegra_get_chip_sku(void) case SKU_ID_AP25E: case SKU_ID_T25E: return TEGRA_SOC_T25; + default: + debug("%s: UNKNOWN Tegra20 SKU ID (0x%02x)\n", __func__, sku_id); + return TEGRA_SOC_T20; } break; case CHIPID_TEGRA30: @@ -83,7 +87,9 @@ int tegra_get_chip_sku(void) case SKU_ID_T33: case SKU_ID_T30: case SKU_ID_TM30MQS_P_A3: + return TEGRA_SOC_T30; default: + debug("%s: UNKNOWN Tegra30 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T30; } break; @@ -91,21 +97,27 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T114_ENG: case SKU_ID_T114_1: + return TEGRA_SOC_T114; default: + debug("%s: UNKNOWN Tegra114 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T114; } break; case CHIPID_TEGRA124: switch (sku_id) { case SKU_ID_T124_ENG: + return TEGRA_SOC_T124; default: + debug("%s: UNKNOWN Tegra124 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T124; } break; case CHIPID_TEGRA210: switch (sku_id) { case SKU_ID_T210_ENG: + return TEGRA_SOC_T210; default: + debug("%s: UNKNOWN Tegra210 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T210; } break; diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 3f968d4aeae..019c4b0b21f 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -5,14 +5,12 @@ #include <cpu_func.h> #include <log.h> -#include <asm/global_data.h> #include <linux/arm-smccc.h> #include <asm/io.h> #include <asm/arch-tegra/pmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch-tegra/tegra.h> #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) static bool tegra_pmc_detect_tz_only(void) diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig index 2a595151d6f..d1d8cbb815f 100644 --- a/arch/arm/mach-versal2/Kconfig +++ b/arch/arm/mach-versal2/Kconfig @@ -43,6 +43,9 @@ config SYS_MEM_RSVD_FOR_MMU config GICV3 def_bool y +config GICV3_SUPPORT_GIC600 + def_bool y + config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 2dfcadb369e..9a02fe40733 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -63,30 +63,69 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { } }; -void mem_map_fill(void) +/** + * mem_map_fill() - Populate global memory map with DRAM banks + * @bank_info: Array of memory regions parsed from device tree + * @num_banks: Number of valid DRAM banks in bank_info array + * + * Copies DRAM bank information into the global versal2_mem_map[] array + * starting at index VERSAL2_MEM_MAP_USED (5), which is after the fixed + * device mappings. This must be called early in boot before MMU + * initialization so that get_page_table_size() can calculate the + * required page table size based on actual memory configuration. + */ +void mem_map_fill(struct mm_region *bank_info, u32 num_banks) { int banks = VERSAL2_MEM_MAP_USED; - for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) - break; + for (int i = 0; i < num_banks; i++) { + if (banks > VERSAL2_MEM_MAP_MAX) + return; - versal2_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal2_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal2_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal2_mem_map[banks].virt = bank_info[i].phys; + versal2_mem_map[banks].phys = bank_info[i].phys; + versal2_mem_map[banks].size = bank_info[i].size; versal2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; } } +/** + * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info + * + * Transfers DRAM bank information from the global versal2_mem_map[] + * array to bd->bi_dram[] for passing memory configuration to the + * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical + * address and size are copied. + * + * This is called during dram_init_banksize() after the memory map + * has been populated by mem_map_fill() in dram_init(). Called after + * dram_init() but before kernel handoff. + */ +void fill_bd_mem_info(void) +{ + struct bd_info *bd = gd->bd; + int banks = VERSAL2_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (!versal2_mem_map[banks].size) + break; + + bd->bi_dram[i].start = versal2_mem_map[banks].phys; + bd->bi_dram[i].size = versal2_mem_map[banks].size; + banks++; + } +} + struct mm_region *mem_map = versal2_mem_map; +#if CONFIG_IS_ENABLED(SYS_MEM_RSVD_FOR_MMU) u64 get_page_table_size(void) { return 0x14000; } +#endif U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index 7b1726a7ef4..cee13488620 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -5,5 +5,7 @@ */ #include <linux/build_bug.h> +#include <asm/armv8/mmu.h> -void mem_map_fill(void); +void mem_map_fill(struct mm_region *bank_info, u32 num_banks); +void fill_bd_mem_info(void); diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 3dcff8076e3..7d65f3ea1a8 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -15,9 +15,6 @@ #include <bzlib.h> #include <watchdog.h> #include <asm/byteorder.h> -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -#endif DECLARE_GLOBAL_DATA_PTR; @@ -65,6 +62,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) bootstage_mark(BOOTSTAGE_ID_RUN_OS); + bootm_final(0); + /* * Linux Kernel Parameters (passing board info data): * sp+00: Ignore, side effect of using jsr to jump to kernel diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 4261e5009fd..16c55ddfd95 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -7,12 +7,8 @@ config SYS_ARCH config STATIC_RELA def_bool y -choice - prompt "Target select" - optional - config TARGET_MICROBLAZE_GENERIC - bool "Support microblaze-generic" + def_bool y select BOARD_LATE_INIT select DM select DM_SERIAL @@ -26,8 +22,8 @@ config TARGET_MICROBLAZE_GENERIC select MTD select SPI imply CMD_DM - -endchoice + help + Support microblaze-generic source "board/xilinx/Kconfig" source "board/xilinx/microblaze-generic/Kconfig" diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 4879a41aab3..b54c902602f 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -17,20 +17,15 @@ #include <image.h> #include <log.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <u-boot/zlib.h> #include <asm/byteorder.h> -DECLARE_GLOBAL_DATA_PTR; - static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*thekernel)(char *cmdline, ulong rd, ulong dt); ulong dt = (ulong)images->ft_addr; ulong rd_start = images->initrd_start; ulong cmdline = images->cmdline_start; - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - thekernel = (void (*)(char *, ulong, ulong))images->ep; debug("## Transferring control to Linux (at address 0x%08lx) ", @@ -39,13 +34,11 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) cmdline, rd_start, dt); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + bootm_final(flag); flush_cache_all(); - if (!fake) { + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) { /* * Linux Kernel Parameters (passing device tree): * r5: pointer to command line diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 87195100023..066c830f3fa 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -268,12 +268,7 @@ static void boot_jump_linux(struct bootm_headers *images) if (CONFIG_IS_ENABLED(MALTA)) linux_extra = gd->ram_size; -#if IS_ENABLED(CONFIG_BOOTSTAGE_FDT) - bootstage_fdt_add_report(); -#endif -#if IS_ENABLED(CONFIG_BOOTSTAGE_REPORT) - bootstage_report(); -#endif + bootm_final(0); if (CONFIG_IS_ENABLED(RESTORE_EXCEPTION_VECTOR_BASE)) trap_restore(); diff --git a/arch/mips/mach-ath79/qca956x/ddr.c b/arch/mips/mach-ath79/qca956x/ddr.c index 2e46e24f483..754e2573e37 100644 --- a/arch/mips/mach-ath79/qca956x/ddr.c +++ b/arch/mips/mach-ath79/qca956x/ddr.c @@ -5,7 +5,6 @@ * Based on QSDK */ -#include <asm/global_data.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> @@ -182,8 +181,6 @@ DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \ DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1) -DECLARE_GLOBAL_DATA_PTR; - void qca956x_ddr_init(void) { u32 ddr_config, ddr_config2, ddr_config3, mod_val, \ diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 22b1b98e0ef..8ae6fb9437a 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -4,7 +4,6 @@ */ #include <init.h> -#include <asm/global_data.h> #include <linux/bitops.h> #include <asm/io.h> @@ -14,8 +13,6 @@ #include <mach/tlb.h> #include <mach/ddr.h> -DECLARE_GLOBAL_DATA_PTR; - #if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c index e2e1760a646..5fc4e0c49e8 100644 --- a/arch/mips/mach-mtmips/ddr_cal.c +++ b/arch/mips/mach-mtmips/ddr_cal.c @@ -7,13 +7,10 @@ #include <asm/addrspace.h> #include <asm/cacheops.h> -#include <asm/global_data.h> #include <linux/bitops.h> #include <linux/io.h> #include <mach/mc.h> -DECLARE_GLOBAL_DATA_PTR; - #define COARSE_MIN_START 6 #define FINE_MIN_START 15 #define COARSE_MAX_START 7 diff --git a/arch/mips/mach-octeon/cvmx-pko.c b/arch/mips/mach-octeon/cvmx-pko.c index 8a9181362bd..432488f7815 100644 --- a/arch/mips/mach-octeon/cvmx-pko.c +++ b/arch/mips/mach-octeon/cvmx-pko.c @@ -52,8 +52,6 @@ #include <mach/cvmx-helper-pki.h> #include <mach/cvmx-helper-pko.h> -DECLARE_GLOBAL_DATA_PTR; - #define CVMX_PKO_NQ_PER_PORT_MAX 32 static cvmx_pko_return_value_t cvmx_pko2_config_port(short ipd_port, diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 71319839ba2..6004e83bf0c 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -10,9 +10,6 @@ #include <image.h> #include <irq_func.h> #include <log.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ @@ -44,6 +41,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; + bootm_final(0); + /* flushes data and instruction caches before calling the kernel */ disable_interrupts(); flush_dcache_all(); diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8ac83420ee2..0dc72c87423 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -73,6 +73,7 @@ config TARGET_KMTEPR2 config TARGET_GAZERBEAM bool "Support gazerbeam" select ARCH_MPC8308 + select REGMAP select SYS_FSL_ERRATUM_ESDHC111 imply ENV_IS_IN_FLASH help diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c5c2220593f..55152ab227e 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -93,7 +93,7 @@ config TARGET_P3041DS select ARCH_P3041 select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_NGPIXIS - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P4080DS @@ -102,7 +102,7 @@ config TARGET_P4080DS select ARCH_P4080 select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_NGPIXIS - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P5040DS @@ -112,7 +112,7 @@ config TARGET_P5040DS select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_NGPIXIS select SYS_FSL_RAID_ENGINE - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_MPC8548CDS @@ -129,7 +129,7 @@ config TARGET_P1010RDB_PA select SUPPORT_TPL select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P1010RDB_PB @@ -140,7 +140,7 @@ config TARGET_P1010RDB_PB select SUPPORT_TPL select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P1020RDB_PC @@ -150,7 +150,7 @@ config TARGET_P1020RDB_PC select ARCH_P1020 select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P1020RDB_PD @@ -160,7 +160,7 @@ config TARGET_P1020RDB_PD select ARCH_P1020 select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P2020RDB @@ -170,7 +170,7 @@ config TARGET_P2020RDB select ARCH_P2020 select SYS_L2_SIZE_512KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply SATA_SIL config TARGET_TURRIS_1X @@ -190,7 +190,7 @@ config TARGET_P2041RDB select FSL_CORENET select PHYS_64BIT select SYS_L3_SIZE_1024KB - imply CMD_SATA + imply SATA imply FSL_SATA config TARGET_QEMU_PPCE500 @@ -229,7 +229,7 @@ config TARGET_T2080QDS select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select FSL_DDR_INTERACTIVE select SYS_L3_SIZE_512KB - imply CMD_SATA + imply SATA config TARGET_T2080RDB bool "Support T2080RDB" @@ -238,7 +238,7 @@ config TARGET_T2080RDB select SUPPORT_SPL select PHYS_64BIT select SYS_L3_SIZE_512KB - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_T4240RDB @@ -248,7 +248,7 @@ config TARGET_T4240RDB select PHYS_64BIT select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select SYS_L3_SIZE_512KB - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_KMP204X @@ -405,7 +405,7 @@ config ARCH_MPC8536 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_REGINFO config ARCH_MPC8540 @@ -482,7 +482,7 @@ config ARCH_P1010 imply CMD_EEPROM imply CMD_MTDPARTS imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_PCI imply CMD_REGINFO imply FSL_SATA @@ -521,7 +521,7 @@ config ARCH_P1020 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_PCI imply CMD_REGINFO imply SATA_SIL @@ -543,7 +543,7 @@ config ARCH_P1021 select FSL_ELBC imply CMD_REGINFO imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_REGINFO imply SATA_SIL @@ -579,7 +579,7 @@ config ARCH_P1024 select FSL_ELBC imply CMD_EEPROM imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_PCI imply CMD_REGINFO imply SATA_SIL @@ -599,7 +599,7 @@ config ARCH_P1025 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC - imply CMD_SATA + imply SATA imply CMD_REGINFO config ARCH_P2020 @@ -687,7 +687,7 @@ config ARCH_P3041 select SYS_FSL_USB2_PHY_ENABLE select FSL_ELBC imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_REGINFO imply FSL_SATA @@ -730,7 +730,7 @@ config ARCH_P4080 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC - imply CMD_SATA + imply SATA imply CMD_REGINFO imply SATA_SIL @@ -761,7 +761,7 @@ config ARCH_P5040 select SYS_FSL_USB2_PHY_ENABLE select SYS_PPC64 select FSL_ELBC - imply CMD_SATA + imply SATA imply CMD_REGINFO imply FSL_SATA @@ -903,7 +903,7 @@ config ARCH_T2080 select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC - imply CMD_SATA + imply SATA imply CMD_NAND imply CMD_REGINFO imply FSL_SATA @@ -946,7 +946,7 @@ config ARCH_T4240 select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC - imply CMD_SATA + imply SATA imply CMD_NAND imply CMD_REGINFO imply FSL_SATA diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index dc44bf3ab3a..f9351a17a48 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -54,12 +54,7 @@ static void boot_jump_linux(struct bootm_headers *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); -#ifdef CONFIG_BOOTSTAGE_FDT - bootstage_fdt_add_report(); -#endif -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif + bootm_final(0); #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 79867656b15..ad7589123c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -17,6 +17,9 @@ config TARGET_ANDES_VOYAGER config TARGET_BANANAPI_F3 bool "Support BananaPi F3 Board" +config TARGET_BEAGLEBOARD_BEAGLEVFIRE + bool "Support BeagleBoard BeagleV-Fire Board (based on Microchip MPFS)" + config TARGET_K230_CANMV bool "Support K230 CanMV Board" @@ -106,6 +109,7 @@ config SPL_ZERO_MEM_BEFORE_USE source "board/andestech/ae350/Kconfig" source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" +source "board/beagle/beaglev_fire/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_generic/Kconfig" diff --git a/arch/riscv/cpu/andes/spl.c b/arch/riscv/cpu/andes/spl.c index a13dc4095a4..1e19fad9288 100644 --- a/arch/riscv/cpu/andes/spl.c +++ b/arch/riscv/cpu/andes/spl.c @@ -8,11 +8,8 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/system.h> -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(RAM_SUPPORT) struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) { diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c index 91007c0a3d3..5d7659887b9 100644 --- a/arch/riscv/cpu/cv1800b/dram.c +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -5,11 +5,8 @@ #include <fdtdec.h> #include <init.h> -#include <asm/global_data.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index c68209d8fb2..f2934cb33e7 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -39,6 +39,7 @@ config SIFIVE_FU540 imply PWM_SIFIVE imply DM_I2C imply SYS_I2C_OCORES + imply OF_UPSTREAM if ENV_IS_IN_SPI_FLASH diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index d7ca9687171..66f9a8d5fa5 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -40,6 +40,7 @@ config SIFIVE_FU740 imply DM_I2C imply SYS_I2C_OCORES imply SPL_I2C + imply OF_UPSTREAM if ENV_IS_IN_SPI_FLASH diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 91007c0a3d3..5d7659887b9 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -5,11 +5,8 @@ #include <fdtdec.h> #include <init.h> -#include <asm/global_data.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 87aaf865246..3aece7d995b 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -41,7 +41,7 @@ int spl_dram_init(void) /* Read the definition of the DDR size from eeprom, and if not, * use the definition in DT */ - size = (get_ddr_size_from_eeprom() >> 16) & 0xFF; + size = get_ddr_size_from_eeprom(); if (check_ddr_size(size)) gd->ram_size = size << 30; diff --git a/arch/riscv/cpu/k230/dram.c b/arch/riscv/cpu/k230/dram.c index b2d3e4fd6a9..5d7659887b9 100644 --- a/arch/riscv/cpu/k230/dram.c +++ b/arch/riscv/cpu/k230/dram.c @@ -3,13 +3,10 @@ * Copyright (C) 2018, Bin Meng <[email protected]> */ -#include <asm/global_data.h> #include <fdtdec.h> #include <init.h> #include <linux/sizes.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig index bcf1ede818b..8054313d182 100644 --- a/arch/riscv/cpu/mpfs/Kconfig +++ b/arch/riscv/cpu/mpfs/Kconfig @@ -6,8 +6,6 @@ config MICROCHIP_MPFS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CLINT if RISCV_MMODE - imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index b95470485f6..ceb934021d9 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu/th1520/spl.c @@ -10,8 +10,6 @@ #include <log.h> #include <init.h> -DECLARE_GLOBAL_DATA_PTR; - #define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220) #define TH1520_SUBSYS_CLK_VO_EN BIT(2) #define TH1520_SUBSYS_CLK_VI_EN BIT(1) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 9b347fc3b50..8e591cb7aa9 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,8 +9,6 @@ dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb -dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb -dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 360679a1781..19c7d6ccaca 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -7,11 +7,11 @@ / { cpus { - assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_COREPLL>; assigned-clock-rates = <1000000000>; bootph-pre-ram; cpu0: cpu@0 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; status = "okay"; cpu0_intc: interrupt-controller { @@ -19,28 +19,28 @@ }; }; cpu1: cpu@1 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu1_intc: interrupt-controller { bootph-pre-ram; }; }; cpu2: cpu@2 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu2_intc: interrupt-controller { bootph-pre-ram; }; }; cpu3: cpu@3 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu3_intc: interrupt-controller { bootph-pre-ram; }; }; cpu4: cpu@4 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu4_intc: interrupt-controller { bootph-pre-ram; @@ -80,7 +80,7 @@ reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; - clocks = <&prci PRCI_CLK_DDRPLL>; + clocks = <&prci FU540_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; bootph-pre-ram; }; @@ -100,7 +100,7 @@ }; ð0 { - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125000000>; }; diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi deleted file mode 100644 index 7db86105348..00000000000 --- a/arch/riscv/dts/fu540-c000.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -#include <dt-bindings/clock/sifive-fu540-prci.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <4>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - dma: dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; - #dma-cells = <1>; - }; - uart1: serial@10011000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <5>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <50>; - clocks = <&prci PRCI_CLK_TLCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <51>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi2: spi@10050000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <6>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - }; -}; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi deleted file mode 100644 index 7b77c13496d..00000000000 --- a/arch/riscv/dts/fu740-c000.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 SiFive, Inc */ - -/dts-v1/; - -#include <dt-bindings/clock/sifive-fu740-prci.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu740-c000", "sifive,fu740"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,bullet0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - reg = <0x0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x1>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x2>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x3>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x4>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - #address-cells = <0>; - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <69>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 0xffffffff>, - <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, - <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, - <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, - <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu740-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <39>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - uart1: serial@10011000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <40>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c1: i2c@10031000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10031000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <53>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000>, - <0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <41>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000>, - <0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <42>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - spi0: spi@10050000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <43>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <55>; - reg = <0x0 0x10090000 0x0 0x2000>, - <0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, - <&prci FU740_PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <44>, <45>, <46>, <47>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <48>, <49>, <50>, <51>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - ccache: cache-controller@2010000 { - compatible = "sifive,fu740-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <19>, <21>, <22>, <20>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>, <31>, <32>, <33>, <34>, <35>, <36>, - <37>, <38>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - pcie@e00000000 { - compatible = "sifive,fu740-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - reg = <0xe 0x00000000 0x0 0x80000000>, - <0xd 0xf0000000 0x0 0x10000000>, - <0x0 0x100d0000 0x0 0x1000>; - reg-names = "dbi", "config", "mgmt"; - device_type = "pci"; - dma-coherent; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ - <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ - <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ - num-lanes = <0x8>; - interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; - interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-parent = <&plic0>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, - <0x0 0x0 0x0 0x2 &plic0 58>, - <0x0 0x0 0x0 0x3 &plic0 59>, - <0x0 0x0 0x0 0x4 &plic0 60>; - clock-names = "pcie_aux"; - clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; - pwren-gpios = <&gpio 5 0>; - reset-gpios = <&gpio 8 0>; - resets = <&prci 4>; - status = "okay"; - }; - }; -}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts deleted file mode 100644 index 4a2729f5ca3..00000000000 --- a/arch/riscv/dts/hifive-unleashed-a00.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -#include "fu540-c000.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SiFive HiFive Unleashed A00"; - compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = <RTCCLK_FREQ>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - - soc { - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <RTCCLK_FREQ>; - clock-output-names = "rtcclk"; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&qspi2 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts deleted file mode 100644 index c4ed9efdff0..00000000000 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 SiFive, Inc */ - -#include "fu740-c000.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "SiFive HiFive Unmatched A00"; - compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", - "sifive,fu740"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = <RTCCLK_FREQ>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x4 0x00000000>; - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <RTCCLK_FREQ>; - clock-output-names = "rtcclk"; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - vcc-supply = <&vdd_bpro>; - interrupt-parent = <&gpio>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - }; - - eeprom@54 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x54>; - vcc-supply = <&vdd_bpro>; - label = "board-id"; - pagesize = <16>; - read-only; - size = <256>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - - regulators { - vdd_bcore: bcores-merged { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <4800000>; - regulator-max-microamp = <4800000>; - regulator-always-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2400000>; - regulator-max-microamp = <2400000>; - regulator-always-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1060000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <1500000>; - regulator-always-on; - }; - - vdd_bmem_bio: bmem-bio-merged { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ld09: ldo9 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spi0 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", - "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", - "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", - "EN_VDD_SD", "SD_CD"; -}; diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index 45ad2a5f7bc..8b689a75013 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -9,8 +9,19 @@ #include <linux/types.h> +/** + * get_pcb_revision_from_eeprom() - get the PCB revision + * + * @return: the PCB revision or 0 on error. + */ u8 get_pcb_revision_from_eeprom(void); -u32 get_ddr_size_from_eeprom(void); + +/** + * get_ddr_size_from_eeprom() - read DDR size from EEPROM + * + * @return: size in GiB or 0 on error. + */ +u8 get_ddr_size_from_eeprom(void); /** * get_mmc_size_from_eeprom() - read eMMC size from EEPROM diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h index 543a1688db8..3a8fdb57136 100644 --- a/arch/riscv/include/asm/u-boot-riscv.h +++ b/arch/riscv/include/asm/u-boot-riscv.h @@ -16,7 +16,6 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); -void board_quiesce_devices(void); int riscv_board_reserved_mem_fixup(void *fdt); int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt); diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 9544907ab1e..69c9ca5c487 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -25,39 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -__weak void board_quiesce_devices(void) -{ -} - -/** - * announce_and_cleanup() - Print message and prepare for kernel boot - * - * @fake: non-zero to do everything except actually boot - */ -static void announce_and_cleanup(int fake) -{ - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_FDT - bootstage_fdt_add_report(); -#endif -#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT) - bootstage_report(); -#endif - - board_quiesce_devices(); - - /* - * Call remove function of all devices with a removal flag set. - * This may be useful for last-stage operations, like cancelling - * of DMA operation or releasing device internal buffers. - */ - dm_remove_devices_active(); - - cleanup_before_linux(); -} - static void boot_prep_linux(struct bootm_headers *images) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && IS_ENABLED(CONFIG_LMB) && images->ft_len) { @@ -75,7 +42,6 @@ static void boot_prep_linux(struct bootm_headers *images) static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*kernel)(ulong hart, void *dtb); - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); #ifdef CONFIG_SMP int ret; #endif @@ -87,9 +53,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) debug("## Transferring control to kernel (at address %08lx) ...\n", (ulong)kernel); - announce_and_cleanup(fake); + bootm_final(flag); + cleanup_before_linux(); - if (!fake) { + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_SMP ret = smp_call_function(images->ep, diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index d74544b93d8..9a0519af494 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -41,8 +41,5 @@ static inline void probe_cache_device(struct driver *driver, struct udevice *dev void enable_caches(void) { - struct udevice *dev = NULL; - - probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); } #endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 762c1d9bbe2..ac92ebf1afd 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -46,6 +46,8 @@ mmc6 = "/mmc6"; mmc7 = "/mmc7"; mmc8 = "/mmc8"; + mmc9 = "/mmc9"; + mmc10 = "/mmc10"; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; @@ -1279,6 +1281,13 @@ filename = "mmc9.img"; }; + /* This is used for RAUC boot tests */ + mmc10 { + status = "disabled"; + compatible = "sandbox,mmc"; + filename = "mmc10.img"; + }; + pch { compatible = "sandbox,pch"; }; diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index 44ba8b52e13..7a5f6f7d36e 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -73,6 +73,7 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { bootstage_mark(BOOTSTAGE_ID_RUN_OS); + bootm_final(flag); printf("## Transferring control to Linux (at address %08lx)...\n", images->ep); printf("sandbox: continuing, as we cannot run Linux\n"); diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index bb0f59e0aa2..81d5957edaa 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -13,11 +13,8 @@ #include <env.h> #include <image.h> #include <asm/byteorder.h> -#include <asm/global_data.h> #include <asm/zimage.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SH_SDRAM_OFFSET #define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET) #else @@ -95,6 +92,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) images->rd_end - images->rd_start); } + bootm_final(0); + /* Boot kernel */ kernel(); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 48b033e7e27..8bf5a300d1f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -130,9 +130,6 @@ source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below -config AHCI - default y - config RAMBASE hex default 0x100000 diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index b72de96a277..ed0ad686b3f 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -14,7 +14,6 @@ #include <asm/cpu.h> #include <asm/cpu_common.h> #include <asm/cpu_x86.h> -#include <asm/global_data.h> #include <asm/msr.h> #include <asm/msr-index.h> #include <asm/mtrr.h> @@ -23,8 +22,6 @@ #include <asm/turbo.h> #include <asm/arch/model_206ax.h> -DECLARE_GLOBAL_DATA_PTR; - static void enable_vmx(void) { struct cpuid_result regs; diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 7a94dc877e3..cde4fbf3557 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -34,22 +34,10 @@ DECLARE_GLOBAL_DATA_PTR; void bootm_announce_and_cleanup(void) { - printf("\nStarting kernel ...\n\n"); - #ifdef CONFIG_SYS_COREBOOT timestamp_add_now(TS_START_KERNEL); #endif - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#if IS_ENABLED(CONFIG_BOOTSTAGE_REPORT) - bootstage_report(); -#endif - - /* - * Call remove function of all devices with a removal flag set. - * This may be useful for last-stage operations, like cancelling - * of DMA operation or releasing device internal buffers. - */ - dm_remove_devices_active(); + bootm_final(0); } #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index bd0efde00c1..96943cb8c46 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -5,13 +5,10 @@ */ #include <init.h> -#include <asm/global_data.h> #include <linux/errno.h> #include <asm/mtrr.h> #include <asm/u-boot-x86.h> -DECLARE_GLOBAL_DATA_PTR; - int init_cache_f_r(void) { bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) || diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 2ea9bcf59c2..a5f2231aa52 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -30,7 +30,6 @@ #include <asm/bootm.h> #include <asm/bootparam.h> #include <asm/efi.h> -#include <asm/global_data.h> #ifdef CONFIG_SYS_COREBOOT #include <asm/arch/timestamp.h> #endif @@ -38,8 +37,6 @@ #include <linux/ctype.h> #include <linux/libfdt.h> -DECLARE_GLOBAL_DATA_PTR; - /* * Memory lay-out: * diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 2958f207397..c19ac9d1f9a 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -178,6 +178,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) printf("Transferring Control to Linux @0x%08lx ...\n\n", (ulong)images->ep); + bootm_final(flag); + flush_dcache_range((unsigned long)params_start, (unsigned long)params); if (flag & BOOTM_STATE_OS_FAKE_GO) diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c index a499590c75b..d3d317edf88 100644 --- a/arch/xtensa/lib/relocate.c +++ b/arch/xtensa/lib/relocate.c @@ -4,6 +4,8 @@ */ #include <relocate.h> +#include <linux/string.h> +#include <linux/types.h> #include <asm/sections.h> #include <asm/string.h> diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index 319635c6b09..1fe33a4c62b 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -5,12 +5,9 @@ #include <clock_legacy.h> #include <time.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/stringify.h> -DECLARE_GLOBAL_DATA_PTR; - #if XCHAL_HAVE_CCOUNT static ulong get_ccount(void) { |