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authorTom Rini <[email protected]>2025-11-06 17:21:46 -0600
committerTom Rini <[email protected]>2025-11-06 17:21:46 -0600
commita9cf66de5944b872c927e1c2f404330d9e962ab0 (patch)
tree8fa90b1e729568a083386c61a717418601f2b4a9 /arch
parentddc916334a7a7e180b532dbb2cf1b778466d2b9b (diff)
parent057b1f8df9b5f6dced7f7db353a175744bf26031 (diff)
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
This is mostly R-Car Gen5 drivers for GPIO, pin control, RSwitch3 and matching PHYs. There is also a few trivial clean ups for arch headers and configs. Board code, DT and clock are coming in follow up PR.
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-renesas/include/mach/rcar-gen3-base.h12
-rw-r--r--arch/arm/mach-renesas/include/mach/rcar-gen4-base.h4
-rw-r--r--arch/arm/mach-renesas/psci-rcar64.c5
3 files changed, 8 insertions, 13 deletions
diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
index 7b4f5f0c651..741fb8b7041 100644
--- a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
+++ b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * ./arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
- *
* Copyright (C) 2015 Renesas Electronics Corporation
*/
@@ -73,11 +71,11 @@
#define GICC_BASE 0xF1020000
/* PFC */
-#define PFC_PUEN5 0xE6060414
-#define PUEN_SSI_SDATA4 BIT(17)
-#define PFC_PUEN6 0xE6060418
-#define PUEN_USB1_OVC (1 << 2)
-#define PUEN_USB1_PWEN (1 << 1)
+#define PFC_PUEN5 0xE6060414
+#define PUEN_SSI_SDATA4 BIT(17)
+#define PFC_PUEN6 0xE6060418
+#define PUEN_USB1_OVC BIT(2)
+#define PUEN_USB1_PWEN BIT(1)
#ifndef __ASSEMBLY__
#include <asm/types.h>
diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
index f34473db35a..d882a9ba4a0 100644
--- a/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
+++ b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
- *
* Copyright (C) 2021 Renesas Electronics Corp.
*/
@@ -31,6 +29,8 @@
#define RST_BASE 0xE6160000 /* Domain0 */
#define RST_SRESCR0 (RST_BASE + 0x18)
#define RST_SPRES 0x5AA58000
+#define RST_WDTRSTCR (RST_BASE + 0x10)
+#define RST_RWDT 0xA55A8002
/* Arm Generic Timer */
#define CNTCR_BASE 0xE6080000
diff --git a/arch/arm/mach-renesas/psci-rcar64.c b/arch/arm/mach-renesas/psci-rcar64.c
index a230692c9e0..459dd55ff45 100644
--- a/arch/arm/mach-renesas/psci-rcar64.c
+++ b/arch/arm/mach-renesas/psci-rcar64.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
+#include <asm/arch/renesas.h>
int __secure psci_features(u32 function_id, u32 psci_fid)
{
@@ -29,10 +30,6 @@ u32 __secure psci_version(void)
return ARM_PSCI_VER_0_2;
}
-#define RST_BASE 0xE6160000 /* Domain0 */
-#define RST_SRESCR0 (RST_BASE + 0x18)
-#define RST_SPRES 0x5AA58000
-
void __secure __noreturn psci_system_reset(void)
{
writel(RST_SPRES, RST_SRESCR0);