diff options
| author | Tom Rini <[email protected]> | 2026-01-26 09:09:16 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-01-26 09:09:16 -0600 |
| commit | c08da5d03c2a0b72e81a11ff7ca507e3a6414db3 (patch) | |
| tree | 4f56e067e2aaf15c440a4685cd3ae2987119e477 /arch | |
| parent | 0ffca1dff1e8960b5920dfc3164e0fcd5892b961 (diff) | |
| parent | 8805aa120ca5341ca14d8f7f2311f7a85d57a5f9 (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Some improvements for some boards' DRAM setup, to allow boards with
"odd" DRAM sizes (1.5GB or 3GB), and to support the T113-s4 with double
the co-packaged DRAM. Support for a new board (X96Q TV box), and a fix
for the DT name prefix. Also we support the new AXP318W PMIC, which is
used on new boards with the A733 SoC. There are some preliminary support
patches for this SoC, but they are not quite ready yet - though maybe I
push some uncontroversial ones a bit later still.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/dram_dw_helpers.c | 22 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/dram_helpers.c | 12 |
3 files changed, 34 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 0eccb1e6c28..59e2e980bfa 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -45,5 +45,6 @@ unsigned long sunxi_dram_init(void); void mctl_await_completion(u32 *reg, u32 mask, u32 val); bool mctl_mem_matches(u32 offset); bool mctl_mem_matches_base(u32 offset, ulong base); +bool mctl_check_memory(phys_addr_t addr); #endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c index 24767354935..d2af2d57fde 100644 --- a/arch/arm/mach-sunxi/dram_dw_helpers.c +++ b/arch/arm/mach-sunxi/dram_dw_helpers.c @@ -143,8 +143,28 @@ void mctl_auto_detect_dram_size(const struct dram_para *para, unsigned long mctl_calc_size(const struct dram_config *config) { + unsigned long size; u8 width = config->bus_full_width ? 4 : 2; /* 8 banks */ - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; + size = (1ULL << (config->cols + config->rows + 3)) * width * + config->ranks; + + /* + * There are boards with non-power-of-2 sized DRAM chips, like 1.5GB + * or 3GB. They are detected as the larger power-of-2 (2GB and 4GB), + * so test the last quarter for being able to store values. + */ + if (!mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) { + if (mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64)) { + size = (size / 4) * 3; + debug("capping memory at %ld MB\n", size >> 20); + } else { + printf("DRAM test failure at address 0x%lx\n", + CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64); + return 0; + } + } + + return size; } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 83dbe4ca98f..376b7d14f86 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -62,3 +62,15 @@ bool mctl_mem_matches(u32 offset) return mctl_mem_matches_base(offset, CFG_SYS_SDRAM_BASE); } #endif + +bool mctl_check_memory(phys_addr_t addr) +{ + uint32_t orig, val; + + orig = readl(addr); + writel(~orig, addr); + val = readl(addr); + writel(orig, addr); + + return ~orig == val; +} |
