ddr: altera: agilex5: LPDDRs in-line ECC support

In-line ECC support was added for LPDDR by reserving the last one-eighth
of the memory space for ECC data. Full memory initialization using the
BIST MEM INIT mailbox command, based on address and size, is required to
correctly generate ECC data and enable proper ECC logic verification.

Signed-off-by: Tingting Meng <[email protected]>

1 files changed, 18 insertions, 8 deletions

diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index d7ab58267eb..8d7dc0945ab 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -25,34 +25,44 @@
 	/*
 	 * Both Memory base address and size default info is retrieved from HW setting.
 	 * Reconfiguration / Overwrite these info can be done with examples below.
-	 */
-	/*
+	 *
+	 * When LPDDR ECC is enabled, the last 1/8 of the memory region must
+	 * be reserved for the Inline ECC buffer.
+	 *
 	 * Example for memory size with 2GB:
 	 * memory {
 	 *	reg = <0x0 0x80000000 0x0 0x80000000>;
 	 * };
-	 */
-	/*
+	 *
 	 * Example for memory size with 8GB:
 	 * memory {
 	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
 	 *	      <0x8 0x80000000 0x1 0x80000000>;
 	 * };
-	 */
-	/*
+	 *
 	 * Example for memory size with 32GB:
 	 * memory {
 	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
 	 *	      <0x8 0x80000000 0x7 0x80000000>;
 	 * };
-	 */
-	/*
+	 *
 	 * Example for memory size with 512GB:
 	 * memory {
 	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
 	 *	      <0x8 0x80000000 0x7 0x80000000>,
 	 *	      <0x88 0x00000000 0x78 0x00000000>;
 	 * };
+	 *
+	 * Example for memory size with 2GB with LPDDR Inline ECC ON:
+	 * memory {
+	 *	reg = <0x0 0x80000000 0x0 0x70000000>;
+	 * };
+	 *
+	 * Example for memory size with 8GB with LPDDR Inline ECC ON:
+	 * memory {
+	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
+	 *	      <0x8 0x80000000 0x1 0x40000000>;
+	 * };
 	 */
 
 	chosen {