Merge tag 'u-boot-rockchip-20211015' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

- Fix for Rockchip mmc HS400 mode;
- Fix for px30 board Odroid Go;
- rockchip_sfc update;
- rk3568 clk update;
- doc fix;

4 files changed, 18 insertions, 8 deletions

diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index aaa8ae2235d..ef706486dc6 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -967,7 +967,7 @@
 		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 		clock-names = "clk_sfc", "hclk_sfc";
 		pinctrl-names = "default";
-		pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
+		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
 		power-domains = <&power PX30_PD_MMC_NAND>;
 		status = "disabled";
 	};
@@ -1953,7 +1953,7 @@
 					<1 RK_PA1 3 &pcfg_pull_none>;
 			};
 
-			sfc_cs: sfc-cs {
+			sfc_cs0: sfc-cs0 {
 				rockchip,pins =
 					<1 RK_PA4 3 &pcfg_pull_none>;
 			};
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 741e8dd9352..bffaa3edf33 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -18,8 +18,18 @@
 	};
 };
 
+/* U-Boot clk driver for px30 cannot set GPU_CLK */
 &cru {
 	u-boot,dm-pre-reloc;
+	assigned-clocks = <&cru PLL_NPLL>,
+		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+		<&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
+
+	assigned-clock-rates = <1188000000>,
+		<200000000>, <200000000>,
+		<150000000>, <150000000>,
+		<100000000>, <17000000>;
 };
 
 &dmc {
@@ -70,7 +80,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&spi_flash {
+&{/sfc@ff3a0000/flash@0} {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 6f91f5040b0..4e3dceecbec 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -618,18 +618,18 @@
 };
 
 &sfc {
+	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+	pinctrl-names = "default";
 	#address-cells = <1>;
 	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
 	status = "okay";
 
-	spi_flash: xt25f128b@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <108000000>;
 		spi-rx-bus-width = <2>;
-		spi-tx-bus-width = <2>;
+		spi-tx-bus-width = <1>;
 	};
 };
 
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 6c59033f03a..399f19ad21e 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -14,7 +14,7 @@
 #define APLL_HZ		(816 * MHz)
 #define GPLL_HZ		(1188 * MHz)
 #define CPLL_HZ		(1000 * MHz)
-#define PPLL_HZ		(100 * MHz)
+#define PPLL_HZ		(200 * MHz)
 
 /* RK3568 pll id */
 enum rk3568_pll_id {