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authorTom Rini <[email protected]>2021-11-01 08:14:45 -0400
committerTom Rini <[email protected]>2021-11-01 08:14:45 -0400
commitdaaa10fddb5d9076601473bc53409ab74f04c048 (patch)
treeb5ca780d0e9ce29fe58362533b56765a9ed3abad /arch
parent360e392274e3bfeda3b7226d2cac7514774d0da1 (diff)
parent5270bee9b27cf63251696916e4b5a5d4412d3a2d (diff)
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixes for x86 build with Clang/LLVM compiler - Tangier ACPI changes - Edison SD card detect pin fix - EFI on x86 doc update with latest instructions - PXE utility fixes to align with latest x86 zboot implementation
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/cpu/tangier/pinmux.c48
-rw-r--r--arch/x86/dts/chromebook_coral.dts1
-rw-r--r--arch/x86/dts/edison.dts17
-rw-r--r--arch/x86/include/asm/arch-tangier/acpi/southcluster.asl81
-rw-r--r--arch/x86/include/asm/i8254.h4
5 files changed, 73 insertions, 78 deletions
diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c
index acf97e3af51..7b2c35fbf79 100644
--- a/arch/x86/cpu/tangier/pinmux.c
+++ b/arch/x86/cpu/tangier/pinmux.c
@@ -37,8 +37,9 @@ struct mrfld_family {
.npins = (e) - (s) + 1, \
}
-/* Now we only support I2C family of pins */
+/* Now we only support SD/SDIO and I2C families of pins */
static struct mrfld_family mrfld_families[] = {
+ MRFLD_FAMILY(3, 37, 56),
MRFLD_FAMILY(7, 101, 114),
};
@@ -116,13 +117,35 @@ static int mrfld_pinconfig_protected(unsigned int pin, u32 mask, u32 bits)
debug("scu: v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n",
v, (u32)bufcfg, bits, mask, bufcfg);
- ret = scu_ipc_raw_command(IPCMSG_INDIRECT_WRITE, 0, &v, 4,
- NULL, 0, (u32)bufcfg, 0);
+ return scu_ipc_raw_command(IPCMSG_INDIRECT_WRITE, 0, &v, 4, NULL, 0, (u32)bufcfg, 0);
+}
+
+static int mrfld_pinconfig(unsigned int pin, u32 mask, u32 bits)
+{
+ struct mrfld_pinctrl *pinctrl;
+ struct udevice *dev;
+ void __iomem *bufcfg;
+ u32 v, value;
+ int ret;
+
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
if (ret)
- pr_err("Failed to set mode via SCU for pin %u (%d)\n",
- pin, ret);
+ return ret;
- return ret;
+ pinctrl = dev_get_priv(dev);
+
+ bufcfg = mrfld_get_bufcfg(pinctrl, pin);
+ if (!bufcfg)
+ return -EINVAL;
+
+ value = readl(bufcfg);
+ v = (value & ~mask) | (bits & mask);
+ writel(v, bufcfg);
+
+ debug("v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n",
+ v, (u32)bufcfg, bits, mask, bufcfg);
+
+ return 0;
}
static int mrfld_pinctrl_cfg_pin(ofnode pin_node)
@@ -133,11 +156,6 @@ static int mrfld_pinctrl_cfg_pin(ofnode pin_node)
u32 mask;
int ret;
- /* For now we only support just protected Family of pins */
- is_protected = ofnode_read_bool(pin_node, "protected");
- if (!is_protected)
- return -ENOTSUPP;
-
pad_offset = ofnode_read_s32_default(pin_node, "pad-offset", -1);
if (pad_offset == -1)
return -EINVAL;
@@ -152,7 +170,13 @@ static int mrfld_pinctrl_cfg_pin(ofnode pin_node)
if (mode & ~mask)
return -ENOTSUPP;
- ret = mrfld_pinconfig_protected(pad_offset, mask, mode);
+ is_protected = ofnode_read_bool(pin_node, "protected");
+ if (is_protected)
+ ret = mrfld_pinconfig_protected(pad_offset, mask, mode);
+ else
+ ret = mrfld_pinconfig(pad_offset, mask, mode);
+ if (ret)
+ pr_err("Failed to set mode for pin %u (%d)\n", pad_offset, ret);
return ret;
}
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index f0caaacfee2..69a1c1ce295 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -825,6 +825,7 @@
* Refer to EDS-Vol2-22.3
* [14:8] steps of delay for HS400, each 125ps
* [6:0] steps of delay for SDR104/HS200, each 125ps
+ */
/*
* EMMC TX DATA Delay 2
diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index 2c8cf6c0710..b3658b8c304 100644
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -94,6 +94,12 @@
sdcard: mmc@ff3fa000 {
compatible = "intel,sdhci-tangier";
reg = <0xff3fa000 0x1000>;
+ /*
+ * In the disconnected state of the SD Card Detection pin
+ * the read value is always the same and inverted to what
+ * we are expecting in the code.
+ */
+ cd-inverted;
};
pmu: power@ff00b000 {
@@ -132,6 +138,17 @@
reg = <0xff0c0000 0x8000>;
/*
+ * Disconnect SD card detection pin, so it won't affect
+ * the reality on two different PCB designs where it's
+ * using the opposite signaling: Edison/Arduino uses
+ * Active Low, while SparkFun went with Active High.
+ */
+ sd_cd@0 {
+ pad-offset = <37>;
+ mode-func = <3>;
+ };
+
+ /*
* Initial configuration came from the firmware.
* Which quite likely has been used in the phones, where I2C #8,
* that is not part of Atom peripheral, is in use.
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index a8852f8202c..4a7c8542618 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -123,10 +123,7 @@ Device (PCI0)
}
})
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
Device (SDHC)
@@ -138,10 +135,7 @@ Device (PCI0)
})
Name (PSTS, Zero)
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Method (_PS3, 0, NotSerialized)
{
@@ -168,10 +162,7 @@ Device (PCI0)
GPIO
})
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Method (_RMV, 0, NotSerialized)
{
@@ -203,10 +194,8 @@ Device (PCI0)
Device (BRC2)
{
Name (_ADR, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+
+ Name (_STA, STA_VISIBLE)
Method (_RMV, 0, NotSerialized)
{
@@ -257,20 +246,14 @@ Device (PCI0)
}
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
Device (I2C1)
{
Name (_ADR, 0x00080000)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (SSCN, Package ()
{
@@ -303,10 +286,7 @@ Device (PCI0)
{
Name (_ADR, 0x00090001)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (SSCN, Package ()
{
@@ -328,10 +308,7 @@ Device (PCI0)
{
Name (_ADR, 0x000c0000)
- Method (_STA)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (AVBL, Zero)
Method (_REG, 2, NotSerialized)
@@ -361,10 +338,7 @@ Device (PCI0)
^IPC1.PMIC
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Device (RHUB)
{
@@ -404,20 +378,14 @@ Device (PCI0)
{
Name (_ADR, 0x00170000)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
Device (HSU0)
{
Name (_ADR, 0x00040001)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Device (BTH0)
{
@@ -428,10 +396,7 @@ Device (PCI0)
HSU0
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (RBUF, ResourceTemplate()
{
@@ -466,10 +431,7 @@ Device (PCI0)
{
Name (_ADR, 0x00130000)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Device (PMIC)
{
@@ -481,10 +443,7 @@ Device (PCI0)
IPC1
})
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (RBUF, ResourceTemplate()
{
@@ -554,10 +513,7 @@ Device (PCI0)
Name (_ADR, 0x00150000)
Name (_UID, Zero)
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
Name (RBUF, ResourceTemplate ()
{
@@ -594,8 +550,5 @@ Device (FLIS)
Return (RBUF)
}
- Method (_STA, 0, NotSerialized)
- {
- Return (STA_VISIBLE)
- }
+ Name (_STA, STA_VISIBLE)
}
diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h
index d769daf85dc..4069b9a2b84 100644
--- a/arch/x86/include/asm/i8254.h
+++ b/arch/x86/include/asm/i8254.h
@@ -7,7 +7,7 @@
/* i8254.h Intel 8254 PIT registers */
#ifndef _ASMI386_I8254_H_
-#define _ASMI386_I8954_H_
+#define _ASMI386_I8254_H_
#define PIT_T0 0x00 /* PIT channel 0 count/status */
#define PIT_T1 0x01 /* PIT channel 1 count/status */
@@ -53,4 +53,4 @@ int i8254_enable_beep(uint frequency_hz);
*/
void i8254_disable_beep(void);
-#endif /* _ASMI386_I8954_H_ */
+#endif /* _ASMI386_I8254_H_ */