Merge tag 'u-boot-socfpga-next-20250731' of https://source.denx.de/u-boot/custodians/u-boot-socfpga

This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.

CI:

  * https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221

Summary of changes:

Agilex5 Power Manager:

  *   Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.

NAND Boot Support for Agilex5:

  *   SPL support for NAND boot is enabled.
  *   UBI/UBIFS support is configured in defconfigs.
  *   Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.

Code Quality Improvements:

  *   Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
  *   Several cleanup patches addressing formatting, logic, and initialization issues.

General Maintenance:

  *   SPDX license tags and header include fixes.
  *   Device tree updates to limit SPI clock frequency and other minor adjustments.

These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.

This patch set has been tested on Agilex 5 devkit.

10 files changed, 56 insertions, 9 deletions

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 874e71b5ca4..402f0bec173 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -668,6 +668,12 @@
 				bootph-all;
 			};
 		};
+
+		pwrmgr: pwrmgr@10d14000 {
+			compatible = "altr,pmgr-agilex5";
+			reg = <0x10d14000 0x100>;
+			bootph-all;
+		};
 	};
 };
 
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
index 86322d7b0ce..9bc3864022b 100644
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -388,6 +388,7 @@
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+			spi-max-frequency = <50000000>;
 			status = "disabled";
 		};
 
@@ -402,6 +403,7 @@
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+			spi-max-frequency = <50000000>;
 			status = "disabled";
 		};
 
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 8d7dc0945ab..938ddb04c04 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -67,7 +67,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-		u-boot,spl-boot-order = &mmc,&flash0,"/memory";
+		u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory";
 	};
 };
 
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a76a9fb2a39..156cfbbcf3b 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -120,7 +120,6 @@ config TARGET_SOCFPGA_N5X
 	select BINMAN if SPL_ATF
 	select CLK
 	select GICV2
-	select FPGA_INTEL_SDM_MAILBOX
 	select NCORE_CACHE
 	select SPL_ALTERA_SDRAM
 	select SPL_CLK if SPL
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index bda12324803..28554b7a109 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -134,7 +134,7 @@ u8 socfpga_get_board_id(void)
 
 	if (jtag_usercode == DEFAULT_JTAG_USERCODE) {
 		debug("JTAG Usercode is not set. Default Board ID to 0\n");
-	} else if (jtag_usercode >= 0 && jtag_usercode <= 255) {
+	} else if (jtag_usercode <= 255) {
 		board_id = jtag_usercode;
 		debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id);
 	} else {
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 763b077d8c1..04203cceb8a 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -68,6 +68,7 @@
 #define SOC64_HANDOFF_CLOCK		(SOC64_HANDOFF_BASE + 0x580)
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_PERI		(SOC64_HANDOFF_BASE + 0x620)
+#define SOC64_HANDOFF_PERI_LEN		1
 #define SOC64_HANDOFF_SDRAM		(SOC64_HANDOFF_BASE + 0x634)
 #define SOC64_HANDOFF_SDRAM_LEN		5
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h b/arch/arm/mach-socfpga/include/mach/secure_vab.h
index 42588588e87..1be0cb61e7a 100644
--- a/arch/arm/mach-socfpga/include/mach/secure_vab.h
+++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h
@@ -1,7 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  *
  * Copyright (C) 2020 Intel Corporation <www.intel.com>
- *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #ifndef	_SECURE_VAB_H_
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 4f080f4f0b3..5222b384434 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -22,6 +22,22 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Agilex5 Sub Device Jtag ID List */
+#define A3690_JTAG_ID	0x036090DD
+#define A3694_JTAG_ID	0x436090DD
+#define A36C0_JTAG_ID	0x0360C0DD
+#define A36C4_JTAG_ID	0x4360C0DD
+#define A36D0_JTAG_ID	0x0360D0DD
+#define A36D4_JTAG_ID	0x4360D0DD
+#define A36F0_JTAG_ID	0x0360F0DD
+#define A36F4_JTAG_ID	0x4360F0DD
+#define A3610_JTAG_ID	0x036010DD
+#define A3614_JTAG_ID	0x436010DD
+#define A3630_JTAG_ID	0x036030DD
+#define A3634_JTAG_ID	0x436030DD
+
+#define JTAG_ID_MASK	0xCFF0FFFF
+
 /*
  * FPGA programming support for SoC FPGA Stratix 10
  */
@@ -42,6 +58,22 @@ static Altera_desc altera_fpga[] = {
 	},
 };
 
+u32 socfpga_get_jtag_id(void)
+{
+	u32 jtag_id;
+
+	jtag_id = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD4);
+
+	if (!jtag_id) {
+		debug("Failed to read JTAG ID. Default JTAG ID to A36F4_JTAG_ID.\n");
+		jtag_id = A36F4_JTAG_ID;
+	}
+
+	debug("%s: jtag_id: 0x%x\n", __func__, jtag_id);
+
+	return jtag_id;
+}
+
 /*
  * The Agilex5 platform has enabled the bloblist feature, and the bloblist
  * address and size are initialized based on the defconfig settings.
diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c
index e931f1043b3..d5ff47a142c 100644
--- a/arch/arm/mach-socfpga/secure_vab.c
+++ b/arch/arm/mach-socfpga/secure_vab.c
@@ -1,17 +1,18 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
  * Copyright (C) 2020 Intel Corporation <www.intel.com>
- *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
+#include <log.h>
+#include <malloc.h>
 #include <asm/arch/mailbox_s10.h>
 #include <asm/arch/secure_vab.h>
 #include <asm/arch/smc_api.h>
 #include <asm/unaligned.h>
-#include <exports.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/intel-smc.h>
-#include <log.h>
 
 #define CHUNKSZ_PER_WD_RESET		(256 * SZ_1K)
 
diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
index a9aad5350d2..2a13301802d 100644
--- a/arch/arm/mach-socfpga/spl_agilex5.c
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -96,6 +96,12 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &dev);
+	if (ret) {
+		debug("PSS SRAM power-off failed: %d\n", ret);
+		hang();
+	}
+
 	if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
 		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 		if (ret) {