Merge tag 'xilinx-for-v2018.09' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.09

clk:
- Fix zynqmp clock driver

common:
- Handle CMD_RET_USAGE in cmd_process_error
- Use return macros in cmd_process_error
- Fix duplication of CONFIG_SYS_PROMPT_HUSH_PS2
- Support watchdog in usb_kbd.c
- Fix name usage in usb_kbd.c
- Support systems with non zero memory start initialized from DT only

gpio:
- Add support for manual relocation in uclass
- zynq - use live tree
- zynq - fix match data reading
- zynq - setup bank name
- xilinx - convert driver to DM

microblaze:
- Use generic iounmap/ioremap implementations
- Redesign reset logic with sysreset features
- Use watchdog and gpio over DM
- Remove unused macros and fix some checkpatch issues
- Fix timer initialization not to be called twice

serial:
- zynq - Use platdata intead of priv data

sysreset:
- Add support for manual relocation in uclass
- Add gpio-restart driver
- Add microblaze soft reset driver

watchdog:
- Add support for aliases in uclass
- Add support for manual relocation in uclass
- Convert xilinx driver to DM
- cadence - update info in the driver and not stop wdt in probe

xilinx:
- Enable LED gpio for some targets with gpio-leds DT node
- Setup variables via Kconfig

zynq:
- Add support for watchdog aliases
- Add support for mini nand/nor configurations
- Wire FPGA initalization in SPL

zynqmp:
- Enable mass storage for zcu100
- Handle external pmufw files
- Add support for secure images
- Some Kconfig movements and alignments
- Add support for watchdog aliases
- Use subcommands style for platform command
- Add mmio_read/write platform commands
- DT updates
- Add support for mini qspi configuration

15 files changed, 327 insertions, 59 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5b3746c80bf..64d58a62418 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1474,6 +1474,8 @@ source "board/toradex/colibri_pxa270/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynq/Kconfig"
 source "board/xilinx/zynqmp/Kconfig"
 source "board/zipitz2/Kconfig"
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9607239b031..094c41b3de6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
 
 dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-cc108.dtb \
+	zynq-cse-nand.dtb \
+	zynq-cse-nor.dtb \
 	zynq-cse-qspi-single.dtb \
 	zynq-microzed.dtb \
 	zynq-minized.dtb \
@@ -150,6 +152,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-mini-emmc0.dtb			\
 	zynqmp-mini-emmc1.dtb			\
 	zynqmp-mini-nand.dtb			\
+	zynqmp-mini-qspi.dtb			\
 	zynqmp-zcu100-revC.dtb			\
 	zynqmp-zcu102-revA.dtb			\
 	zynqmp-zcu102-revB.dtb			\
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 00000000000..9b1dd19a85d
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Zynq CSE NAND Board";
+	compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &dcc;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x400000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+			slcr: slcr@f8000000 {
+			u-boot,dm-pre-reloc;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			reg = <0xF8000000 0x1000>;
+			ranges;
+			clkc: clkc@100 {
+				u-boot,dm-pre-reloc;
+				#clock-cells = <1>;
+				compatible = "xlnx,ps7-clkc";
+				clock-output-names = "armpll", "ddrpll",
+						"iopll", "cpu_6or4x",
+						"cpu_3or2x", "cpu_2x", "cpu_1x",
+						"ddr2x", "ddr3x", "dci",
+						"lqspi", "smc", "pcap", "gem0",
+						"gem1", "fclk0", "fclk1",
+						"fclk2", "fclk3", "can0",
+						"can1", "sdio0", "sdio1",
+						"uart0", "uart1", "spi0",
+						"spi1", "dma", "usb0_aper",
+						"usb1_aper", "gem0_aper",
+						"gem1_aper", "sdio0_aper",
+						"sdio1_aper", "spi0_aper",
+						"spi1_aper", "can0_aper",
+						"can1_aper", "i2c0_aper",
+						"i2c1_aper", "uart0_aper",
+						"uart1_aper", "gpio_aper",
+						"lqspi_aper", "smc_aper",
+						"swdt", "dbg_trc", "dbg_apb";
+				reg = <0x100 0x100>;
+			};
+		};
+	};
+
+};
+
+&dcc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 00000000000..ba6f9a1a79e
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Zynq CSE NOR Board";
+	compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &dcc;
+	};
+
+	memory@fffc0000 {
+		device_type = "memory";
+		reg = <0xFFFC0000 0x40000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&intc>;
+		ranges;
+
+		intc: interrupt-controller@f8f01000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0xF8F01000 0x1000>,
+			      <0xF8F00100 0x100>;
+		};
+
+		slcr: slcr@f8000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			reg = <0xF8000000 0x1000>;
+			ranges;
+			clkc: clkc@100 {
+				#clock-cells = <1>;
+				compatible = "xlnx,ps7-clkc";
+				fclk-enable = <0xf>;
+				clock-output-names = "armpll", "ddrpll",
+						"iopll", "cpu_6or4x",
+						"cpu_3or2x", "cpu_2x", "cpu_1x",
+						"ddr2x", "ddr3x", "dci",
+						"lqspi", "smc", "pcap", "gem0",
+						"gem1", "fclk0", "fclk1",
+						"fclk2", "fclk3", "can0",
+						"can1", "sdio0", "sdio1",
+						"uart0", "uart1", "spi0",
+						"spi1", "dma", "usb0_aper",
+						"usb1_aper", "gem0_aper",
+						"gem1_aper", "sdio0_aper",
+						"sdio1_aper", "spi0_aper",
+						"spi1_aper", "can0_aper",
+						"can1_aper", "i2c0_aper",
+						"i2c1_aper", "uart0_aper",
+						"uart1_aper", "gpio_aper",
+						"lqspi_aper", "smc_aper",
+						"swdt", "dbg_trc", "dbg_apb";
+				reg = <0x100 0x100>;
+			};
+		};
+	};
+
+};
+
+&dcc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
new file mode 100644
index 00000000000..c235a5f731d
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <[email protected]>
+ * Michal Simek <[email protected]>
+ */
+
+/dts-v1/;
+
+/ {
+	model = "ZynqMP MINI QSPI";
+	compatible = "xlnx,zynqmp";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &dcc;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@fffc0000 {
+		device_type = "memory";
+		reg = <0x0 0xfffc0000 0x40000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		qspi: spi@ff0f0000 {
+			compatible = "xlnx,zynqmp-qspi-1.0";
+			status = "disabled";
+			clock-names = "ref_clk", "pclk";
+			clocks = <&misc_clk &misc_clk>;
+			num-cs = <1>;
+			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		misc_clk: misc_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+		};
+	};
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "n25q512a11";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&dcc {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 6e575a063be..2fffe177b58 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -280,11 +280,13 @@
 &spi0 { /* Low Speed connector */
 	status = "okay";
 	label = "LS-SPI0";
+	num-cs = <1>;
 };
 
 &spi1 { /* High Speed connector */
 	status = "okay";
 	label = "HS-SPI1";
+	num-cs = <1>;
 };
 
 &uart0 {
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index d3ea9e67e07..f47273fde9c 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -54,7 +54,7 @@ int dram_init_banksize(void)
 
 int dram_init(void)
 {
-	if (fdtdec_setup_memory_size() != 0)
+	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;
 
 	return 0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 77628e11818..a4f6d5c1ac9 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -40,7 +40,7 @@ struct bsel bsel_str[] = {
 
 int dram_init(void)
 {
-	if (fdtdec_setup_memory_size() != 0)
+	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;
 
 	return 0;
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
index f69cf004ec8..3ff3c1073e2 100644
--- a/arch/arm/mach-zynq/include/mach/hardware.h
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -20,6 +20,7 @@
 #define ZYNQ_EFUSE_BASEADDR		0xF800D000
 #define ZYNQ_USB_BASEADDR0		0xE0002000
 #define ZYNQ_USB_BASEADDR1		0xE0003000
+#define ZYNQ_OCM_BASEADDR		0xFFFC0000
 
 /* Bootmode setting values */
 #define ZYNQ_BM_MASK		0x7
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 83297d6c694..9b7c0be951b 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -29,6 +29,9 @@ void board_init_f(ulong dummy)
 void spl_board_init(void)
 {
 	preloader_console_init();
+#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
+	arch_early_init_r();
+#endif
 	board_init();
 }
 #endif
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index f791c0081ea..c5645934513 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -15,7 +15,7 @@ config TARGET_MICROBLAZE_GENERIC
 	select OF_CONTROL
 	select DM
 	select DM_SERIAL
-	select ENV_IS_IN_FLASH
+	select SYSRESET
 
 endchoice
 
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index d3c523d3874..070c12cce9e 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -47,3 +47,11 @@ int spl_start_uboot(void)
 
 	return 1;
 }
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	__asm__ __volatile__ ("mts rmsr, r0;" \
+			      "bra r0");
+
+	return 0;
+}
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index ef229023bf0..58e5c307508 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -51,6 +51,10 @@ int timer_init (void)
 
 	debug("TIMER: Initialization\n");
 
+	/* Do not init before relocation */
+	if (!(gd->flags & GD_FLG_RELOC))
+		return 0;
+
 	node = fdt_node_offset_by_compatible(blob, node,
 				"xlnx,xps-timer-1.00.a");
 	if (node != -1) {
diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h
index 4762de02438..306ab4c9f2a 100644
--- a/arch/microblaze/include/asm/gpio.h
+++ b/arch/microblaze/include/asm/gpio.h
@@ -1,14 +1 @@
-#ifndef _ASM_MICROBLAZE_GPIO_H_
-#define _ASM_MICROBLAZE_GPIO_H_
-
 #include <asm-generic/gpio.h>
-
-/* Allocation functions */
-extern int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0,
-			   u32 gpio_no1);
-extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no);
-
-#define gpio_status()	gpio_info()
-extern void gpio_info(void);
-
-#endif
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index c7516a47e8c..8e6be0ae267 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * include/asm-microblaze/io.h -- Misc I/O operations
  *
@@ -21,39 +22,42 @@
 #define IO_SPACE_LIMIT 0xFFFFFFFF
 
 #define readb(addr) \
-  ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+	({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
+
 #define readw(addr) \
-  ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+	({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
+
 #define readl(addr) \
-	({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+	({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
 
 #define writeb(b, addr) \
-  (void)((*(volatile unsigned char *) (addr)) = (b))
+	(void)((*(volatile unsigned char *)(addr)) = (b))
+
 #define writew(b, addr) \
-  (void)((*(volatile unsigned short *) (addr)) = (b))
+	(void)((*(volatile unsigned short *)(addr)) = (b))
+
 #define writel(b, addr) \
-  (void)((*(volatile unsigned int *) (addr)) = (b))
+	(void)((*(volatile unsigned int *)(addr)) = (b))
 
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+#define memset_io(a, b, c)        memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)    memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)      memcpy((void *)(a), (b), (c))
 
-#define inb(addr)	readb (addr)
-#define inw(addr)	readw (addr)
-#define inl(addr)	readl (addr)
-#define outb(x, addr)	((void) writeb (x, addr))
-#define outw(x, addr)	((void) writew (x, addr))
-#define outl(x, addr)	((void) writel (x, addr))
+#define inb(addr)	readb(addr)
+#define inw(addr)	readw(addr)
+#define inl(addr)	readl(addr)
+#define outb(x, addr)	((void)writeb(x, addr))
+#define outw(x, addr)	((void)writew(x, addr))
+#define outl(x, addr)	((void)writel(x, addr))
 
 /* Some #definitions to keep strange Xilinx code happy */
-#define in_8(addr)	readb (addr)
-#define in_be16(addr)	readw (addr)
-#define in_be32(addr)	readl (addr)
-
-#define out_8(addr,x )	outb (x,addr)
-#define out_be16(addr,x )	outw (x,addr)
-#define out_be32(addr,x )	outl (x,addr)
+#define in_8(addr)	readb(addr)
+#define in_be16(addr)	readw(addr)
+#define in_be32(addr)	readl(addr)
 
+#define out_8(addr, x)		outb(x, addr)
+#define out_be16(addr, x)	outw(x, addr)
+#define out_be32(addr, x)	outl(x, addr)
 
 #define inb_p(port)		inb((port))
 #define outb_p(val, port)	outb((val), (port))
@@ -71,58 +75,65 @@
 #define __raw_writew writew
 #define __raw_writel writel
 
-static inline void io_insb (unsigned long port, void *dst, unsigned long count)
+static inline void io_insb(unsigned long port, void *dst, unsigned long count)
 {
 	unsigned char *p = dst;
+
 	while (count--)
-		*p++ = inb (port);
+		*p++ = inb(port);
 }
-static inline void io_insw (unsigned long port, void *dst, unsigned long count)
+
+static inline void io_insw(unsigned long port, void *dst, unsigned long count)
 {
 	unsigned short *p = dst;
+
 	while (count--)
-		*p++ = inw (port);
+		*p++ = inw(port);
 }
-static inline void io_insl (unsigned long port, void *dst, unsigned long count)
+
+static inline void io_insl(unsigned long port, void *dst, unsigned long count)
 {
 	unsigned long *p = dst;
+
 	while (count--)
-		*p++ = inl (port);
+		*p++ = inl(port);
 }
 
 static inline void
-io_outsb (unsigned long port, const void *src, unsigned long count)
+io_outsb(unsigned long port, const void *src, unsigned long count)
 {
 	const unsigned char *p = src;
+
 	while (count--)
-		outb (*p++, port);
+		outb(*p++, port);
 }
+
 static inline void
-io_outsw (unsigned long port, const void *src, unsigned long count)
+io_outsw(unsigned long port, const void *src, unsigned long count)
 {
 	const unsigned short *p = src;
+
 	while (count--)
-		outw (*p++, port);
+		outw(*p++, port);
 }
+
 static inline void
-io_outsl (unsigned long port, const void *src, unsigned long count)
+io_outsl(unsigned long port, const void *src, unsigned long count)
 {
 	const unsigned long *p = src;
+
 	while (count--)
-		outl (*p++, port);
+		outl(*p++, port);
 }
 
-#define outsb(a,b,l) io_outsb(a,b,l)
-#define outsw(a,b,l) io_outsw(a,b,l)
-#define outsl(a,b,l) io_outsl(a,b,l)
-
-#define insb(a,b,l) io_insb(a,b,l)
-#define insw(a,b,l) io_insw(a,b,l)
-#define insl(a,b,l) io_insl(a,b,l)
+#define outsb(a, b, l) io_outsb(a, b, l)
+#define outsw(a, b, l) io_outsw(a, b, l)
+#define outsl(a, b, l) io_outsl(a, b, l)
 
+#define insb(a, b, l) io_insb(a, b, l)
+#define insw(a, b, l) io_insw(a, b, l)
+#define insl(a, b, l) io_insl(a, b, l)
 
-#define iounmap(addr)				((void)0)
-#define ioremap(physaddr, size)			(physaddr)
 #define ioremap_nocache(physaddr, size)		(physaddr)
 #define ioremap_writethrough(physaddr, size)	(physaddr)
 #define ioremap_fullcache(physaddr, size)	(physaddr)