Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Misc Kconfig cleanups (Chris & Pali)
- turris_omnia: Fix hangup in debug UART (this introduces
  TPL/SPL_DEBUG_UART_BASE) Pali
- mvebu: uDPU: include fixed-phy support (Robert)
- pinctrl: probe pinctrl drivers during post-bind (Robert)

6 files changed, 40 insertions, 35 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0afec5155b1..9898c7d68e1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -401,6 +401,12 @@ config SYS_ARM_CACHE_WRITEALLOC
 	  write is performed.
 endchoice
 
+config ARCH_VERY_EARLY_INIT
+	bool
+
+config SPL_ARCH_VERY_EARLY_INIT
+	bool
+
 config ARCH_CPU_INIT
 	bool "Enable ARCH_CPU_INIT"
 	help
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index ba312901f33..612a2d5b698 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -90,6 +90,11 @@ clbss_l:cmp	r0, r1			/* while not at end of BSS */
 
 ENTRY(_main)
 
+/* Call arch_very_early_init before initializing C runtime environment. */
+#if CONFIG_IS_ENABLED(ARCH_VERY_EARLY_INIT)
+	bl	arch_very_early_init
+#endif
+
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index a3f273f4f94..a81b8e2b0df 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -16,10 +16,7 @@ config ARMADA_32BIT
 	select SUPPORT_SPL
 	select TRANSLATION_OFFSET
 	select SPL_SYS_NO_VECTOR_TABLE if SPL
-
-config ARMADA_64BIT
-	bool
-	select ARM64
+	select ARCH_VERY_EARLY_INIT
 
 # ARMv7 SoCs...
 config ARMADA_375
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 1b451889d24..8bd2246325c 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -21,6 +21,7 @@ else # CONFIG_ARCH_KIRKWOOD
 
 obj-y	= cpu.o
 obj-y	+= dram.o
+obj-y	+= lowlevel.o
 obj-$(CONFIG_DM_RESET) += system-controller.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 1e893777b29..173d95a760a 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -413,20 +413,7 @@ static void update_sdram_window_sizes(void)
 	}
 }
 
-void mmu_disable(void)
-{
-	asm volatile(
-		"mrc p15, 0, r0, c1, c0, 0\n"
-		"bic r0, #1\n"
-		"mcr p15, 0, r0, c1, c0, 0\n");
-}
-
 #ifdef CONFIG_ARCH_CPU_INIT
-static void set_cbar(u32 addr)
-{
-	asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
-}
-
 #define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
 #define MV_USB_PHY_PLL_REG(reg)		(MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
 #define MV_USB_X3_BASE(addr)		(MVEBU_AXP_USB_BASE | BIT(11) | \
@@ -476,24 +463,6 @@ int arch_cpu_init(void)
 	struct pl310_regs *const pl310 =
 		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-	/*
-	 * Only with disabled MMU its possible to switch the base
-	 * register address on Armada 38x. Without this the SDRAM
-	 * located at >= 0x4000.0000 is also not accessible, as its
-	 * still locked to cache.
-	 */
-	mmu_disable();
-
-	/* Linux expects the internal registers to be at 0xf1000000 */
-	writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
-	set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-
-	/*
-	 * From this stage on, the SoC detection is working. As we have
-	 * configured the internal register base to the value used
-	 * in the macros / defines in the U-Boot header (soc.h).
-	 */
-
 	if (mvebu_soc_family() == MVEBU_SOC_A38X) {
 		/*
 		 * To fully release / unlock this area from cache, we need
diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S
new file mode 100644
index 00000000000..2491310eb0c
--- /dev/null
+++ b/arch/arm/mach-mvebu/lowlevel.S
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(arch_very_early_init)
+#ifdef CONFIG_ARMADA_38X
+	/*
+	 * Only with disabled MMU its possible to switch the base
+	 * register address on Armada 38x. Without this the SDRAM
+	 * located at >= 0x4000.0000 is also not accessible, as its
+	 * still locked to cache.
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, #1
+	mcr	p15, 0, r0, c1, c0, 0
+#endif
+
+	/* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */
+	ldr	r0, =SOC_REGS_PHY_BASE
+	ldr	r1, =INTREG_BASE_ADDR_REG
+	str	r0, [r1]
+	add	r0, r0, #0xC000
+	mcr	p15, 4, r0, c15, c0
+
+	bx lr
+ENDPROC(arch_very_early_init)