Merge tag 'v2025.10-rc3' into next

Prepare v2025.10-rc3

31 files changed, 388 insertions, 1747 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eece3bdcdce..ff8f1ed1ac0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -648,11 +648,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
 	sun8i-r40-oka40i-c.dtb \
 	sun8i-t3-cqa3t-bv3.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
-dtb-$(CONFIG_MACH_SUN8I_V3S) += \
-	sun8i-s3-elimo-initium.dtb \
-	sun8i-s3-pinecube.dtb \
-	sun8i-v3-sl631-imx179.dtb \
-	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN8I_R528) += \
 	sun8i-t113s-mangopi-mq-r-t113.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
diff --git a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi
index c9f302799f1..dff0355150d 100644
--- a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi
@@ -7,6 +7,13 @@
 
 #include "r8a779g0-u-boot.dtsi"
 
+&avb0_pins {
+	pins-vddq18-25-avb {
+		pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0";
+		power-source = <1800>;
+	};
+};
+
 /* Page 31 / FAN */
 &gpio1 {
 	pwm-fan-hog {
@@ -44,7 +51,16 @@
 
 &rpc {
 	flash@0 {
+		/*
+		 * EVTA1 is populated with Spansion S25FS512S
+		 * EVTB1 is populated with Winbond W77Q51NW
+		 */
+		compatible = "jedec,spi-nor";
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <1>;
 	};
 };
+
+&vcc_sdhi {
+	states = <1800000 0>, <3300000 1>;
+};
diff --git a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
deleted file mode 100644
index 052b010a560..00000000000
--- a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Matteo Scordino <[email protected]>
- */
-
-/dts-v1/;
-#include "sun8i-v3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-/ {
-	model = "Elimo Impetus SoM";
-	compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-s3-elimo-initium.dts b/arch/arm/dts/sun8i-s3-elimo-initium.dts
deleted file mode 100644
index 039677c2cc6..00000000000
--- a/arch/arm/dts/sun8i-s3-elimo-initium.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Matteo Scordino <[email protected]>
- */
-
-/dts-v1/;
-#include "sun8i-s3-elimo-impetus.dtsi"
-
-/ {
-	model = "Elimo Initium";
-	compatible = "elimo,initium", "elimo,impetus", "sochip,s3",
-		     "allwinner,sun8i-v3";
-
-	aliases {
-		serial1 = &uart1;
-	};
-};
-
-&uart1 {
-	pinctrl-0 = <&uart1_pg_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&emac {
-	phy-handle = <&int_mii_phy>;
-	phy-mode = "mii";
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
deleted file mode 100644
index d18192d51d1..00000000000
--- a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019 Icenowy Zheng <[email protected]>
- */
-
-/dts-v1/;
-#include "sun8i-v3.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Sipeed Lichee Zero Plus";
-	compatible = "sipeed,lichee-zero-plus", "sochip,s3",
-		     "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	reg_vcc3v3: vcc3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "peripheral";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts
deleted file mode 100644
index e0d4404b595..00000000000
--- a/arch/arm/dts/sun8i-s3-pinecube.dts
+++ /dev/null
@@ -1,228 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
-/*
- * Copyright 2019 Icenowy Zheng <[email protected]>
- */
-
-/dts-v1/;
-#include "sun8i-v3.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "PineCube IP Camera";
-	compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart2;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led1 {
-			label = "pine64:ir:led1";
-			gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
-		};
-
-		led2 {
-			label = "pine64:ir:led2";
-			gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */
-		};
-	};
-
-	reg_vcc5v0: vcc5v0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	reg_vcc_wifi: vcc-wifi {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc-wifi";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */
-		vin-supply = <&reg_dcdc3>;
-		startup-delay-us = <200000>;
-	};
-
-	wifi_pwrseq: pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */
-		post-power-on-delay-ms = <200>;
-	};
-};
-
-&csi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&csi1_8bit_pins>;
-	status = "okay";
-
-	port {
-		csi1_ep: endpoint {
-			remote-endpoint = <&ov5640_ep>;
-			bus-width = <8>;
-			hsync-active = <1>; /* Active high */
-			vsync-active = <0>; /* Active low */
-			data-active = <1>;  /* Active high */
-			pclk-sample = <1>;  /* Rising */
-		};
-	};
-};
-
-&emac {
-	phy-handle = <&int_mii_phy>;
-	phy-mode = "mii";
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	axp209: pmic@34 {
-		reg = <0x34>;
-		interrupt-parent = <&nmi_intc>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pe_pins>;
-	status = "okay";
-
-	ov5640: camera@3c {
-		compatible = "ovti,ov5640";
-		reg = <0x3c>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&csi1_mclk_pin>;
-		clocks = <&ccu CLK_CSI1_MCLK>;
-		clock-names = "xclk";
-
-		AVDD-supply = <&reg_ldo3>;
-		DOVDD-supply = <&reg_ldo3>;
-		DVDD-supply = <&reg_ldo4>;
-		reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */
-		powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */
-
-		port {
-			ov5640_ep: endpoint {
-				remote-endpoint = <&csi1_ep>;
-				bus-width = <8>;
-				hsync-active = <1>; /* Active high */
-				vsync-active = <0>; /* Active low */
-				data-active = <1>;  /* Active high */
-				pclk-sample = <1>;  /* Rising */
-			};
-		};
-	};
-};
-
-&lradc {
-	vref-supply = <&reg_ldo2>;
-	status = "okay";
-
-	button-200 {
-		label = "Setup";
-		linux,code = <KEY_SETUP>;
-		channel = <0>;
-		voltage = <190000>;
-	};
-};
-
-&mmc0 {
-	vmmc-supply = <&reg_dcdc3>;
-	bus-width = <4>;
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
-
-&mmc1 {
-	vmmc-supply = <&reg_vcc_wifi>;
-	vqmmc-supply = <&reg_dcdc3>;
-	mmc-pwrseq = <&wifi_pwrseq>;
-	bus-width = <4>;
-	non-removable;
-	status = "okay";
-};
-
-&pio {
-	vcc-pd-supply = <&reg_dcdc3>;
-	vcc-pe-supply = <&reg_ldo3>;
-};
-
-#include "axp209.dtsi"
-
-&ac_power_supply {
-	status = "okay";
-};
-
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-min-microvolt = <1250000>;
-	regulator-max-microvolt = <1250000>;
-	regulator-name = "vdd-sys-cpu-ephy";
-};
-
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-min-microvolt = <3300000>;
-	regulator-max-microvolt = <3300000>;
-	regulator-name = "vcc-3v3";
-};
-
-&reg_ldo1 {
-	regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
-	regulator-name = "avcc";
-};
-
-&reg_ldo3 {
-	regulator-min-microvolt = <2800000>;
-	regulator-max-microvolt = <2800000>;
-	regulator-name = "avdd-dovdd-2v8-csi";
-	regulator-soft-start;
-	regulator-ramp-delay = <1600>;
-};
-
-&reg_ldo4 {
-	regulator-min-microvolt = <1800000>;
-	regulator-max-microvolt = <1800000>;
-	regulator-name = "dvdd-1v8-csi";
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "winbond,w25q128", "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <40000000>;
-	};
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_vbus-supply = <&reg_vcc5v0>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/dts/sun8i-v3-sl631-imx179.dts
deleted file mode 100644
index 117aeece4e5..00000000000
--- a/arch/arm/dts/sun8i-v3-sl631-imx179.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
-/*
- * Copyright 2020 Paul Kocialkowski <[email protected]>
- */
-
-#include "sun8i-v3-sl631.dtsi"
-
-/ {
-	model = "SL631 Action Camera with IMX179";
-	compatible = "allwinner,sl631-imx179", "allwinner,sl631",
-		     "allwinner,sun8i-v3";
-};
diff --git a/arch/arm/dts/sun8i-v3-sl631.dtsi b/arch/arm/dts/sun8i-v3-sl631.dtsi
deleted file mode 100644
index 6f93f8c49f8..00000000000
--- a/arch/arm/dts/sun8i-v3-sl631.dtsi
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
-/*
- * Copyright 2020 Paul Kocialkowski <[email protected]>
- */
-
-/dts-v1/;
-
-#include "sun8i-v3.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "SL631 Action Camera";
-	compatible = "allwinner,sl631", "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&i2c0 {
-	status = "okay";
-
-	axp209: pmic@34 {
-		reg = <0x34>;
-		interrupt-parent = <&nmi_intc>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pb_pins>;
-	status = "okay";
-};
-
-&lradc {
-	vref-supply = <&reg_ldo2>;
-	status = "okay";
-
-	button-174 {
-		label = "Down";
-		linux,code = <KEY_DOWN>;
-		channel = <0>;
-		voltage = <174603>;
-	};
-
-	button-384 {
-		label = "Up";
-		linux,code = <KEY_UP>;
-		channel = <0>;
-		voltage = <384126>;
-	};
-
-	button-593 {
-		label = "OK";
-		linux,code = <KEY_OK>;
-		channel = <0>;
-		voltage = <593650>;
-	};
-};
-
-&mmc0 {
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-	bus-width = <4>;
-	vmmc-supply = <&reg_dcdc3>;
-	status = "okay";
-};
-
-&pio {
-	vcc-pd-supply = <&reg_dcdc3>;
-	vcc-pe-supply = <&reg_dcdc3>;
-};
-
-#include "axp209.dtsi"
-
-&ac_power_supply {
-	status = "okay";
-};
-
-&battery_power_supply {
-	status = "okay";
-};
-
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-min-microvolt = <1250000>;
-	regulator-max-microvolt = <1250000>;
-	regulator-name = "vdd-sys-cpu";
-};
-
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-min-microvolt = <3300000>;
-	regulator-max-microvolt = <3300000>;
-	regulator-name = "vdd-3v3";
-};
-
-&reg_ldo1 {
-	regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
-	regulator-name = "avcc";
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-	};
-};
-
-&uart1 {
-	pinctrl-0 = <&uart1_pg_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "peripheral";
-	status = "okay";
-};
-
-&usbphy {
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi
deleted file mode 100644
index 186c30cbe6e..00000000000
--- a/arch/arm/dts/sun8i-v3.dtsi
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019 Icenowy Zheng <[email protected]>
- * Copyright (C) 2021 Tobias Schramm <[email protected]>
- */
-
-#include "sun8i-v3s.dtsi"
-
-/ {
-	soc {
-		i2s0: i2s@1c22000 {
-			#sound-dai-cells = <0>;
-			compatible = "allwinner,sun8i-v3-i2s",
-				     "allwinner,sun8i-h3-i2s";
-			reg = <0x01c22000 0x400>;
-			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
-			clock-names = "apb", "mod";
-			dmas = <&dma 3>, <&dma 3>;
-			dma-names = "rx", "tx";
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2s0_pins>;
-			resets = <&ccu RST_BUS_I2S0>;
-			status = "disabled";
-		};
-	};
-};
-
-&ccu {
-	compatible = "allwinner,sun8i-v3-ccu";
-};
-
-&codec_analog {
-	compatible = "allwinner,sun8i-v3-codec-analog",
-		     "allwinner,sun8i-h3-codec-analog";
-};
-
-&emac {
-	/delete-property/ phy-handle;
-	/delete-property/ phy-mode;
-};
-
-&mdio_mux {
-	external_mdio: mdio@2 {
-		reg = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&pio {
-	compatible = "allwinner,sun8i-v3-pinctrl";
-
-	i2s0_pins: i2s0-pins {
-		pins = "PG10", "PG11", "PG12", "PG13";
-		function = "i2s";
-	};
-
-	uart1_pg_pins: uart1-pg-pins {
-		pins = "PG6", "PG7";
-		function = "uart1";
-	};
-};
diff --git a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts b/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
deleted file mode 100644
index f34dfdf1566..00000000000
--- a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
+++ /dev/null
@@ -1,276 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include "sun8i-v3s.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-/ {
-	model = "Anbernic RG Nano";
-	compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s";
-
-	aliases {
-		rtc0 = &pcf8563;
-		rtc1 = &rtc;
-		serial0 = &uart0;
-	};
-
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>;
-		default-brightness-level = <11>;
-		power-supply = <&reg_vcc5v0>;
-		pwms = <&pwm 0 40000 1>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	gpio_keys: gpio-keys {
-		compatible = "gpio-keys";
-
-		button-a {
-			gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-A";
-			linux,code = <BTN_EAST>;
-		};
-
-		button-b {
-			gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-B";
-			linux,code = <BTN_SOUTH>;
-		};
-
-		button-down {
-			gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-DOWN";
-			linux,code = <BTN_DPAD_DOWN>;
-		};
-
-		button-left {
-			gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-LEFT";
-			linux,code = <BTN_DPAD_LEFT>;
-		};
-
-		button-right {
-			gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-RIGHT";
-			linux,code = <BTN_DPAD_RIGHT>;
-		};
-
-		button-se {
-			gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-SELECT";
-			linux,code = <BTN_SELECT>;
-		};
-
-		button-st {
-			gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-START";
-			linux,code = <BTN_START>;
-		};
-
-		button-tl {
-			gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-L";
-			linux,code = <BTN_TL>;
-		};
-
-		button-tr {
-			gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-R";
-			linux,code = <BTN_TR>;
-		};
-
-		button-up {
-			gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-UP";
-			linux,code = <BTN_DPAD_UP>;
-		};
-
-		button-x {
-			gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-X";
-			linux,code = <BTN_NORTH>;
-		};
-
-		button-y {
-			gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-Y";
-			linux,code = <BTN_WEST>;
-		};
-	};
-};
-
-&codec {
-	allwinner,audio-routing = "Speaker", "HP",
-				  "MIC1", "Mic",
-				  "Mic", "HBIAS";
-	allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */
-	status = "okay";
-};
-
-&ehci {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	gpio_expander: gpio@20 {
-		compatible = "nxp,pcal6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		interrupt-parent = <&pio>;
-		interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */
-		vcc-supply = <&reg_vcc3v3>;
-	};
-
-	axp209: pmic@34 {
-		reg = <0x34>;
-		interrupt-parent = <&pio>;
-		interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */
-	};
-
-	pcf8563: rtc@51 {
-		compatible = "nxp,pcf8563";
-		reg = <0x51>;
-	};
-};
-
-#include "axp209.dtsi"
-
-&battery_power_supply {
-	status = "okay";
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	disable-wp;
-	vmmc-supply = <&reg_vcc3v3>;
-	vqmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&ohci {
-	status = "okay";
-};
-
-&pio {
-	vcc-pb-supply = <&reg_vcc3v3>;
-	vcc-pc-supply = <&reg_vcc3v3>;
-	vcc-pf-supply = <&reg_vcc3v3>;
-	vcc-pg-supply = <&reg_vcc3v3>;
-
-	spi0_no_miso_pins: spi0-no-miso-pins {
-		pins = "PC1", "PC2", "PC3";
-		function = "spi0";
-	};
-};
-
-&pwm {
-	pinctrl-0 = <&pwm0_pin>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-max-microvolt = <1250000>;
-	regulator-min-microvolt = <1250000>;
-	regulator-name = "vdd-cpu";
-};
-
-/* DCDC3 wired into every 3.3v input that isn't the RTC. */
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-max-microvolt = <3300000>;
-	regulator-min-microvolt = <3300000>;
-	regulator-name = "vcc-io";
-};
-
-/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */
-&reg_ldo1 {
-	regulator-always-on;
-	regulator-name = "vcc-rtc";
-};
-
-/* LDO2 wired into VCC-PLL and audio codec. */
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-max-microvolt = <3000000>;
-	regulator-min-microvolt = <3000000>;
-	regulator-name = "vcc-pll";
-};
-
-/* LDO3, LDO4, and LDO5 unused. */
-&reg_ldo3 {
-	status = "disabled";
-};
-
-&reg_ldo4 {
-	status = "disabled";
-};
-
-/* RTC uses internal oscillator */
-&rtc {
-	/delete-property/ clocks;
-};
-
-&spi0 {
-	pinctrl-0 = <&spi0_no_miso_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	display@0 {
-		compatible = "saef,sftc154b", "panel-mipi-dbi-spi";
-		reg = <0>;
-		backlight = <&backlight>;
-		dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */
-		reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
-		spi-max-frequency = <100000000>;
-
-		height-mm = <39>;
-		width-mm = <39>;
-
-		/* Set hb-porch to compensate for non-visible area */
-		panel-timing {
-			hactive = <240>;
-			vactive = <240>;
-			hback-porch = <80>;
-			vback-porch = <0>;
-			clock-frequency = <0>;
-			hfront-porch = <0>;
-			hsync-len = <0>;
-			vfront-porch = <0>;
-			vsync-len = <0>;
-		};
-	};
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usb_power_supply {
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
deleted file mode 100644
index 752ad05c8f8..00000000000
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <[email protected]>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "sun8i-v3s-licheepi-zero.dts"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Lichee Pi Zero with Dock";
-	compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
-		     "allwinner,sun8i-v3s";
-
-	aliases {
-		ethernet0 = &emac;
-	};
-
-	leds {
-		/* The LEDs use PG0~2 pins, which conflict with MMC1 */
-		status = "disabled";
-	};
-};
-
-&emac {
-	allwinner,leds-active-low;
-	status = "okay";
-};
-
-&lradc {
-	vref-supply = <&reg_vcc3v0>;
-	status = "okay";
-
-	button-200 {
-		label = "Volume Up";
-		linux,code = <KEY_VOLUMEUP>;
-		channel = <0>;
-		voltage = <200000>;
-	};
-
-	button-400 {
-		label = "Volume Down";
-		linux,code = <KEY_VOLUMEDOWN>;
-		channel = <0>;
-		voltage = <400000>;
-	};
-
-	button-600 {
-		label = "Select";
-		linux,code = <KEY_SELECT>;
-		channel = <0>;
-		voltage = <600000>;
-	};
-
-	button-800 {
-		label = "Start";
-		linux,code = <KEY_OK>;
-		channel = <0>;
-		voltage = <800000>;
-	};
-};
-
-&mmc1 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
deleted file mode 100644
index 2e4587d26ce..00000000000
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <[email protected]>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "sun8i-v3s.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-/ {
-	model = "Lichee Pi Zero";
-	compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		blue_led {
-			label = "licheepi:blue:usr";
-			gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
-		};
-
-		green_led {
-			label = "licheepi:green:usr";
-			gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
-			default-state = "on";
-		};
-
-		red_led {
-			label = "licheepi:red:usr";
-			gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
-		};
-	};
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
deleted file mode 100644
index b3a32534762..00000000000
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <[email protected]>
- * Copyright (C) 2021 Tobias Schramm <[email protected]>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/sun6i-rtc.h>
-#include <dt-bindings/clock/sun8i-v3s-ccu.h>
-#include <dt-bindings/reset/sun8i-v3s-ccu.h>
-#include <dt-bindings/clock/sun8i-de2.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	interrupt-parent = <&gic>;
-
-	chosen {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		framebuffer-lcd {
-			compatible = "allwinner,simple-framebuffer",
-				     "simple-framebuffer";
-			allwinner,pipeline = "mixer0-lcd0";
-			clocks = <&display_clocks CLK_MIXER0>,
-				 <&ccu CLK_TCON0>;
-			status = "disabled";
-		};
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			compatible = "arm,cortex-a7";
-			device_type = "cpu";
-			reg = <0>;
-			clocks = <&ccu CLK_CPU>;
-		};
-	};
-
-	de: display-engine {
-		compatible = "allwinner,sun8i-v3s-display-engine";
-		allwinner,pipelines = <&mixer0>;
-		status = "disabled";
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		osc24M: osc24M-clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-			clock-accuracy = <50000>;
-			clock-output-names = "osc24M";
-		};
-
-		osc32k: osc32k-clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			clock-accuracy = <50000>;
-			clock-output-names = "ext-osc32k";
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		display_clocks: clock@1000000 {
-			compatible = "allwinner,sun8i-v3s-de2-clk";
-			reg = <0x01000000 0x10000>;
-			clocks = <&ccu CLK_BUS_DE>,
-				 <&ccu CLK_DE>;
-			clock-names = "bus",
-				      "mod";
-			resets = <&ccu RST_BUS_DE>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		mixer0: mixer@1100000 {
-			compatible = "allwinner,sun8i-v3s-de2-mixer";
-			reg = <0x01100000 0x100000>;
-			clocks = <&display_clocks 0>,
-				 <&display_clocks 6>;
-			clock-names = "bus",
-				      "mod";
-			resets = <&display_clocks 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				mixer0_out: port@1 {
-					reg = <1>;
-
-					mixer0_out_tcon0: endpoint {
-						remote-endpoint = <&tcon0_in_mixer0>;
-					};
-				};
-			};
-		};
-
-		syscon: system-control@1c00000 {
-			compatible = "allwinner,sun8i-v3s-system-control",
-				     "allwinner,sun8i-h3-system-control";
-			reg = <0x01c00000 0xd0>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-		};
-
-		nmi_intc: interrupt-controller@1c000d0 {
-			compatible = "allwinner,sun8i-v3s-nmi",
-				     "allwinner,sun9i-a80-nmi";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			reg = <0x01c000d0 0x0c>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		dma: dma-controller@1c02000 {
-			compatible = "allwinner,sun8i-v3s-dma";
-			reg = <0x01c02000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_DMA>;
-			resets = <&ccu RST_BUS_DMA>;
-			#dma-cells = <1>;
-		};
-
-		tcon0: lcd-controller@1c0c000 {
-			compatible = "allwinner,sun8i-v3s-tcon";
-			reg = <0x01c0c000 0x1000>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_TCON0>,
-				 <&ccu CLK_TCON0>;
-			clock-names = "ahb",
-				      "tcon-ch0";
-			clock-output-names = "tcon-data-clock";
-			#clock-cells = <0>;
-			resets = <&ccu RST_BUS_TCON0>;
-			reset-names = "lcd";
-			status = "disabled";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				tcon0_in: port@0 {
-					reg = <0>;
-
-					tcon0_in_mixer0: endpoint {
-						remote-endpoint = <&mixer0_out_tcon0>;
-					};
-				};
-
-				tcon0_out: port@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <1>;
-				};
-			};
-		};
-
-
-		mmc0: mmc@1c0f000 {
-			compatible = "allwinner,sun7i-a20-mmc";
-			reg = <0x01c0f000 0x1000>;
-			clocks = <&ccu CLK_BUS_MMC0>,
-				 <&ccu CLK_MMC0>,
-				 <&ccu CLK_MMC0_OUTPUT>,
-				 <&ccu CLK_MMC0_SAMPLE>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ccu RST_BUS_MMC0>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&mmc0_pins>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		mmc1: mmc@1c10000 {
-			compatible = "allwinner,sun7i-a20-mmc";
-			reg = <0x01c10000 0x1000>;
-			clocks = <&ccu CLK_BUS_MMC1>,
-				 <&ccu CLK_MMC1>,
-				 <&ccu CLK_MMC1_OUTPUT>,
-				 <&ccu CLK_MMC1_SAMPLE>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ccu RST_BUS_MMC1>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&mmc1_pins>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		mmc2: mmc@1c11000 {
-			compatible = "allwinner,sun7i-a20-mmc";
-			reg = <0x01c11000 0x1000>;
-			clocks = <&ccu CLK_BUS_MMC2>,
-				 <&ccu CLK_MMC2>,
-				 <&ccu CLK_MMC2_OUTPUT>,
-				 <&ccu CLK_MMC2_SAMPLE>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ccu RST_BUS_MMC2>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		crypto@1c15000 {
-			compatible = "allwinner,sun8i-v3s-crypto",
-				     "allwinner,sun8i-a33-crypto";
-			reg = <0x01c15000 0x1000>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
-			clock-names = "ahb", "mod";
-			dmas = <&dma 16>, <&dma 16>;
-			dma-names = "rx", "tx";
-			resets = <&ccu RST_BUS_CE>;
-			reset-names = "ahb";
-		};
-
-		usb_otg: usb@1c19000 {
-			compatible = "allwinner,sun8i-h3-musb";
-			reg = <0x01c19000 0x0400>;
-			clocks = <&ccu CLK_BUS_OTG>;
-			resets = <&ccu RST_BUS_OTG>;
-			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "mc";
-			phys = <&usbphy 0>;
-			phy-names = "usb";
-			extcon = <&usbphy 0>;
-			status = "disabled";
-		};
-
-		usbphy: phy@1c19400 {
-			compatible = "allwinner,sun8i-v3s-usb-phy";
-			reg = <0x01c19400 0x2c>,
-			      <0x01c1a800 0x4>;
-			reg-names = "phy_ctrl",
-				    "pmu0";
-			clocks = <&ccu CLK_USB_PHY0>;
-			clock-names = "usb0_phy";
-			resets = <&ccu RST_USB_PHY0>;
-			reset-names = "usb0_reset";
-			status = "disabled";
-			#phy-cells = <1>;
-		};
-
-		ehci: usb@1c1a000 {
-			compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
-			reg = <0x01c1a000 0x100>;
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
-			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
-			phys = <&usbphy 0>;
-			phy-names = "usb";
-			status = "disabled";
-		};
-
-		ohci: usb@1c1a400 {
-			compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
-			reg = <0x01c1a400 0x100>;
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
-				 <&ccu CLK_USB_OHCI0>;
-			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
-			phys = <&usbphy 0>;
-			phy-names = "usb";
-			status = "disabled";
-		};
-
-		ccu: clock@1c20000 {
-			compatible = "allwinner,sun8i-v3s-ccu";
-			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-			clock-names = "hosc", "losc";
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		rtc: rtc@1c20400 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun8i-v3-rtc";
-			reg = <0x01c20400 0x54>;
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc32k>;
-			clock-output-names = "osc32k", "osc32k-out";
-		};
-
-		pio: pinctrl@1c20800 {
-			compatible = "allwinner,sun8i-v3s-pinctrl";
-			reg = <0x01c20800 0x400>;
-			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
-				 <&rtc CLK_OSC32K>;
-			clock-names = "apb", "hosc", "losc";
-			gpio-controller;
-			#gpio-cells = <3>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-
-			/omit-if-no-ref/
-			csi0_mclk_pin: csi0-mclk-pin {
-				pins = "PE20";
-				function = "csi_mipi";
-			};
-
-			/omit-if-no-ref/
-			csi1_8bit_pins: csi1-8bit-pins {
-				pins = "PE0", "PE2", "PE3", "PE8", "PE9",
-				       "PE10", "PE11", "PE12", "PE13", "PE14",
-				       "PE15";
-				function = "csi";
-			};
-
-			/omit-if-no-ref/
-			csi1_mclk_pin: csi1-mclk-pin {
-				pins = "PE1";
-				function = "csi";
-			};
-
-			i2c0_pins: i2c0-pins {
-				pins = "PB6", "PB7";
-				function = "i2c0";
-			};
-
-			/omit-if-no-ref/
-			i2c1_pb_pins: i2c1-pb-pins {
-				pins = "PB8", "PB9";
-				function = "i2c1";
-			};
-
-			/omit-if-no-ref/
-			i2c1_pe_pins: i2c1-pe-pins {
-				pins = "PE21", "PE22";
-				function = "i2c1";
-			};
-
-			uart0_pb_pins: uart0-pb-pins {
-				pins = "PB8", "PB9";
-				function = "uart0";
-			};
-
-			uart2_pins: uart2-pins {
-				pins = "PB0", "PB1";
-				function = "uart2";
-			};
-
-			mmc0_pins: mmc0-pins {
-				pins = "PF0", "PF1", "PF2", "PF3",
-				       "PF4", "PF5";
-				function = "mmc0";
-				drive-strength = <30>;
-				bias-pull-up;
-			};
-
-			mmc1_pins: mmc1-pins {
-				pins = "PG0", "PG1", "PG2", "PG3",
-				       "PG4", "PG5";
-				function = "mmc1";
-				drive-strength = <30>;
-				bias-pull-up;
-			};
-
-			/omit-if-no-ref/
-			pwm0_pin: pwm0-pin {
-				pins = "PB4";
-				function = "pwm0";
-			};
-
-			/omit-if-no-ref/
-			pwm1_pin: pwm1-pin {
-				pins = "PB5";
-				function = "pwm1";
-			};
-
-			spi0_pins: spi0-pins {
-				pins = "PC0", "PC1", "PC2", "PC3";
-				function = "spi0";
-			};
-		};
-
-		timer@1c20c00 {
-			compatible = "allwinner,sun8i-v3s-timer";
-			reg = <0x01c20c00 0xa0>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc24M>;
-		};
-
-		wdt0: watchdog@1c20ca0 {
-			compatible = "allwinner,sun6i-a31-wdt";
-			reg = <0x01c20ca0 0x20>;
-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc24M>;
-		};
-
-		pwm: pwm@1c21400 {
-			compatible = "allwinner,sun8i-v3s-pwm",
-				     "allwinner,sun7i-a20-pwm";
-			reg = <0x01c21400 0xc>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-
-		lradc: lradc@1c22800 {
-			compatible = "allwinner,sun4i-a10-lradc-keys";
-			reg = <0x01c22800 0x400>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		codec: codec@1c22c00 {
-			#sound-dai-cells = <0>;
-			compatible = "allwinner,sun8i-v3s-codec";
-			reg = <0x01c22c00 0x400>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
-			clock-names = "apb", "codec";
-			resets = <&ccu RST_BUS_CODEC>;
-			dmas = <&dma 15>, <&dma 15>;
-			dma-names = "rx", "tx";
-			allwinner,codec-analog-controls = <&codec_analog>;
-			status = "disabled";
-		};
-
-		codec_analog: codec-analog@1c23000 {
-			compatible = "allwinner,sun8i-v3s-codec-analog";
-			reg = <0x01c23000 0x4>;
-		};
-
-		uart0: serial@1c28000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28000 0x400>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&ccu CLK_BUS_UART0>;
-			dmas = <&dma 6>, <&dma 6>;
-			dma-names = "tx", "rx";
-			resets = <&ccu RST_BUS_UART0>;
-			status = "disabled";
-		};
-
-		uart1: serial@1c28400 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28400 0x400>;
-			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&ccu CLK_BUS_UART1>;
-			dmas = <&dma 7>, <&dma 7>;
-			dma-names = "tx", "rx";
-			resets = <&ccu RST_BUS_UART1>;
-			status = "disabled";
-		};
-
-		uart2: serial@1c28800 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28800 0x400>;
-			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&ccu CLK_BUS_UART2>;
-			dmas = <&dma 8>, <&dma 8>;
-			dma-names = "tx", "rx";
-			resets = <&ccu RST_BUS_UART2>;
-			pinctrl-0 = <&uart2_pins>;
-			pinctrl-names = "default";
-			status = "disabled";
-		};
-
-		i2c0: i2c@1c2ac00 {
-			compatible = "allwinner,sun6i-a31-i2c";
-			reg = <0x01c2ac00 0x400>;
-			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_I2C0>;
-			resets = <&ccu RST_BUS_I2C0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c0_pins>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		i2c1: i2c@1c2b000 {
-			compatible = "allwinner,sun6i-a31-i2c";
-			reg = <0x01c2b000 0x400>;
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_I2C1>;
-			resets = <&ccu RST_BUS_I2C1>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		emac: ethernet@1c30000 {
-			compatible = "allwinner,sun8i-v3s-emac";
-			syscon = <&syscon>;
-			reg = <0x01c30000 0x10000>;
-			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			resets = <&ccu RST_BUS_EMAC>;
-			reset-names = "stmmaceth";
-			clocks = <&ccu CLK_BUS_EMAC>;
-			clock-names = "stmmaceth";
-			phy-handle = <&int_mii_phy>;
-			phy-mode = "mii";
-			status = "disabled";
-
-			mdio: mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "snps,dwmac-mdio";
-			};
-
-			mdio_mux: mdio-mux {
-				compatible = "allwinner,sun8i-h3-mdio-mux";
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				mdio-parent-bus = <&mdio>;
-				/* Only one MDIO is usable at the time */
-				internal_mdio: mdio@1 {
-					compatible = "allwinner,sun8i-h3-mdio-internal";
-					reg = <1>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					int_mii_phy: ethernet-phy@1 {
-						compatible = "ethernet-phy-ieee802.3-c22";
-						reg = <1>;
-						clocks = <&ccu CLK_BUS_EPHY>;
-						resets = <&ccu RST_BUS_EPHY>;
-					};
-				};
-			};
-		};
-
-		spi0: spi@1c68000 {
-			compatible = "allwinner,sun8i-h3-spi";
-			reg = <0x01c68000 0x1000>;
-			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-			clock-names = "ahb", "mod";
-			dmas = <&dma 23>, <&dma 23>;
-			dma-names = "rx", "tx";
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_pins>;
-			resets = <&ccu RST_BUS_SPI0>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		gic: interrupt-controller@1c81000 {
-			compatible = "arm,gic-400";
-			reg = <0x01c81000 0x1000>,
-			      <0x01c82000 0x2000>,
-			      <0x01c84000 0x2000>,
-			      <0x01c86000 0x2000>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		};
-
-		csi1: camera@1cb4000 {
-			compatible = "allwinner,sun8i-v3s-csi";
-			reg = <0x01cb4000 0x3000>;
-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_CSI>,
-				 <&ccu CLK_CSI_SCLK>,
-				 <&ccu CLK_DRAM_CSI>;
-			clock-names = "bus", "mod", "ram";
-			resets = <&ccu RST_BUS_CSI>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 0d915d496ca..60ac5085f73 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -20,6 +20,11 @@
 		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
 	model = "ZynqMP KR260 revB";
 
+	aliases {
+		ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
+		ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
+	};
+
 	ina260-u14 {
 		compatible = "iio-hwmon";
 		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index 13f13ca7d10..f973652d0cb 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -635,7 +635,8 @@ enum env_location env_get_location(enum env_operation op, int prio)
 
 	switch (dev) {
 	case QSPI_BOOT:
-		env_loc = ENVL_SPI_FLASH;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			env_loc = ENVL_SPI_FLASH;
 		break;
 	case SD1_BOOT:
 	case SD2_BOOT:
@@ -643,10 +644,16 @@ enum env_location env_get_location(enum env_operation op, int prio)
 	case MMC1_BOOT:
 	case MMC2_BOOT:
 	case MMC3_BOOT:
-		env_loc =  ENVL_MMC;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+			env_loc =  ENVL_MMC;
 		break;
 	default:
-		env_loc = ENVL_NOWHERE;
+		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+			env_loc = ENVL_NOWHERE;
+		else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			env_loc = ENVL_SPI_FLASH;
+		else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+			env_loc = ENVL_MMC;
 		break;
 	}
 
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9fb82644f12..3f7dafdcce5 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -809,7 +809,13 @@ enum env_location env_get_location(enum env_operation op, int prio)
 			return ENVL_FAT;
 		return ENVL_NOWHERE;
 	default:
-		return ENVL_NOWHERE;
+		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+			return ENVL_NOWHERE;
+		else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+			return ENVL_MMC;
+		return ENVL_UNKNOWN;
 	}
 }
 
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index fc921a4be26..5fb3240acc5 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -534,8 +534,7 @@ int board_late_init(void)
 		env_set_hex("ramdisk_addr_r", addr) : 1;
 	status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ?
 		env_set_hex("kernel_comp_addr_r", addr) : 1;
-	status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ?
-		env_set_hex("kernel_comp_size", addr) : 1;
+	status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
 	status |= !lmb_alloc(SZ_4M, &addr) ?
 		env_set_hex("scriptaddr", addr) : 1;
 	status |= !lmb_alloc(SZ_4M, &addr) ?
@@ -544,9 +543,13 @@ int board_late_init(void)
 	if (IS_ENABLED(CONFIG_FASTBOOT)) {
 		status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ?
 			env_set_hex("fastboot_addr_r", addr) : 1;
-		/* override loadaddr for memory rich soc */
-		status |= !lmb_alloc(SZ_128M, &addr) ?
-			env_set_hex("loadaddr", addr) : 1;
+		/*
+		 * Override loadaddr for memory rich soc since ${loadaddr} and
+		 * ${kernel_addr_r} need to be different for the Android boot image
+		 * flow. It's typically safe for ${loadaddr} to be the same address
+		 * as the fastboot buffer.
+		 */
+		status |= env_set_hex("loadaddr", addr);
 	}
 
 	fdt_status |= !lmb_alloc(SZ_2M, &addr) ?
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6a511c4fd39..b04ec671696 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -487,6 +487,7 @@ config MACH_SUN8I_V3S
 	select SUNXI_DRAM_DW_16BIT
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+	imply OF_UPSTREAM
 
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
@@ -718,9 +719,9 @@ config DRAM_CLK
 	int "sunxi dram clock speed"
 	default 792 if MACH_SUN9I
 	default 648 if MACH_SUN8I_R40
-	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
 		       MACH_SUN8I_V3S
+	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 672 if MACH_SUN50I
 	default 744 if MACH_SUN50I_H6
 	default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index fb4837c2082..432b1c10f92 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -476,8 +476,8 @@ void board_init_f(ulong dummy)
 	/* Enable non-secure access to some peripherals */
 	tzpc_init();
 
-	clock_init();
 	timer_init();
+	clock_init();
 	gpio_init();
 
 	spl_init();
diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c
index 3a231141168..1496f99624d 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_a133.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c
@@ -416,7 +416,7 @@ static void mctl_com_init(const struct dram_para *para,
 static void mctl_drive_odt_config(const struct dram_para *para)
 {
 	u32 val;
-	u64 base;
+	ulong base;
 	u32 i;
 
 	/* DX drive */
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 877181016f3..3345c9b8e82 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -1078,18 +1078,18 @@ static bool mctl_phy_init(const struct dram_para *para,
 		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
 		break;
 	case SUNXI_DRAM_TYPE_LPDDR3:
-		writel(mr0, &mctl_ctl->mrctrl1);
-		writel(0x800000f0, &mctl_ctl->mrctrl0);
-		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
-
-		writel(4, &mctl_ctl->mrctrl1);
+		/* MR0 is read-only */
+		/* MR1: nWR=14, BL8 */
+		writel(0x183, &mctl_ctl->mrctrl1);
 		writel(0x800000f0, &mctl_ctl->mrctrl0);
 		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
 
-		writel(mr2, &mctl_ctl->mrctrl1);
+		/* MR2: no WR leveling, WL set A, use nWR>9, nRL=14/nWL=8 */
+		writel(0x21c, &mctl_ctl->mrctrl1);
 		writel(0x800000f0, &mctl_ctl->mrctrl0);
 		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
 
+		/* MR3: 34.3 Ohm pull-up/pull-down resistor */
 		writel(0x301, &mctl_ctl->mrctrl1);
 		writel(0x800000f0, &mctl_ctl->mrctrl0);
 		mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8c6feae5735..04eb0e6f23c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_ANDES_AE350
 	bool "Support Andes ae350"
 
+config TARGET_ANDES_VOYAGER
+	bool "Support Andes Voyager Board"
+
 config TARGET_BANANAPI_F3
 	bool "Support BananaPi F3 Board"
 
@@ -101,6 +104,7 @@ config SPL_ZERO_MEM_BEFORE_USE
 
 # board-specific options below
 source "board/andestech/ae350/Kconfig"
+source "board/andestech/voyager/Kconfig"
 source "board/aspeed/ibex_ast2700/Kconfig"
 source "board/canaan/k230_canmv/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 15c4e14599d..d5123e4b7d9 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -608,14 +608,14 @@ static inline bool supports_extension(char ext)
 
 static int riscv_cpu_probe(void)
 {
-#ifdef CONFIG_CPU
-	int ret;
+	if (CONFIG_IS_ENABLED(CPU)) {
+		int ret;
 
-	/* probe cpus so that RISC-V timer can be bound */
-	ret = cpu_probe_all();
-	if (ret)
-		return log_msg_ret("RISC-V cpus probe failed\n", ret);
-#endif
+		/* probe cpus so that RISC-V timer can be bound */
+		ret = cpu_probe_all();
+		if (ret)
+			return log_msg_ret("RISC-V cpus probe failed\n", ret);
+	}
 
 	return 0;
 }
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 2b10c2d6c01..a637727b76b 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb
 dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb
 dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
@@ -14,6 +15,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
 dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
 
 include $(srctree)/scripts/Makefile.dts
diff --git a/arch/riscv/dts/qilai-voyager.dts b/arch/riscv/dts/qilai-voyager.dts
new file mode 100644
index 00000000000..44933529f89
--- /dev/null
+++ b/arch/riscv/dts/qilai-voyager.dts
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "binman.dtsi"
+#include "voyager-u-boot.dtsi"
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	compatible = "andestech,voyager", "andestech,qilai";
+	model = "Voyager";
+
+	aliases {
+		uart0 = &serial0;
+		spi0 = &spi;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7";
+		stdout-path = "uart0:115200n8";
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x3938700>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <0x1>;
+			riscv,priv-minor = <0xa>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <0x3938700>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x20>;
+			next-level-cache = <&L2>;
+
+			CPU0_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			reg = <0x1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <0x1>;
+			riscv,priv-minor = <0xa>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <0x3938700>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x20>;
+			next-level-cache = <&L2>;
+
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			reg = <0x2>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <0x1>;
+			riscv,priv-minor = <0xa>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <0x3938700>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x20>;
+			next-level-cache = <&L2>;
+
+			CPU2_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			reg = <0x3>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <0x1>;
+			riscv,priv-minor = <0xa>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <0x3938700>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x20>;
+			next-level-cache = <&L2>;
+
+			CPU3_intc: interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	L2: l2-cache@200000 {
+		compatible = "cache";
+		cache-level = <0x2>;
+		cache-size = <0x40000>;
+		reg = <0x0 0x00200000 0x0 0x100000>;
+		andes,inst-prefetch = <0x3>;
+		andes,data-prefetch = <0x3>;
+		andes,tag-ram-ctl = <0x0 0x0>;
+		andes,data-ram-ctl = <0x0 0x0>;
+	};
+
+	memory@400000000 {
+		device_type = "memory";
+		reg = <0x04 0x00000000 0x0 0x40000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "simple-bus";
+		ranges;
+
+		plic0: interrupt-controller@2000000 {
+			compatible = "riscv,plic0";
+			#address-cells = <0x2>;
+			#interrupt-cells = <0x2>;
+			interrupt-controller;
+			reg = <0x0 0x02000000 0x0 0x2000000>;
+			riscv,ndev = <0x47>;
+			interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
+					       &CPU1_intc 11 &CPU1_intc 9
+					       &CPU2_intc 11 &CPU2_intc 9
+					       &CPU3_intc 11 &CPU3_intc 9>;
+		};
+
+		plic1: interrupt-controller@400000 {
+			compatible = "andestech,plicsw";
+			#address-cells = <0x2>;
+			#interrupt-cells = <0x2>;
+			interrupt-controller;
+			reg = <0x0 0x00400000 0x0 0x400000>;
+			riscv,ndev = <0x1>;
+			interrupts-extended = <&CPU0_intc 3
+					       &CPU1_intc 3
+					       &CPU2_intc 3
+					       &CPU3_intc 3>;
+		};
+
+		plmt0@100000 {
+			compatible = "andestech,plmt0";
+			reg = <0x0 0x00100000 0x0 0x100000>;
+			interrupts-extended = <&CPU0_intc 7
+					       &CPU1_intc 7
+					       &CPU2_intc 7
+					       &CPU3_intc 7>;
+		};
+	};
+
+	spiclk: virt_100mhz {
+		#clock-cells = <0x0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x5f5e100>;
+	};
+
+	serial0: serial@30300000 {
+		compatible = "andestech,uart16550", "ns16550a";
+		reg = <0x0 0x30300000 0x0 0x1000>;
+		interrupts = <0x9 0x4>;
+		clock-frequency = <0x12c0000>;
+		reg-shift = <0x2>;
+		reg-offset = <0x20>;
+		no-loopback-test = <0x1>;
+		interrupt-parent = <&plic0>;
+	};
+
+	mmc0: mmc@30c00000 {
+		compatible = "andestech,atfsdc010";
+		max-frequency = <0x5f5e100>;
+		clock-freq-min-max = <0x61a80 0x5f5e100>;
+		fifo-depth = <0x10>;
+		reg = <0x0 0x30c00000 0x0 0x1000>;
+		interrupts = <0x12 0x4>;
+		cap-sd-highspeed;
+		interrupt-parent = <&plic0>;
+		dma-coherent;
+	};
+
+	spi: spi@30900000 {
+		compatible = "andestech,atcspi200";
+		reg = <0x0 0x30900000 0x0 0x100000>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		num-cs = <0x1>;
+		clocks = <&spiclk>;
+		interrupts = <0x4 0x4>;
+		interrupt-parent = <&plic0>;
+
+		flash@0 {
+			compatible = "mx25u1635e", "jedec,spi-nor";
+			spi-max-frequency = <0x2faf080>;
+			reg = <0x0>;
+			spi-cpol;
+			spi-cpha;
+		};
+	};
+};
diff --git a/arch/riscv/dts/voyager-u-boot.dtsi b/arch/riscv/dts/voyager-u-boot.dtsi
new file mode 100644
index 00000000000..cef0aa08b37
--- /dev/null
+++ b/arch/riscv/dts/voyager-u-boot.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+	cpus {
+		bootph-pre-ram;
+		CPU0: cpu@0 {
+			bootph-pre-ram;
+			CPU0_intc: interrupt-controller {
+				bootph-pre-ram;
+			};
+		};
+		CPU1: cpu@1 {
+			bootph-pre-ram;
+			CPU1_intc: interrupt-controller {
+				bootph-pre-ram;
+			};
+		};
+		CPU2: cpu@2 {
+			bootph-pre-ram;
+			CPU2_intc: interrupt-controller {
+				bootph-pre-ram;
+			};
+		};
+		CPU3: cpu@3 {
+			bootph-pre-ram;
+			CPU3_intc: interrupt-controller {
+				bootph-pre-ram;
+			};
+		};
+	};
+
+	memory@0 {
+		bootph-pre-ram;
+	};
+
+	soc {
+		bootph-pre-ram;
+
+		plic1: interrupt-controller@400000 {
+			bootph-pre-ram;
+		};
+
+		plmt0@100000 {
+			bootph-pre-ram;
+		};
+	};
+
+	serial0: serial@30300000 {
+		bootph-pre-ram;
+	};
+
+};
diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts
new file mode 100644
index 00000000000..715080ed763
--- /dev/null
+++ b/arch/riscv/dts/xilinx-binman.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * binman file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2025, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 4050ce2f051..f7a3e076fd5 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -2,15 +2,13 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
 
 /dts-v1/;
 
-#include "binman.dtsi"
-
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -26,6 +24,7 @@
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv32imafdc";
+			mmu-type = "riscv,sv39";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;
@@ -70,7 +69,8 @@
 			interrupt-controller;
 			interrupt-parent = <&cpu0_intc>;
 			#interrupt-cells = <2>;
-			kind-of-intr = <0>;
+			xlnx,num-intr-inputs = <2>;
+			xlnx,kind-of-intr = <0>;
 		};
 
 		xlnx_timer0: timer@41c00000 {
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 4d65d338ecb..e6235ed2f52 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -2,15 +2,13 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */
 
 /dts-v1/;
 
-#include "binman.dtsi"
-
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -26,6 +24,7 @@
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;
@@ -70,7 +69,8 @@
 			interrupt-controller;
 			interrupt-parent = <&cpu0_intc>;
 			#interrupt-cells = <2>;
-			kind-of-intr = <0>;
+			xlnx,num-intr-inputs = <2>;
+			xlnx,kind-of-intr = <0>;
 		};
 
 		xlnx_timer0: timer@41c00000 {
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 9884077c933..e5479bbe84e 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/memcpy.S
@@ -125,6 +125,14 @@ WEAK(memcpy)
 .copy_end:
 	ret
 
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define M_SLL sll
+#define M_SRL srl
+#else
+#define M_SLL srl
+#define M_SRL sll
+#endif
+
 .Lmisaligned_word_copy:
 	/*
 	 * Misaligned word-wise copy.
@@ -144,10 +152,10 @@ WEAK(memcpy)
 	addi	t0, t0, -(SZREG-1)
 	/* At least one iteration will be executed here, no check */
 1:
-	srl	a4, a5, t3
+	M_SRL	a4, a5, t3
 	REG_L	a5, SZREG(a1)
 	addi	a1, a1, SZREG
-	sll	a2, a5, t4
+	M_SLL	a2, a5, t4
 	or	a2, a2, a4
 	REG_S	a2, 0(a0)
 	addi	a0, a0, SZREG
diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S
index fbe6701dbe4..b2c1c736713 100644
--- a/arch/riscv/lib/memmove.S
+++ b/arch/riscv/lib/memmove.S
@@ -91,6 +91,14 @@ WEAK(memmove)
 	mv	a0, t0
 	ret
 
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define M_SLL sll
+#define M_SRL srl
+#else
+#define M_SLL srl
+#define M_SRL sll
+#endif
+
 .Lmisaligned_word_copy:
 	/*
 	 * Misaligned word-wise copy.
@@ -110,10 +118,10 @@ WEAK(memmove)
 	addi	t0, t0, SZREG-1
 	/* At least one iteration will be executed here, no check */
 1:
-	sll	a4, a5, t4
+	M_SLL	a4, a5, t4
 	addi	a1, a1, -SZREG
 	REG_L	a5, 0(a1)
-	srl	a2, a5, t3
+	M_SRL	a2, a5, t3
 	or	a2, a2, a4
 	addi	a0, a0, -SZREG
 	REG_S	a2, 0(a0)