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authorSimon Glass <[email protected]>2011-09-21 12:40:02 +0000
committerAlbert ARIBAUD <[email protected]>2011-10-27 21:56:29 +0200
commit03c609f69b12dca47b9422595fdde29be1fb35c9 (patch)
treeaa4e9f2bb9ac562ace58b5891d7001704ef8d812 /board/eNET/eNET.c
parentc30a15e590c7e5bfd27e4704c81648071f11d51f (diff)
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the code now deals with both PLL clocks and source clocks. This also tidied up the assert() to match the one sent upstream, and fixes an error in the PWM id. Signed-off-by: Simon Glass <[email protected]> Tested-by: Tom Warren <[email protected]>
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