diff options
| author | Ye Li <[email protected]> | 2019-05-15 09:56:59 +0000 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2019-07-19 20:14:50 +0200 |
| commit | 9c1563e3fd24ca7161c089dfd999d031f95094de (patch) | |
| tree | 2427c80f845acaaaca1c198f46f06fa63c89a0c2 /board/freescale/mx7ulp_evk/plugin.S | |
| parent | 285aea01d2f9398b9c127c7a7fbaa401adf6969f (diff) | |
mx7ulp: Select the SCG1 APLL PFD as a system clock source
Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Peng Fan <[email protected]>
Diffstat (limited to 'board/freescale/mx7ulp_evk/plugin.S')
| -rw-r--r-- | board/freescale/mx7ulp_evk/plugin.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index ccd2fc03a43..55dfecc7512 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -18,7 +18,7 @@ ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00160000 + ldr r3, =0x00160002 str r3, [r2, #0x508] ldr r3, =0x00000002 str r3, [r2, #0x510] |