board: microsoft: surface-rt: add Microsoft Surface RT support

Surface RT is a hybrid tablet computer developed and manufactured
by Microsoft and shipped with Windows RT. The tablet uses a 1.3 GHz
quad-core Nvidia Tegra 3 chipset with 2 GB of RAM, features 10.8
inch 1366x768 screen and 32/64 GB of internal memory that can be
supplemented with a microSDXC card giving up to 200 GB of
additional storage.

Tested-by: Jethro Bull <[email protected]>
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>

4 files changed, 66 insertions, 0 deletions

diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig
new file mode 100644
index 00000000000..9e66897f6b1
--- /dev/null
+++ b/board/microsoft/surface-rt/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SURFACE_RT
+
+config SYS_BOARD
+	default "surface-rt"
+
+config SYS_VENDOR
+	default "microsoft"
+
+config SYS_CONFIG_NAME
+	default "surface-rt"
+
+endif
diff --git a/board/microsoft/surface-rt/MAINTAINERS b/board/microsoft/surface-rt/MAINTAINERS
new file mode 100644
index 00000000000..1bbd896de92
--- /dev/null
+++ b/board/microsoft/surface-rt/MAINTAINERS
@@ -0,0 +1,7 @@
+Microsoft Surface RT
+M:	Jonas Schwöbel <[email protected]>
+S:	Maintained
+F:	board/microsoft/surface-rt/
+F:	configs/surface-rt_defconfig
+F:	doc/board/microsoft/surface-rt.rst
+F:	include/configs/surface-rt.h
diff --git a/board/microsoft/surface-rt/Makefile b/board/microsoft/surface-rt/Makefile
new file mode 100644
index 00000000000..da4094a7df3
--- /dev/null
+++ b/board/microsoft/surface-rt/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2021
+#  Open Surface RT
+
+obj-$(CONFIG_SPL_BUILD) += surface-rt-spl.o
diff --git a/board/microsoft/surface-rt/surface-rt-spl.c b/board/microsoft/surface-rt/surface-rt-spl.c
new file mode 100644
index 00000000000..f327a80efba
--- /dev/null
+++ b/board/microsoft/surface-rt/surface-rt-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  Surface RT SPL stage configuration
+ *
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2021
+ *  Svyatoslav Ryhel <[email protected]>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR		(0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR		(0x60 << 1)
+#define TPS62361B_SET3_REG		0x03
+#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set VDD_CORE to 1.200V. */
+	tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+	udelay(1000);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}