diff options
| author | Wadim Egorov <[email protected]> | 2024-02-28 09:42:16 +0100 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-03-07 07:59:15 -0500 |
| commit | 46b3ff8205c714d5038cc57efecd29f96769925d (patch) | |
| tree | 1a409c413954c5e37c1a687a7d7a3754edaad162 /board/phytec | |
| parent | 9522956605205d23fe99142547ca3227574d418a (diff) | |
board: phytec: am64x: Add PHYTEC phyCORE-AM64x SoM
Add support for PHYTEC phyCORE-AM64x SoM.
Supported features:
- 2GB DDR4 RAM
- eMMC Flash
- external uSD
- OSPI NOR Flash
- debug UART
Product page SoM: https://www.phytec.com/product/phycore-am64x
Device trees were taken from Linux v6.8-rc2.
Signed-off-by: Wadim Egorov <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/phycore_am64x/Kconfig | 33 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/MAINTAINERS | 15 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/Makefile | 9 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/board-cfg.yaml | 36 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/phycore-am64x.c | 50 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/phycore_am64x.env | 23 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/pm-cfg.yaml | 12 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/rm-cfg.yaml | 1215 | ||||
| -rw-r--r-- | board/phytec/phycore_am64x/sec-cfg.yaml | 379 |
9 files changed, 1772 insertions, 0 deletions
diff --git a/board/phytec/phycore_am64x/Kconfig b/board/phytec/phycore_am64x/Kconfig new file mode 100644 index 00000000000..427adb6fedd --- /dev/null +++ b/board/phytec/phycore_am64x/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com +# Author: Matt McKee <[email protected]> +# +# Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH +# Author: Wadim Egorov <[email protected]> + +if TARGET_PHYCORE_AM64X_A53 + +config SYS_BOARD + default "phycore_am64x" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_am64x" + +endif + +if TARGET_PHYCORE_AM64X_R5 + +config SYS_BOARD + default "phycore_am64x" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_am64x" + +endif diff --git a/board/phytec/phycore_am64x/MAINTAINERS b/board/phytec/phycore_am64x/MAINTAINERS new file mode 100644 index 00000000000..caa9bbc97c4 --- /dev/null +++ b/board/phytec/phycore_am64x/MAINTAINERS @@ -0,0 +1,15 @@ +phyCORE-AM64x +M: Wadim Egorov <[email protected]> +W: https://www.phytec.com/product/phycore-am64x +S: Maintained +F: arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi +F: arch/arm/dts/k3-am64-phycore-som.dtsi +F: arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +F: arch/arm/dts/k3-am642-phyboard-electra-rdk.dts +F: arch/arm/dts/k3-am642-phycore-som-binman.dtsi +F: arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts +F: board/phytec/phycore_am64x +F: configs/phycore_am64x_a53_defconfig +F: configs/phycore_am64x_r5_defconfig +F: doc/board/phytec/phycore-am64x.rst +F: include/configs/phycore_am64x.h diff --git a/board/phytec/phycore_am64x/Makefile b/board/phytec/phycore_am64x/Makefile new file mode 100644 index 00000000000..78b8f1b1b81 --- /dev/null +++ b/board/phytec/phycore_am64x/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com +# Author: Matt McKee <[email protected]> +# +# Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH +# Author: Wadim Egorov <[email protected]> + +obj-y += phycore-am64x.o diff --git a/board/phytec/phycore_am64x/board-cfg.yaml b/board/phytec/phycore_am64x/board-cfg.yaml new file mode 100644 index 00000000000..8981b75caa2 --- /dev/null +++ b/board/phytec/phycore_am64x/board-cfg.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM64x +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c new file mode 100644 index 00000000000..8f3b22657c7 --- /dev/null +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee <[email protected]> + * + * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <[email protected]> + */ + +#include <asm/io.h> +#include <env.h> +#include <env_internal.h> +#include <spl.h> +#include <fdt_support.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 +#define CORE_VOLTAGE 0x80000000 + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + u32 val; + + /* Set USB PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB0_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); +} +#endif diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env new file mode 100644 index 00000000000..ada3a9233be --- /dev/null +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -0,0 +1,23 @@ +fdtaddr=0x88000000 +loadaddr=0x82000000 +scriptaddr=0x80000000 +fdt_addr_r=0x88000000 +kernel_addr_r=0x82000000 +ramdisk_addr_r=0x88080000 +fdtoverlay_addr_r=0x89000000 + +fdtfile=CONFIG_DEFAULT_FDT_FILE +mmcdev=1 +mmcroot=2 +mmcpart=1 +console=ttyS2,115200n8 +mmcargs=setenv bootargs console=${console} earlycon=ns16550a,mmio32,0x02800000 + root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} Image +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile} +mmcboot=run mmcargs; + mmc dev ${mmcdev}; + mmc rescan; + run loadimage; + run loadfdt; + booti ${loadaddr} - ${fdtaddr} diff --git a/board/phytec/phycore_am64x/pm-cfg.yaml b/board/phytec/phycore_am64x/pm-cfg.yaml new file mode 100644 index 00000000000..7afb2962108 --- /dev/null +++ b/board/phytec/phycore_am64x/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM64x +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/phytec/phycore_am64x/rm-cfg.yaml b/board/phytec/phycore_am64x/rm-cfg.yaml new file mode 100644 index 00000000000..88b37b5972c --- /dev/null +++ b/board/phytec/phycore_am64x/rm-cfg.yaml @@ -0,0 +1,1215 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM64x +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 38 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 5 + host_id: 41 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 6 + host_id: 43 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - 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+ start_resource: 16 + num_resource: 16 + type: 1964 + host_id: 35 + reserved: 0 + - + start_resource: 32 + num_resource: 8 + type: 1966 + host_id: 128 + reserved: 0 + - + start_resource: 32 + num_resource: 8 + type: 1968 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + - + start_resource: 40 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + - + start_resource: 20 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 40 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 21 + num_resource: 4 + type: 1973 + host_id: 12 + reserved: 0 + - + start_resource: 48 + num_resource: 64 + type: 1974 + host_id: 12 + reserved: 0 + - + start_resource: 25 + num_resource: 4 + type: 1975 + host_id: 12 + reserved: 0 + - + start_resource: 112 + num_resource: 64 + type: 1976 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 2124 + host_id: 35 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 2124 + host_id: 36 + reserved: 0 + - + start_resource: 22 + num_resource: 2 + type: 2124 + host_id: 38 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 2124 + host_id: 41 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 2124 + host_id: 43 + reserved: 0 + - + start_resource: 28 + num_resource: 4 + type: 2124 + host_id: 128 + reserved: 0 diff --git a/board/phytec/phycore_am64x/sec-cfg.yaml b/board/phytec/phycore_am64x/sec-cfg.yaml new file mode 100644 index 00000000000..b61551c3208 --- /dev/null +++ b/board/phytec/phycore_am64x/sec-cfg.yaml @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM64x +# + +--- + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - # 1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - # 1 + host_id: 0 + supervisor_host_id: 0 + - # 2 + host_id: 0 + supervisor_host_id: 0 + - # 3 + host_id: 0 + supervisor_host_id: 0 + - # 4 + host_id: 0 + supervisor_host_id: 0 + - # 5 + host_id: 0 + supervisor_host_id: 0 + - # 6 + host_id: 0 + supervisor_host_id: 0 + - # 7 + host_id: 0 + supervisor_host_id: 0 + - # 8 + host_id: 0 + supervisor_host_id: 0 + - # 9 + host_id: 0 + supervisor_host_id: 0 + - # 10 + host_id: 0 + supervisor_host_id: 0 + - # 11 + host_id: 0 + supervisor_host_id: 0 + - # 12 + host_id: 0 + supervisor_host_id: 0 + - # 13 + host_id: 0 + supervisor_host_id: 0 + - # 14 + host_id: 0 + supervisor_host_id: 0 + - # 15 + host_id: 0 + supervisor_host_id: 0 + - # 16 + host_id: 0 + supervisor_host_id: 0 + - # 17 + host_id: 0 + supervisor_host_id: 0 + - # 18 + host_id: 0 + supervisor_host_id: 0 + - # 19 + host_id: 0 + supervisor_host_id: 0 + - # 20 + host_id: 0 + supervisor_host_id: 0 + - # 21 + host_id: 0 + supervisor_host_id: 0 + - # 22 + host_id: 0 + supervisor_host_id: 0 + - # 23 + host_id: 0 + supervisor_host_id: 0 + - # 24 + host_id: 0 + supervisor_host_id: 0 + - # 25 + host_id: 0 + supervisor_host_id: 0 + - # 26 + host_id: 0 + supervisor_host_id: 0 + - # 27 + host_id: 0 + supervisor_host_id: 0 + - # 28 + host_id: 0 + supervisor_host_id: 0 + - # 29 + host_id: 0 + supervisor_host_id: 0 + - # 30 + host_id: 0 + supervisor_host_id: 0 + - # 31 + host_id: 0 + supervisor_host_id: 0 + - # 32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + write_host_id: 0 + otp_entry: + - # 1 + host_id: 0 + host_perms: 0 + - # 2 + host_id: 0 + host_perms: 0 + - # 3 + host_id: 0 + host_perms: 0 + - # 4 + host_id: 0 + host_perms: 0 + - # 5 + host_id: 0 + host_perms: 0 + - # 6 + host_id: 0 + host_perms: 0 + - # 7 + host_id: 0 + host_perms: 0 + - # 8 + host_id: 0 + host_perms: 0 + - # 9 + host_id: 0 + host_perms: 0 + - # 10 + host_id: 0 + host_perms: 0 + - # 11 + host_id: 0 + host_perms: 0 + - # 12 + host_id: 0 + host_perms: 0 + - # 13 + host_id: 0 + host_perms: 0 + - # 14 + host_id: 0 + host_perms: 0 + - # 15 + host_id: 0 + host_perms: 0 + - # 16 + host_id: 0 + host_perms: 0 + - # 17 + host_id: 0 + host_perms: 0 + - # 18 + host_id: 0 + host_perms: 0 + - # 19 + host_id: 0 + host_perms: 0 + - # 20 + host_id: 0 + host_perms: 0 + - # 21 + host_id: 0 + host_perms: 0 + - # 22 + host_id: 0 + host_perms: 0 + - # 23 + host_id: 0 + host_perms: 0 + - # 24 + host_id: 0 + host_perms: 0 + - # 25 + host_id: 0 + host_perms: 0 + - # 26 + host_id: 0 + host_perms: 0 + - # 27 + host_id: 0 + host_perms: 0 + - # 28 + host_id: 0 + host_perms: 0 + - # 29 + host_id: 0 + host_perms: 0 + - # 30 + host_id: 0 + host_perms: 0 + - # 31 + host_id: 0 + host_perms: 0 + - # 32 + host_id: 0 + host_perms: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0 + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] |