diff options
| author | Tom Rini <[email protected]> | 2026-04-09 16:34:38 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-04-09 16:34:38 -0600 |
| commit | e2fa3e570f83ab0f9ce667ddaec9dc738bcf05b9 (patch) | |
| tree | 14de6d1a620c15e7b5bf349787edda955ee42745 /board/renesas/common/gen4-spl.c | |
| parent | 2a1bcefce835b827bbf88a9e112d646c5c4af9c1 (diff) | |
| parent | 4a95a2a9e13ab05e4fc309f92bc33998d80afe01 (diff) | |
Assorted fixes and tweaks, HUSH parser, preboot env variable, SMC
command enablement, s_init and 32bit/64bit code clean up, DBSC and APMU
remoteproc clean ups, UFS dev_phys_to_bus() remap support and SCIF R-Car
Gen5 support.
Diffstat (limited to 'board/renesas/common/gen4-spl.c')
| -rw-r--r-- | board/renesas/common/gen4-spl.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index ebfefab7253..e4c1190eac7 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -82,7 +82,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) #define RTGRP3_BIT BIT(19) #define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) -void s_init(void) +int mach_cpu_init(void) { /* Unlock CPG access */ writel(0x5A5AFFFF, CPGWPR); @@ -95,6 +95,8 @@ void s_init(void) writel(0x00ff00ff, APMU_BASE + 0x18); writel(0x00ff00ff, APMU_BASE + 0x1c); clrbits_le32(APMU_BASE + 0x68, BIT(29)); + + return 0; } void reset_cpu(void) |