diff options
| author | Richard Genoud <[email protected]> | 2026-01-23 12:44:58 +0100 |
|---|---|---|
| committer | Michael Trimarchi <[email protected]> | 2026-02-03 21:45:18 +0100 |
| commit | 7d1de98011519ebbb128f76f368724b62f3bc6eb (patch) | |
| tree | 90b6c130a31afcb72a62527a08281abab2f9235b /board/sunxi | |
| parent | f163da5e6d26904e5df509169ccc8cc91a0fb295 (diff) | |
mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller
Introduce H6/H616 NAND controller support for SPL
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
For SPL, most of the work was setting the clocks, adding the new
capability structure for H616 and supporting the new USER_DATA_LEN
registers.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <[email protected]>
Signed-off-by: Michael Trimarchi <[email protected]>
Diffstat (limited to 'board/sunxi')
| -rw-r--r-- | board/sunxi/board.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 85f20ffe085..954a8715075 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -309,12 +309,20 @@ static void nand_clock_setup(void) { void * const ccm = (void *)SUNXI_CCM_BASE; +#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_H6) + setbits_le32(ccm + CCU_H6_NAND_GATE_RESET, + (1 << GATE_SHIFT) | (1 << RESET_SHIFT)); + setbits_le32(ccm + CCU_H6_MBUS_GATE, (1 << MBUS_GATE_OFFSET_NAND)); + setbits_le32(ccm + CCU_NAND1_CLK_CFG, CCM_NAND_CTRL_ENABLE | + CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); +#else setbits_le32(ccm + CCU_AHB_GATE0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I setbits_le32(ccm + CCU_AHB_RESET0_CFG, (1 << AHB_GATE_OFFSET_NAND0)); #endif +#endif setbits_le32(ccm + CCU_NAND0_CLK_CFG, CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); } |