diff options
| author | Michal Simek <[email protected]> | 2026-06-23 14:53:34 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2026-07-08 08:55:51 +0200 |
| commit | 722cd61c35444835dbfbd0d2a25b2593eae3fe3f (patch) | |
| tree | 8bd1c7efaaa782bdf549f79d14354f59630bf445 /board/xilinx | |
| parent | d885e802ce8722a4dae77255b7aa16ccaf7976d8 (diff) | |
arm64: zynqmp: Move board_early_init_r clock setup to mach code
board_early_init_r() programmed the system timestamp counter directly
with readl()/writel() in board code. This is SoC register setup rather
than board policy, and similar code exists across the Xilinx SoCs.
Move it into zynqmp_timer_setup() in arch/arm/mach-zynqmp so the board
hook only keeps the EL3 guard and calls the helper. The asm/arch/clk.h
include (for zynqmp_get_system_timer_freq()) moves to cpu.c along with
the code.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/2d8f2419fab314b4ff8fd53b846e1dd6151586d3.1782219202.git.michal.simek@amd.com
Diffstat (limited to 'board/xilinx')
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index a12c039d8c9..5d13881f3ec 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -24,7 +24,6 @@ #include <malloc.h> #include <memalign.h> #include <wdt.h> -#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/arch/psu_init_gpl.h> @@ -214,26 +213,11 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - - if (!val) { - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); + zynqmp_timer_setup(); - /* Program freq register in System counter */ - writel(zynqmp_get_system_timer_freq(), - &iou_scntr_secure->base_frequency_id_register); - /* And enable system counter */ - writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, - &iou_scntr_secure->counter_control_register); - } return 0; } |