Merge branch 'next'

112 files changed, 13802 insertions, 1134 deletions

diff --git a/board/Marvell/octeontx/board-fdt.c b/board/Marvell/octeontx/board-fdt.c
index 6642b167e19..9d913b959e0 100644
--- a/board/Marvell/octeontx/board-fdt.c
+++ b/board/Marvell/octeontx/board-fdt.c
@@ -296,13 +296,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return 0;
 }
 
-/**
- * Return the FDT base address that was passed by ATF
- *
- * Return:	FDT base address received from ATF in x1 register
- */
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	return (void *)fdt_base_addr;
+	*fdtp = (void *)fdt_base_addr;
+
+	return 0;
 }
diff --git a/board/Marvell/octeontx2/board-fdt.c b/board/Marvell/octeontx2/board-fdt.c
index 04be9fb0a9a..e5a4db00bb7 100644
--- a/board/Marvell/octeontx2/board-fdt.c
+++ b/board/Marvell/octeontx2/board-fdt.c
@@ -210,13 +210,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return 0;
 }
 
-/**
- * Return the FDT base address that was passed by ATF
- *
- * Return:	FDT base address received from ATF in x1 register
- */
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	return (void *)fdt_base_addr;
+	*fdtp = (void *)fdt_base_addr;
+
+	return 0;
 }
diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c
index 974e9eb8200..01ba53cf68d 100644
--- a/board/Marvell/octeontx2/board.c
+++ b/board/Marvell/octeontx2/board.c
@@ -234,7 +234,8 @@ static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc,
 		return CMD_RET_USAGE;
 
 	addr = hextoul(argv[1], NULL);
-	fdt = board_fdt_blob_setup(&err);
+	fdt = (void *)gd->fdt_blob;
+	err = board_fdt_blob_setup(&fdt);
 	entry = (uboot_entry_t)addr;
 	flush_cache((ulong)addr, 1 << 20);	/* 1MiB should be enough */
 	dcache_disable();
diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c
index 5ae5baed6ba..1d9d4a929c2 100644
--- a/board/andestech/ae350/ae350.c
+++ b/board/andestech/ae350/ae350.c
@@ -79,21 +79,24 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 }
 
 #define ANDES_HW_DTB_ADDRESS	0xF2000000
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-
 	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
-		if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC)
-			return (void *)(ulong)gd->arch.firmware_fdt_addr;
+		if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) ==
+			FDT_MAGIC) {
+			*fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr;
+
+			return 0;
+		}
 	}
 
-	if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC)
-		return (void *)CONFIG_SYS_FDT_BASE;
-	return (void *)ANDES_HW_DTB_ADDRESS;
+	if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) {
+		*fdtp = (void *)CONFIG_SYS_FDT_BASE;
+
+		return 0;
+	}
 
-	*err = -EINVAL;
-	return NULL;
+	return -EINVAL;
 }
 
 #ifdef CONFIG_SPL_BOARD_INIT
diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c
index 1336d2eb163..75ba3c33d56 100644
--- a/board/armltd/total_compute/total_compute.c
+++ b/board/armltd/total_compute/total_compute.c
@@ -37,15 +37,13 @@ struct mm_region *mem_map = total_compute_mem_map;
  */
 unsigned long __section(".data") fw_dtb_pointer;
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) {
-		*err = -ENXIO;
-		return NULL;
-	}
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return -ENXIO;
 
-	return (void *)fw_dtb_pointer;
+	*fdtp = (void *)fw_dtb_pointer;
+	return 0;
 }
 
 int misc_init_r(void)
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 0119f54f0df..b5ede58757d 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -168,42 +168,37 @@ static bool is_valid_dtb(uintptr_t dtb_ptr)
 	return fdt_subnode_offset((void *)dtb_ptr, 0, "memory") >= 0;
 }
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 	phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
 
-	*err = 0;
-	if (fdt_rom_addr == ~0UL) {
-		*err = -ENXIO;
-		return NULL;
-	}
+	if (fdt_rom_addr == ~0UL)
+		return -ENXIO;
 
-	return (void *)fdt_rom_addr;
+	*fdtp = (void *)fdt_rom_addr;
+	return 0;
 #endif
 
 #ifdef VEXPRESS_FDT_ADDR
 	if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) {
-		*err = 0;
-		return (void *)VEXPRESS_FDT_ADDR;
+		*fdtp = (void *)VEXPRESS_FDT_ADDR;
+		return 0;
 	}
 #endif
 
 	if (is_valid_dtb(prior_stage_fdt_address[1])) {
-		*err = 0;
-		return (void *)prior_stage_fdt_address[1];
+		*fdtp = (void *)prior_stage_fdt_address[1];
+		return 0;
 	} else if (is_valid_dtb(prior_stage_fdt_address[0])) {
-		*err = 0;
-		return (void *)prior_stage_fdt_address[0];
+		*fdtp = (void *)prior_stage_fdt_address[0];
+		return 0;
 	}
 
-	if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) {
-		*err = 0;
-		return (void *)gd->fdt_blob;
-	}
+	if (fdt_magic(*fdtp) == FDT_MAGIC)
+		return 0;
 
-	*err = -ENXIO;
-	return NULL;
+	return -ENXIO;
 }
 #endif
 
diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile
index 9131a92efae..332b41f35c0 100644
--- a/board/beacon/beacon-rzg2m/Makefile
+++ b/board/beacon/beacon-rzg2m/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y	:= beacon-rzg2m.o ../../renesas/rcar-common/common.o
+obj-y	:= beacon-rzg2m.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index b85fd806cba..1adee9a461f 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -281,7 +281,7 @@ int board_eth_init(struct bd_info *bis)
 	setup_iomux_enet();
 
 #ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(base, -1);
+	bus = fec_get_miibus(NULL, base, -1);
 	if (!bus)
 		return -EINVAL;
 	/* scan phy 4,5,6,7 */
diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c
index bc05aecc446..e655f610c84 100644
--- a/board/broadcom/bcmstb/bcmstb.c
+++ b/board/broadcom/bcmstb/bcmstb.c
@@ -130,9 +130,10 @@ int board_late_init(void)
 	return 0;
 }
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
 	/* Stored the DTB address there during our init */
-	return (void *)prior_stage_fdt_address;
+	*fdtp = (void *)prior_stage_fdt_address;
+
+	return 0;
 }
diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c
index e0bdc7a5a88..d6b19530023 100644
--- a/board/coreboot/coreboot/sysinfo.c
+++ b/board/coreboot/coreboot/sysinfo.c
@@ -24,21 +24,21 @@ static int cb_get_str(struct udevice *dev, int id, size_t size, char *val)
 	const char *str = NULL;
 
 	switch (id) {
-	case SYSINFO_ID_BOARD_MODEL:
+	case SYSID_BOARD_MODEL:
 		if (priv->t1)
 			str = smbios_string(priv->system,
 					    priv->t1->product_name);
 		break;
-	case SYSINFO_ID_BOARD_MANUFACTURER:
+	case SYSID_BOARD_MANUFACTURER:
 		if (priv->t1)
 			str = smbios_string(priv->system,
 					    priv->t1->manufacturer);
 		break;
-	case SYSINFO_ID_PRIOR_STAGE_VERSION:
+	case SYSID_PRIOR_STAGE_VERSION:
 		if (priv->t0)
 			str = smbios_string(priv->bios, priv->t0->bios_ver);
 		break;
-	case SYSINFO_ID_PRIOR_STAGE_DATE:
+	case SYSID_PRIOR_STAGE_DATE:
 		if (priv->t0)
 			str = smbios_string(priv->bios,
 					    priv->t0->bios_release_date);
diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c
index 32c50b4f0f5..71010803f55 100644
--- a/board/dhelectronics/common/dh_common.c
+++ b/board/dhelectronics/common/dh_common.c
@@ -7,9 +7,27 @@
 #include <dm.h>
 #include <i2c_eeprom.h>
 #include <net.h>
+#include <u-boot/crc.h>
 
 #include "dh_common.h"
 
+static int on_dh_som_serial_number(const char *name, const char *value, enum env_op op,
+				   int flags)
+{
+	env_set("SN", value);
+	return 0;
+}
+
+U_BOOT_ENV_CALLBACK(dh_som_serial_number, on_dh_som_serial_number);
+
+static int on_SN(const char *name, const char *value, enum env_op op, int flags)
+{
+	env_set("dh_som_serial_number", value);
+	return 0;
+}
+
+U_BOOT_ENV_CALLBACK(SN, on_SN);
+
 bool dh_mac_is_in_env(const char *env)
 {
 	unsigned char enetaddr[6];
@@ -30,6 +48,149 @@ int dh_get_mac_is_enabled(const char *alias)
 	return 0;
 }
 
+int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias)
+{
+	struct eeprom_id_page *eip = (struct eeprom_id_page *)eeprom_buffer;
+	struct udevice *dev;
+	size_t payload_len;
+	int eeprom_size;
+	u16 crc16_calc;
+	u16 crc16_eip;
+	u8 crc8_calc;
+	ofnode node;
+	int ret;
+
+	node = ofnode_path(alias);
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
+	if (ret)
+		return ret;
+
+	eeprom_size = i2c_eeprom_size(dev);
+	if (eeprom_size < 0) {
+		printf("%s: Error getting EEPROM ID page size! ret = %d\n", __func__, ret);
+		return eeprom_size;
+	}
+
+	if (eeprom_size == 0 || eeprom_size > DH_EEPROM_ID_PAGE_MAX_SIZE) {
+		eeprom_size = DH_EEPROM_ID_PAGE_MAX_SIZE;
+		printf("Get invalid EEPROM ID page size %d bytes! Try to read %d bytes.\n",
+		       eeprom_size, DH_EEPROM_ID_PAGE_MAX_SIZE);
+	}
+
+	ret = i2c_eeprom_read(dev, 0x0, eeprom_buffer, eeprom_size);
+	if (ret) {
+		printf("%s: Error reading EEPROM ID page! ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* Validate header ID */
+	if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') {
+		printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n",
+		       __func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.',
+		       isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.',
+		       isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.',
+		       eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]);
+		return -EINVAL;
+	}
+
+	/* Validate header checksum */
+	crc8_calc = crc8(0xff, eeprom_buffer, offsetof(struct eeprom_id_page, hdr.crc8_hdr));
+	if (eip->hdr.crc8_hdr != crc8_calc) {
+		printf("%s: Error validating header checksum! (got 0x%02x != calc 0x%02x)\n",
+		       __func__, eip->hdr.crc8_hdr, crc8_calc);
+		return -EINVAL;
+	}
+
+	/*
+	 * Validate header version
+	 * The payload is defined by the version specified in the header.
+	 * Currently only version 0x10 is defined, so take the length of
+	 * the only defined payload as the payload length.
+	 */
+	if (eip->hdr.version != DH_EEPROM_ID_PAGE_V1_0) {
+		printf("%s: Error validating version! (0x%02X is not supported)\n",
+		       __func__, eip->hdr.version);
+		return -EINVAL;
+	}
+	payload_len = sizeof(eip->pl);
+
+	/* Validate payload checksum */
+	crc16_eip = (eip->hdr.crc16_pl[1] << 8) | eip->hdr.crc16_pl[0];
+	crc16_calc = crc16(0xffff, eeprom_buffer + sizeof(eip->hdr), payload_len);
+	if (crc16_eip != crc16_calc) {
+		printf("%s: Error validating data checksum! (got 0x%02x != calc 0x%02x)\n",
+		       __func__, crc16_eip, crc16_calc);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len,
+				    struct eeprom_id_page *eip)
+{
+	const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ?
+			     DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR;
+	const u8 soc_coded = eip->pl.item_prefix & 0xf;
+	char soc_chr;
+
+	if (!eip)
+		return -EINVAL;
+
+	/* Copy requested data */
+	switch (request) {
+	case DH_MAC0:
+		if (!is_valid_ethaddr(eip->pl.mac0))
+			return -EINVAL;
+
+		if (data_len >= sizeof(eip->pl.mac0))
+			memcpy(data, eip->pl.mac0, sizeof(eip->pl.mac0));
+		else
+			return -EINVAL;
+		break;
+	case DH_MAC1:
+		if (!is_valid_ethaddr(eip->pl.mac1))
+			return -EINVAL;
+
+		if (data_len >= sizeof(eip->pl.mac1))
+			memcpy(data, eip->pl.mac1, sizeof(eip->pl.mac1));
+		else
+			return -EINVAL;
+		break;
+	case DH_ITEM_NUMBER:
+		if (data_len < 8) /* String length must be 7 characters + string termination */
+			return -EINVAL;
+
+		if (soc_coded == DH_ITEM_PREFIX_NXP)
+			soc_chr = DH_ITEM_PREFIX_NXP_CHR;
+		else if (soc_coded == DH_ITEM_PREFIX_ST)
+			soc_chr = DH_ITEM_PREFIX_ST_CHR;
+		else
+			return -EINVAL;
+
+		snprintf(data, data_len, "%c%c%05d", fin_chr, soc_chr,
+			 (eip->pl.item_num[0] << 16) | (eip->pl.item_num[1] << 8) |
+			 eip->pl.item_num[2]);
+		break;
+	case DH_SERIAL_NUMBER:
+		/*
+		 * data_len must be greater than the size of eip->pl.serial,
+		 * because there is a string termination needed.
+		 */
+		if (data_len <= sizeof(eip->pl.serial))
+			return -EINVAL;
+
+		data[sizeof(eip->pl.serial)] = 0;
+		memcpy(data, eip->pl.serial, sizeof(eip->pl.serial));
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
 {
 	struct udevice *dev;
@@ -62,7 +223,7 @@ int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
 	return 0;
 }
 
-__weak int dh_setup_mac_address(void)
+__weak int dh_setup_mac_address(struct eeprom_id_page *eip)
 {
 	unsigned char enetaddr[6];
 
@@ -72,6 +233,9 @@ __weak int dh_setup_mac_address(void)
 	if (dh_get_mac_is_enabled("ethernet0"))
 		return 0;
 
+	if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
+		return eth_env_set_enetaddr("ethaddr", enetaddr);
+
 	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
 		return eth_env_set_enetaddr("ethaddr", enetaddr);
 
diff --git a/board/dhelectronics/common/dh_common.h b/board/dhelectronics/common/dh_common.h
index a2de5b1553e..c4693c60618 100644
--- a/board/dhelectronics/common/dh_common.h
+++ b/board/dhelectronics/common/dh_common.h
@@ -3,6 +3,52 @@
  * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <[email protected]>
  */
 
+#define DH_EEPROM_ID_PAGE_MAX_SIZE	64
+
+enum eip_request_values {
+	DH_MAC0,
+	DH_MAC1,
+	DH_ITEM_NUMBER,
+	DH_SERIAL_NUMBER,
+};
+
+/* DH item: Vendor coding */
+#define DH_ITEM_PREFIX_NXP	0x01
+#define DH_ITEM_PREFIX_NXP_CHR	'I'
+#define DH_ITEM_PREFIX_ST	0x02
+#define DH_ITEM_PREFIX_ST_CHR	'S'
+
+/*
+ * DH item: Finished state coding
+ * Bit = 0 means half finished
+ *         Prefix is 'H'
+ * Bit = 1 means finished with a customer image flashed
+ *         Prefix is 'F'
+ */
+#define DH_ITEM_PREFIX_FIN_BIT		BIT(7)
+#define DH_ITEM_PREFIX_FIN_HALF_CHR	'H'
+#define DH_ITEM_PREFIX_FIN_FLASHED_CHR	'F'
+
+struct eeprom_id_page {
+	/* Header */
+	struct {
+		u8	id[3];		/* Identifier 'D', 'H', 'E' - 'D' is at index 0 */
+		u8	version;	/* 0x10 -- Version 1.0 */
+		u8	crc16_pl[2];	/* Checksum payload, [1] is MSbyte */
+		u8	crc8_hdr;	/* Checksum header */
+	} hdr;
+	/* Payload */
+	struct {
+		u8	mac0[6];
+		u8	mac1[6];
+		u8	item_prefix;	/* H/F is coded in MSbits, Vendor coding starts at LSbits */
+		u8	item_num[3];	/* [2] is MSbyte */
+		u8	serial[9];	/* [8] is MSbyte */
+	} pl;
+};
+
+#define DH_EEPROM_ID_PAGE_V1_0		0x10
+
 /*
  * dh_mac_is_in_env - Check if MAC address is already set
  *
@@ -29,8 +75,39 @@ int dh_get_mac_is_enabled(const char *alias);
 int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
 
 /*
+ * dh_read_eeprom_id_page() - Read EEPROM ID page content into given buffer
+ * @eeprom_buffer:	Buffer for EEPROM ID page content
+ * @alias:		Alias for EEPROM ID page device tree node
+ *
+ * Read the content of the EEPROM ID page into the given buffer (parameter
+ * eeprom_buffer). The EEPROM ID page device is selected via alias device
+ * tree name (parameter alias). The data of the EEPROM ID page is verified.
+ * An error is returned for reading failures and invalid data.
+ *
+ * Return: 0 if OK, other value on error
+ */
+int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias);
+
+/*
+ * dh_get_value_from_eeprom_buffer() - Get value from EEPROM buffer
+ * @eip_request_values:	Requested value as enum
+ * @data:		Buffer where value is to be stored
+ * @data_len:		Length of the value buffer
+ * @eip:		Pointer to EEPROM ID page struct from which the data is parsed
+ *
+ * Gets the value specified by the parameter eip_request_values from the EEPROM
+ * data struct (parameter eip). The data is written to the specified data
+ * buffer (parameter data). If the length of the data (parameter data_len) is
+ * not sufficient to copy the data into the buffer, an error is returned.
+ *
+ * Return: 0 if OK, other value on error
+ */
+int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len,
+				    struct eeprom_id_page *eip);
+
+/*
  * dh_setup_mac_address - Try to get MAC address from various locations and write it to env
  *
  * Return: 0 if OK, other value on error
  */
-int dh_setup_mac_address(void);
+int dh_setup_mac_address(struct eeprom_id_page *eip);
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index f2b14bf701a..234824b38c2 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -84,7 +84,7 @@ int board_usb_phy_mode(int port)
 }
 #endif
 
-int dh_setup_mac_address(void)
+int dh_setup_mac_address(struct eeprom_id_page *eip)
 {
 	unsigned char enetaddr[6];
 
@@ -171,7 +171,7 @@ int board_late_init(void)
 	u32 hw_code;
 	char buf[16];
 
-	dh_setup_mac_address();
+	dh_setup_mac_address(NULL);
 
 	hw_code = board_get_hwcode();
 
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 78aae412350..4af3cbe9fe2 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -40,7 +40,7 @@ int board_phys_sdram_size(phys_size_t *size)
 	return 0;
 }
 
-static int dh_imx8_setup_ethaddr(void)
+static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip)
 {
 	unsigned char enetaddr[6];
 
@@ -53,6 +53,9 @@ static int dh_imx8_setup_ethaddr(void)
 	if (!dh_imx_get_mac_from_fuse(enetaddr))
 		goto out;
 
+	if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
+		goto out;
+
 	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
 		goto out;
 
@@ -62,7 +65,7 @@ out:
 	return eth_env_set_enetaddr("ethaddr", enetaddr);
 }
 
-static int dh_imx8_setup_eth1addr(void)
+static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip)
 {
 	unsigned char enetaddr[6];
 
@@ -75,6 +78,9 @@ static int dh_imx8_setup_eth1addr(void)
 	if (!dh_imx_get_mac_from_fuse(enetaddr))
 		goto increment_out;
 
+	if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip))
+		goto out;
+
 	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
 		goto out;
 
@@ -95,21 +101,58 @@ out:
 	return eth_env_set_enetaddr("eth1addr", enetaddr);
 }
 
-int dh_setup_mac_address(void)
+int dh_setup_mac_address(struct eeprom_id_page *eip)
 {
 	int ret;
 
-	ret = dh_imx8_setup_ethaddr();
+	ret = dh_imx8_setup_ethaddr(eip);
 	if (ret)
 		printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
 
-	ret = dh_imx8_setup_eth1addr();
+	ret = dh_imx8_setup_eth1addr(eip);
 	if (ret)
 		printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
 
 	return ret;
 }
 
+void dh_add_item_number_and_serial_to_env(struct eeprom_id_page *eip)
+{
+	char *item_number_env;
+	char item_number[8];	/* String with 7 characters + string termination */
+	char *serial_env;
+	char serial[10];	/* String with 9 characters + string termination */
+	int ret;
+
+	ret = dh_get_value_from_eeprom_buffer(DH_ITEM_NUMBER, item_number, sizeof(item_number),
+					      eip);
+	if (ret) {
+		printf("%s: Unable to get DHSOM item number from EEPROM ID page! ret = %d\n",
+		       __func__, ret);
+	} else {
+		item_number_env = env_get("dh_som_item_number");
+		if (!item_number_env)
+			env_set("dh_som_item_number", item_number);
+		else if (strcmp(item_number_env, item_number))
+			printf("Warning: Environment dh_som_item_number differs from EEPROM ID page value (%s != %s)\n",
+			       item_number_env, item_number);
+	}
+
+	ret = dh_get_value_from_eeprom_buffer(DH_SERIAL_NUMBER, serial, sizeof(serial),
+					      eip);
+	if (ret) {
+		printf("%s: Unable to get DHSOM serial number from EEPROM ID page! ret = %d\n",
+		       __func__, ret);
+	} else {
+		serial_env = env_get("dh_som_serial_number");
+		if (!serial_env)
+			env_set("dh_som_serial_number", serial);
+		else if (strcmp(serial_env, serial))
+			printf("Warning: Environment dh_som_serial_number differs from EEPROM ID page value (%s != %s)\n",
+			       serial_env, serial);
+	}
+}
+
 int board_init(void)
 {
 	return 0;
@@ -117,7 +160,27 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	dh_setup_mac_address();
+	u8 eeprom_buffer[DH_EEPROM_ID_PAGE_MAX_SIZE] = { 0 };
+	struct eeprom_id_page *eip = (struct eeprom_id_page *)eeprom_buffer;
+	int ret;
+
+	ret = dh_read_eeprom_id_page(eeprom_buffer, "eeprom0wl");
+	if (ret) {
+		/*
+		 * The EEPROM ID page is available on SoM rev. 200 and greater.
+		 * For SoM rev. 100 the return value will be -ENODEV. Suppress
+		 * the error message for that, because the absence cannot be
+		 * treated as an error.
+		 */
+		if (ret != -ENODEV)
+			printf("%s: Cannot read valid data from EEPROM ID page! ret = %d\n",
+			       __func__, ret);
+		dh_setup_mac_address(NULL);
+	} else {
+		dh_setup_mac_address(eip);
+		dh_add_item_number_and_serial_to_env(eip);
+	}
+
 	return 0;
 }
 
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index e0e18b4dfea..31f5a775137 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -149,11 +149,12 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
 	/* QEMU loads a generated DTB for us at the start of RAM. */
-	return (void *)CFG_SYS_SDRAM_BASE;
+	*fdtp = (void *)CFG_SYS_SDRAM_BASE;
+
+	return 0;
 }
 
 void enable_caches(void)
diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c
index 58e5d5eb942..40d295dbf06 100644
--- a/board/emulation/qemu-ppce500/qemu-ppce500.c
+++ b/board/emulation/qemu-ppce500/qemu-ppce500.c
@@ -334,15 +334,11 @@ u32 cpu_mask(void)
 	return (1 << cpu_numcores()) - 1;
 }
 
-/**
- * Return the virtual address of FDT that was passed by QEMU
- *
- * Return: virtual address of FDT received from QEMU in r3 register
- */
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	return get_fdt_virt();
+	*fdtp = get_fdt_virt();
+
+	return 0;
 }
 
 /* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index e5193e31e37..a90222ea6a4 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -64,9 +64,10 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
 	/* Stored the DTB address there during our init */
-	return (void *)(ulong)gd->arch.firmware_fdt_addr;
+	*fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr;
+
+	return 0;
 }
diff --git a/board/freescale/imx91_evk/Kconfig b/board/freescale/imx91_evk/Kconfig
new file mode 100644
index 00000000000..caaa82b4af8
--- /dev/null
+++ b/board/freescale/imx91_evk/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_IMX91_11X11_EVK
+
+config SYS_BOARD
+	default "imx91_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx91_evk"
+
+config IMX91_EVK_LPDDR4
+	bool "Using LPDDR4 Timing and PMIC voltage"
+	default y
+	select IMX9_LPDDR4X
+	help
+	  Select the LPDDR4 timing and 1.1V VDDQ
+
+endif
diff --git a/board/freescale/imx91_evk/MAINTAINERS b/board/freescale/imx91_evk/MAINTAINERS
new file mode 100644
index 00000000000..f7d39bfb0a3
--- /dev/null
+++ b/board/freescale/imx91_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX91 11x11 EVK BOARD
+M:	Peng Fan <[email protected]>
+S:	Maintained
+F:	board/freescale/imx91_evk/
+F:	include/configs/imx91_evk.h
+F:	configs/imx91_11x11_evk_defconfig
+F:	configs/imx91_11x11_evk_inline_ecc_defconfig
diff --git a/board/freescale/imx91_evk/Makefile b/board/freescale/imx91_evk/Makefile
new file mode 100644
index 00000000000..a96228af959
--- /dev/null
+++ b/board/freescale/imx91_evk/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx91_evk.o
+
+ifdef CONFIG_XPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_IMX9_DRAM_INLINE_ECC
+obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts_ecc.o lpddr4_timing_1600mts_ecc.o
+else
+obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts.o lpddr4_timing_1600mts.o
+endif
+endif
diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c
new file mode 100644
index 00000000000..83bfca2f22d
--- /dev/null
+++ b/board/freescale/imx91_evk/imx91_evk.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "11X11_EVK");
+	env_set("board_rev", "iMX93");
+#endif
+	return 0;
+}
diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env
new file mode 100644
index 00000000000..92486c6f74d
--- /dev/null
+++ b/board/freescale/imx91_evk/imx91_evk.env
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+boot_targets=mmc0 mmc1
+boot_fit=no
+bootm_size=0x10000000
+cntr_addr=0x98000000
+cntr_file=os_cntr_signed.bin
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
+prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r}
+mmcboot=
+	echo Booting from mmc ...;
+	run mmcargs;
+	if test ${sec_boot} = yes; then
+		if run auth_os; then
+			run boot_os;
+		else
+			echo ERR: failed to authenticate;
+		fi;
+	else
+		if run loadfdt; then
+			run boot_os;
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	fi;
+netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs
+	ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+	echo Booting from net ...;
+	run netargs;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	if test ${sec_boot} = yes; then
+		${get_cmd} ${cntr_addr} ${cntr_file};
+		if run auth_os; then
+			run boot_os;
+		else
+			echo ERR: failed to authenticate;
+		fi;
+	else
+		${get_cmd} ${loadaddr} ${image};
+		if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+			run boot_os;
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	fi;
diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c
new file mode 100644
index 00000000000..45e19daa028
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x4e300110, 0x44100001},
+	{0x4e300000, 0x8000ff},
+	{0x4e300008, 0x0},
+	{0x4e300080, 0x80000512},
+	{0x4e300084, 0x0},
+	{0x4e300114, 0x1002},
+	{0x4e300260, 0x80},
+	{0x4e300f04, 0x80},
+	{0x4e300800, 0x43b30002},
+	{0x4e300804, 0x1f1f1f1f},
+	{0x4e301000, 0x0},
+	{0x4e301240, 0x0},
+	{0x4e301244, 0x0},
+	{0x4e301248, 0x0},
+	{0x4e30124c, 0x0},
+	{0x4e301250, 0x0},
+	{0x4e301254, 0x0},
+	{0x4e301258, 0x0},
+	{0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+	{
+		{
+			{0x4e300100, 0x02121100},
+			{0x4e300104, 0xF866000C},
+			{0x4e300108, 0xF2FA8088},
+			{0x4e30010C, 0x0061E1A0},
+			{0x4e300124, 0x0C340000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30700000},
+			{0x4e300170, 0x8A0A0508},
+			{0x4e300250, 0x00000011},
+			{0x4e300254, 0x00900090},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+			{0x4e300300, 0x0F220F09},
+			{0x4e300304, 0x00901008},
+			{0x4e300308, 0x063C061A},
+		},
+		{
+			{0x01, 0xA4},
+			{0x02, 0x52},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x00091000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x81820A48},
+			{0x4e30010C, 0x00310110},
+			{0x4e300124, 0x061A0000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30100000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000009},
+			{0x4e300254, 0x00440044},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x00061000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x6E62FA48},
+			{0x4e30010C, 0x0031010D},
+			{0x4e300124, 0x04C50000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30000000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000007},
+			{0x4e300254, 0x00340034},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		1,
+	},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x4},
+	{0x100a1, 0x5},
+	{0x100a2, 0x6},
+	{0x100a3, 0x7},
+	{0x100a4, 0x0},
+	{0x100a5, 0x1},
+	{0x100a6, 0x2},
+	{0x100a7, 0x3},
+	{0x110a0, 0x3},
+	{0x110a1, 0x2},
+	{0x110a2, 0x0},
+	{0x110a3, 0x1},
+	{0x110a4, 0x7},
+	{0x110a5, 0x6},
+	{0x110a6, 0x4},
+	{0x110a7, 0x5},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x200c5, 0xb},
+	{0x1200c5, 0x3},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x1},
+	{0x12002e, 0x1},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x2007d, 0x212},
+	{0x2007c, 0x61},
+	{0x120024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x12007d, 0x212},
+	{0x12007c, 0x61},
+	{0x220024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x22007d, 0x212},
+	{0x22007c, 0x61},
+	{0x20056, 0x3},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
+	{0x1004d, 0x600},
+	{0x1014d, 0x600},
+	{0x1104d, 0x600},
+	{0x1114d, 0x600},
+	{0x11004d, 0x600},
+	{0x11014d, 0x600},
+	{0x11104d, 0x600},
+	{0x11114d, 0x600},
+	{0x21004d, 0x600},
+	{0x21014d, 0x600},
+	{0x21104d, 0x600},
+	{0x21114d, 0x600},
+	{0x10049, 0xe3f},
+	{0x10149, 0xe3f},
+	{0x11049, 0xe3f},
+	{0x11149, 0xe3f},
+	{0x110049, 0xe3f},
+	{0x110149, 0xe3f},
+	{0x111049, 0xe3f},
+	{0x111149, 0xe3f},
+	{0x210049, 0xe3f},
+	{0x210149, 0xe3f},
+	{0x211049, 0xe3f},
+	{0x211149, 0xe3f},
+	{0x43, 0x7f},
+	{0x1043, 0x7f},
+	{0x2043, 0x7f},
+	{0x20018, 0x1},
+	{0x20075, 0x4},
+	{0x20050, 0x11},
+	{0x2009b, 0x2},
+	{0x20008, 0x190},
+	{0x120008, 0xc8},
+	{0x220008, 0x9c},
+	{0x20088, 0x9},
+	{0x200b2, 0x10c},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x1200b2, 0x10c},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x2200b2, 0x10c},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x200fa, 0x2},
+	{0x1200fa, 0x2},
+	{0x2200fa, 0x2},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x600},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5655},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x1004a, 0x500},
+	{0x1104a, 0x500},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0x20021, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x41},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x1005f, 0x0},
+	{0x1015f, 0x0},
+	{0x1105f, 0x0},
+	{0x1115f, 0x0},
+	{0x11005f, 0x0},
+	{0x11015f, 0x0},
+	{0x11105f, 0x0},
+	{0x11115f, 0x0},
+	{0x21005f, 0x0},
+	{0x21015f, 0x0},
+	{0x21105f, 0x0},
+	{0x21115f, 0x0},
+	{0x55, 0x0},
+	{0x1055, 0x0},
+	{0x2055, 0x0},
+	{0x200c5, 0x0},
+	{0x1200c5, 0x0},
+	{0x2200c5, 0x0},
+	{0x2002e, 0x0},
+	{0x12002e, 0x0},
+	{0x22002e, 0x0},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x0},
+	{0x2003a, 0x0},
+	{0x2007d, 0x0},
+	{0x2007c, 0x0},
+	{0x120024, 0x0},
+	{0x12007d, 0x0},
+	{0x12007c, 0x0},
+	{0x220024, 0x0},
+	{0x22007d, 0x0},
+	{0x22007c, 0x0},
+	{0x20056, 0x0},
+	{0x120056, 0x0},
+	{0x220056, 0x0},
+	{0x1004d, 0x0},
+	{0x1014d, 0x0},
+	{0x1104d, 0x0},
+	{0x1114d, 0x0},
+	{0x11004d, 0x0},
+	{0x11014d, 0x0},
+	{0x11104d, 0x0},
+	{0x11114d, 0x0},
+	{0x21004d, 0x0},
+	{0x21014d, 0x0},
+	{0x21104d, 0x0},
+	{0x21114d, 0x0},
+	{0x10049, 0x0},
+	{0x10149, 0x0},
+	{0x11049, 0x0},
+	{0x11149, 0x0},
+	{0x110049, 0x0},
+	{0x110149, 0x0},
+	{0x111049, 0x0},
+	{0x111149, 0x0},
+	{0x210049, 0x0},
+	{0x210149, 0x0},
+	{0x211049, 0x0},
+	{0x211149, 0x0},
+	{0x43, 0x0},
+	{0x1043, 0x0},
+	{0x2043, 0x0},
+	{0x20018, 0x0},
+	{0x20075, 0x0},
+	{0x20050, 0x0},
+	{0x2009b, 0x0},
+	{0x20008, 0x0},
+	{0x120008, 0x0},
+	{0x220008, 0x0},
+	{0x20088, 0x0},
+	{0x200b2, 0x0},
+	{0x10043, 0x0},
+	{0x10143, 0x0},
+	{0x11043, 0x0},
+	{0x11143, 0x0},
+	{0x1200b2, 0x0},
+	{0x110043, 0x0},
+	{0x110143, 0x0},
+	{0x111043, 0x0},
+	{0x111143, 0x0},
+	{0x2200b2, 0x0},
+	{0x210043, 0x0},
+	{0x210143, 0x0},
+	{0x211043, 0x0},
+	{0x211143, 0x0},
+	{0x200fa, 0x0},
+	{0x1200fa, 0x0},
+	{0x2200fa, 0x0},
+	{0x20019, 0x0},
+	{0x120019, 0x0},
+	{0x220019, 0x0},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x0},
+	{0x200f3, 0x0},
+	{0x200f4, 0x0},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0x0},
+	{0x1004a, 0x0},
+	{0x1104a, 0x0},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0xd0000, 0x0},
+	{0x90000, 0x0},
+	{0x90001, 0x0},
+	{0x90002, 0x0},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x0},
+	{0x90029, 0x0},
+	{0x9002a, 0x0},
+	{0x9002b, 0x0},
+	{0x9002c, 0x0},
+	{0x9002d, 0x0},
+	{0x9002e, 0x0},
+	{0x9002f, 0x0},
+	{0x90030, 0x0},
+	{0x90031, 0x0},
+	{0x90032, 0x0},
+	{0x90033, 0x0},
+	{0x90034, 0x0},
+	{0x90035, 0x0},
+	{0x90036, 0x0},
+	{0x90037, 0x0},
+	{0x90038, 0x0},
+	{0x90039, 0x0},
+	{0x9003a, 0x0},
+	{0x9003b, 0x0},
+	{0x9003c, 0x0},
+	{0x9003d, 0x0},
+	{0x9003e, 0x0},
+	{0x9003f, 0x0},
+	{0x90040, 0x0},
+	{0x90041, 0x0},
+	{0x90042, 0x0},
+	{0x90043, 0x0},
+	{0x90044, 0x0},
+	{0x90045, 0x0},
+	{0x90046, 0x0},
+	{0x90047, 0x0},
+	{0x90048, 0x0},
+	{0x90049, 0x0},
+	{0x9004a, 0x0},
+	{0x9004b, 0x0},
+	{0x9004c, 0x0},
+	{0x9004d, 0x0},
+	{0x9004e, 0x0},
+	{0x9004f, 0x0},
+	{0x90050, 0x0},
+	{0x90051, 0x0},
+	{0x90052, 0x0},
+	{0x90053, 0x0},
+	{0x90054, 0x0},
+	{0x90055, 0x0},
+	{0x90056, 0x0},
+	{0x90057, 0x0},
+	{0x90058, 0x0},
+	{0x90059, 0x0},
+	{0x9005a, 0x0},
+	{0x9005b, 0x0},
+	{0x9005c, 0x0},
+	{0x9005d, 0x0},
+	{0x9005e, 0x0},
+	{0x9005f, 0x0},
+	{0x90060, 0x0},
+	{0x90061, 0x0},
+	{0x90062, 0x0},
+	{0x90063, 0x0},
+	{0x90064, 0x0},
+	{0x90065, 0x0},
+	{0x90066, 0x0},
+	{0x90067, 0x0},
+	{0x90068, 0x0},
+	{0x90069, 0x0},
+	{0x9006a, 0x0},
+	{0x9006b, 0x0},
+	{0x9006c, 0x0},
+	{0x9006d, 0x0},
+	{0x9006e, 0x0},
+	{0x9006f, 0x0},
+	{0x90070, 0x0},
+	{0x90071, 0x0},
+	{0x90072, 0x0},
+	{0x90073, 0x0},
+	{0x90074, 0x0},
+	{0x90075, 0x0},
+	{0x90076, 0x0},
+	{0x90077, 0x0},
+	{0x90078, 0x0},
+	{0x90079, 0x0},
+	{0x9007a, 0x0},
+	{0x9007b, 0x0},
+	{0x9007c, 0x0},
+	{0x9007d, 0x0},
+	{0x9007e, 0x0},
+	{0x9007f, 0x0},
+	{0x90080, 0x0},
+	{0x90081, 0x0},
+	{0x90082, 0x0},
+	{0x90083, 0x0},
+	{0x90084, 0x0},
+	{0x90085, 0x0},
+	{0x90086, 0x0},
+	{0x90087, 0x0},
+	{0x90088, 0x0},
+	{0x90089, 0x0},
+	{0x9008a, 0x0},
+	{0x9008b, 0x0},
+	{0x9008c, 0x0},
+	{0x9008d, 0x0},
+	{0x9008e, 0x0},
+	{0x9008f, 0x0},
+	{0x90090, 0x0},
+	{0x90091, 0x0},
+	{0x90092, 0x0},
+	{0x90093, 0x0},
+	{0x90094, 0x0},
+	{0x90095, 0x0},
+	{0x90096, 0x0},
+	{0x90097, 0x0},
+	{0x90098, 0x0},
+	{0x90099, 0x0},
+	{0x9009a, 0x0},
+	{0x9009b, 0x0},
+	{0x9009c, 0x0},
+	{0x9009d, 0x0},
+	{0x9009e, 0x0},
+	{0x9009f, 0x0},
+	{0x900a0, 0x0},
+	{0x900a1, 0x0},
+	{0x900a2, 0x0},
+	{0x900a3, 0x0},
+	{0x900a4, 0x0},
+	{0x900a5, 0x0},
+	{0x900a6, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x0},
+	{0x900a9, 0x0},
+	{0x40000, 0x0},
+	{0x40020, 0x0},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x0},
+	{0x40021, 0x0},
+	{0x40041, 0x0},
+	{0x40061, 0x0},
+	{0x40002, 0x0},
+	{0x40022, 0x0},
+	{0x40042, 0x0},
+	{0x40062, 0x0},
+	{0x40003, 0x0},
+	{0x40023, 0x0},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x0},
+	{0x40024, 0x0},
+	{0x40044, 0x0},
+	{0x40064, 0x0},
+	{0x40005, 0x0},
+	{0x40025, 0x0},
+	{0x40045, 0x0},
+	{0x40065, 0x0},
+	{0x40006, 0x0},
+	{0x40026, 0x0},
+	{0x40046, 0x0},
+	{0x40066, 0x0},
+	{0x40007, 0x0},
+	{0x40027, 0x0},
+	{0x40047, 0x0},
+	{0x40067, 0x0},
+	{0x40008, 0x0},
+	{0x40028, 0x0},
+	{0x40048, 0x0},
+	{0x40068, 0x0},
+	{0x40009, 0x0},
+	{0x40029, 0x0},
+	{0x40049, 0x0},
+	{0x40069, 0x0},
+	{0x4000a, 0x0},
+	{0x4002a, 0x0},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x0},
+	{0x4002b, 0x0},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x0},
+	{0x4002c, 0x0},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0x0},
+	{0x4002d, 0x0},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x0},
+	{0x4002e, 0x0},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x0},
+	{0x4002f, 0x0},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x0},
+	{0x40030, 0x0},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x0},
+	{0x40031, 0x0},
+	{0x40051, 0x0},
+	{0x40071, 0x0},
+	{0x40012, 0x0},
+	{0x40032, 0x0},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x0},
+	{0x40033, 0x0},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x0},
+	{0x40034, 0x0},
+	{0x40054, 0x0},
+	{0x40074, 0x0},
+	{0x40015, 0x0},
+	{0x40035, 0x0},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x0},
+	{0x40036, 0x0},
+	{0x40056, 0x0},
+	{0x40076, 0x0},
+	{0x40017, 0x0},
+	{0x40037, 0x0},
+	{0x40057, 0x0},
+	{0x40077, 0x0},
+	{0x40018, 0x0},
+	{0x40038, 0x0},
+	{0x40058, 0x0},
+	{0x40078, 0x0},
+	{0x40019, 0x0},
+	{0x40039, 0x0},
+	{0x40059, 0x0},
+	{0x40079, 0x0},
+	{0x4001a, 0x0},
+	{0x4003a, 0x0},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x0},
+	{0x900ac, 0x0},
+	{0x900ad, 0x0},
+	{0x900ae, 0x0},
+	{0x900af, 0x0},
+	{0x900b0, 0x0},
+	{0x900b1, 0x0},
+	{0x900b2, 0x0},
+	{0x900b3, 0x0},
+	{0x900b4, 0x0},
+	{0x900b5, 0x0},
+	{0x900b6, 0x0},
+	{0x900b7, 0x0},
+	{0x900b8, 0x0},
+	{0x900b9, 0x0},
+	{0x900ba, 0x0},
+	{0x900bb, 0x0},
+	{0x900bc, 0x0},
+	{0x900bd, 0x0},
+	{0x900be, 0x0},
+	{0x900bf, 0x0},
+	{0x900c0, 0x0},
+	{0x900c1, 0x0},
+	{0x900c2, 0x0},
+	{0x900c3, 0x0},
+	{0x900c4, 0x0},
+	{0x900c5, 0x0},
+	{0x900c6, 0x0},
+	{0x900c7, 0x0},
+	{0x900c8, 0x0},
+	{0x900c9, 0x0},
+	{0x900ca, 0x0},
+	{0x900cb, 0x0},
+	{0x900cc, 0x0},
+	{0x900cd, 0x0},
+	{0x900ce, 0x0},
+	{0x900cf, 0x0},
+	{0x900d0, 0x0},
+	{0x900d1, 0x0},
+	{0x900d2, 0x0},
+	{0x900d3, 0x0},
+	{0x900d4, 0x0},
+	{0x900d5, 0x0},
+	{0x900d6, 0x0},
+	{0x900d7, 0x0},
+	{0x900d8, 0x0},
+	{0x900d9, 0x0},
+	{0x900da, 0x0},
+	{0x900db, 0x0},
+	{0x900dc, 0x0},
+	{0x900dd, 0x0},
+	{0x900de, 0x0},
+	{0x900df, 0x0},
+	{0x900e0, 0x0},
+	{0x900e1, 0x0},
+	{0x900e2, 0x0},
+	{0x900e3, 0x0},
+	{0x900e4, 0x0},
+	{0x900e5, 0x0},
+	{0x900e6, 0x0},
+	{0x900e7, 0x0},
+	{0x900e8, 0x0},
+	{0x900e9, 0x0},
+	{0x900ea, 0x0},
+	{0x900eb, 0x0},
+	{0x900ec, 0x0},
+	{0x900ed, 0x0},
+	{0x900ee, 0x0},
+	{0x900ef, 0x0},
+	{0x900f0, 0x0},
+	{0x900f1, 0x0},
+	{0x900f2, 0x0},
+	{0x900f3, 0x0},
+	{0x900f4, 0x0},
+	{0x900f5, 0x0},
+	{0x900f6, 0x0},
+	{0x900f7, 0x0},
+	{0x900f8, 0x0},
+	{0x900f9, 0x0},
+	{0x900fa, 0x0},
+	{0x900fb, 0x0},
+	{0x900fc, 0x0},
+	{0x900fd, 0x0},
+	{0x900fe, 0x0},
+	{0x900ff, 0x0},
+	{0x90100, 0x0},
+	{0x90101, 0x0},
+	{0x90102, 0x0},
+	{0x90103, 0x0},
+	{0x90104, 0x0},
+	{0x90105, 0x0},
+	{0x90106, 0x0},
+	{0x90107, 0x0},
+	{0x90108, 0x0},
+	{0x90109, 0x0},
+	{0x9010a, 0x0},
+	{0x9010b, 0x0},
+	{0x9010c, 0x0},
+	{0x9010d, 0x0},
+	{0x9010e, 0x0},
+	{0x9010f, 0x0},
+	{0x90110, 0x0},
+	{0x90111, 0x0},
+	{0x90112, 0x0},
+	{0x90113, 0x0},
+	{0x90114, 0x0},
+	{0x90115, 0x0},
+	{0x90116, 0x0},
+	{0x90117, 0x0},
+	{0x90118, 0x0},
+	{0x90119, 0x0},
+	{0x9011a, 0x0},
+	{0x9011b, 0x0},
+	{0x9011c, 0x0},
+	{0x9011d, 0x0},
+	{0x9011e, 0x0},
+	{0x9011f, 0x0},
+	{0x90120, 0x0},
+	{0x90121, 0x0},
+	{0x90122, 0x0},
+	{0x90123, 0x0},
+	{0x90124, 0x0},
+	{0x90125, 0x0},
+	{0x90126, 0x0},
+	{0x90127, 0x0},
+	{0x90128, 0x0},
+	{0x90129, 0x0},
+	{0x9012a, 0x0},
+	{0x9012b, 0x0},
+	{0x9012c, 0x0},
+	{0x9012d, 0x0},
+	{0x9012e, 0x0},
+	{0x9012f, 0x0},
+	{0x90130, 0x0},
+	{0x90131, 0x0},
+	{0x90132, 0x0},
+	{0x90133, 0x0},
+	{0x90134, 0x0},
+	{0x90135, 0x0},
+	{0x90136, 0x0},
+	{0x90137, 0x0},
+	{0x90138, 0x0},
+	{0x90139, 0x0},
+	{0x9013a, 0x0},
+	{0x9013b, 0x0},
+	{0x9013c, 0x0},
+	{0x9013d, 0x0},
+	{0x9013e, 0x0},
+	{0x9013f, 0x0},
+	{0x90140, 0x0},
+	{0x90141, 0x0},
+	{0x90142, 0x0},
+	{0x90143, 0x0},
+	{0x90144, 0x0},
+	{0x90145, 0x0},
+	{0x90146, 0x0},
+	{0x90147, 0x0},
+	{0x90148, 0x0},
+	{0x90149, 0x0},
+	{0x9014a, 0x0},
+	{0x9014b, 0x0},
+	{0x9014c, 0x0},
+	{0x9014d, 0x0},
+	{0x9014e, 0x0},
+	{0x9014f, 0x0},
+	{0x90150, 0x0},
+	{0x90151, 0x0},
+	{0x90152, 0x0},
+	{0x90153, 0x0},
+	{0x90154, 0x0},
+	{0x90155, 0x0},
+	{0x90156, 0x0},
+	{0x90157, 0x0},
+	{0x90158, 0x0},
+	{0x90159, 0x0},
+	{0x9015a, 0x0},
+	{0x9015b, 0x0},
+	{0x9015c, 0x0},
+	{0x9015d, 0x0},
+	{0x9015e, 0x0},
+	{0x9015f, 0x0},
+	{0x90160, 0x0},
+	{0x90161, 0x0},
+	{0x90162, 0x0},
+	{0x90163, 0x0},
+	{0x90164, 0x0},
+	{0x90165, 0x0},
+	{0x90166, 0x0},
+	{0x90167, 0x0},
+	{0x90168, 0x0},
+	{0x90169, 0x0},
+	{0x9016a, 0x0},
+	{0x9016b, 0x0},
+	{0x9016c, 0x0},
+	{0x9016d, 0x0},
+	{0x9016e, 0x0},
+	{0x9016f, 0x0},
+	{0x90170, 0x0},
+	{0x90171, 0x0},
+	{0x90172, 0x0},
+	{0x90173, 0x0},
+	{0x90174, 0x0},
+	{0x90175, 0x0},
+	{0x90176, 0x0},
+	{0x90177, 0x0},
+	{0x90178, 0x0},
+	{0x90179, 0x0},
+	{0x9017a, 0x0},
+	{0x9017b, 0x0},
+	{0x9017c, 0x0},
+	{0x9017d, 0x0},
+	{0x9017e, 0x0},
+	{0x9017f, 0x0},
+	{0x90180, 0x0},
+	{0x90181, 0x0},
+	{0x90182, 0x0},
+	{0x90183, 0x0},
+	{0x90184, 0x0},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x0},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x0},
+	{0x90017, 0x0},
+	{0x9001f, 0x0},
+	{0x90026, 0x0},
+	{0x400d0, 0x0},
+	{0x400d1, 0x0},
+	{0x400d2, 0x0},
+	{0x400d3, 0x0},
+	{0x400d4, 0x0},
+	{0x400d5, 0x0},
+	{0x400d6, 0x0},
+	{0x400d7, 0x0},
+	{0x200be, 0x0},
+	{0x2000b, 0x0},
+	{0x2000c, 0x0},
+	{0x2000d, 0x0},
+	{0x2000e, 0x0},
+	{0x12000b, 0x0},
+	{0x12000c, 0x0},
+	{0x12000d, 0x0},
+	{0x12000e, 0x0},
+	{0x22000b, 0x0},
+	{0x22000c, 0x0},
+	{0x22000d, 0x0},
+	{0x22000e, 0x0},
+	{0x9000c, 0x0},
+	{0x9000d, 0x0},
+	{0x9000e, 0x0},
+	{0x9000f, 0x0},
+	{0x90010, 0x0},
+	{0x90011, 0x0},
+	{0x90012, 0x0},
+	{0x90013, 0x0},
+	{0x20010, 0x0},
+	{0x20011, 0x0},
+	{0x120010, 0x0},
+	{0x120011, 0x0},
+	{0x40080, 0x0},
+	{0x40081, 0x0},
+	{0x40082, 0x0},
+	{0x40083, 0x0},
+	{0x40084, 0x0},
+	{0x40085, 0x0},
+	{0x140080, 0x0},
+	{0x140081, 0x0},
+	{0x140082, 0x0},
+	{0x140083, 0x0},
+	{0x140084, 0x0},
+	{0x140085, 0x0},
+	{0x240080, 0x0},
+	{0x240081, 0x0},
+	{0x240082, 0x0},
+	{0x240083, 0x0},
+	{0x240084, 0x0},
+	{0x240085, 0x0},
+	{0x400fd, 0x0},
+	{0x400f1, 0x0},
+	{0x10011, 0x0},
+	{0x10012, 0x0},
+	{0x10013, 0x0},
+	{0x10018, 0x0},
+	{0x10002, 0x0},
+	{0x100b2, 0x0},
+	{0x101b4, 0x0},
+	{0x102b4, 0x0},
+	{0x103b4, 0x0},
+	{0x104b4, 0x0},
+	{0x105b4, 0x0},
+	{0x106b4, 0x0},
+	{0x107b4, 0x0},
+	{0x108b4, 0x0},
+	{0x11011, 0x0},
+	{0x11012, 0x0},
+	{0x11013, 0x0},
+	{0x11018, 0x0},
+	{0x11002, 0x0},
+	{0x110b2, 0x0},
+	{0x111b4, 0x0},
+	{0x112b4, 0x0},
+	{0x113b4, 0x0},
+	{0x114b4, 0x0},
+	{0x115b4, 0x0},
+	{0x116b4, 0x0},
+	{0x117b4, 0x0},
+	{0x118b4, 0x0},
+	{0x20089, 0x0},
+	{0xc0080, 0x0},
+	{0x200cb, 0x0},
+	{0x10068, 0x0},
+	{0x10069, 0x0},
+	{0x10168, 0x0},
+	{0x10169, 0x0},
+	{0x10268, 0x0},
+	{0x10269, 0x0},
+	{0x10368, 0x0},
+	{0x10369, 0x0},
+	{0x10468, 0x0},
+	{0x10469, 0x0},
+	{0x10568, 0x0},
+	{0x10569, 0x0},
+	{0x10668, 0x0},
+	{0x10669, 0x0},
+	{0x10768, 0x0},
+	{0x10769, 0x0},
+	{0x10868, 0x0},
+	{0x10869, 0x0},
+	{0x100aa, 0x0},
+	{0x10062, 0x0},
+	{0x10001, 0x0},
+	{0x100a0, 0x0},
+	{0x100a1, 0x0},
+	{0x100a2, 0x0},
+	{0x100a3, 0x0},
+	{0x100a4, 0x0},
+	{0x100a5, 0x0},
+	{0x100a6, 0x0},
+	{0x100a7, 0x0},
+	{0x11068, 0x0},
+	{0x11069, 0x0},
+	{0x11168, 0x0},
+	{0x11169, 0x0},
+	{0x11268, 0x0},
+	{0x11269, 0x0},
+	{0x11368, 0x0},
+	{0x11369, 0x0},
+	{0x11468, 0x0},
+	{0x11469, 0x0},
+	{0x11568, 0x0},
+	{0x11569, 0x0},
+	{0x11668, 0x0},
+	{0x11669, 0x0},
+	{0x11768, 0x0},
+	{0x11769, 0x0},
+	{0x11868, 0x0},
+	{0x11869, 0x0},
+	{0x110aa, 0x0},
+	{0x11062, 0x0},
+	{0x11001, 0x0},
+	{0x110a0, 0x0},
+	{0x110a1, 0x0},
+	{0x110a2, 0x0},
+	{0x110a3, 0x0},
+	{0x110a4, 0x0},
+	{0x110a5, 0x0},
+	{0x110a6, 0x0},
+	{0x110a7, 0x0},
+	{0x80, 0x0},
+	{0x1080, 0x0},
+	{0x2080, 0x0},
+	{0x10020, 0x0},
+	{0x10080, 0x0},
+	{0x10081, 0x0},
+	{0x100d0, 0x0},
+	{0x100d1, 0x0},
+	{0x1008c, 0x0},
+	{0x1008d, 0x0},
+	{0x10180, 0x0},
+	{0x10181, 0x0},
+	{0x101d0, 0x0},
+	{0x101d1, 0x0},
+	{0x1018c, 0x0},
+	{0x1018d, 0x0},
+	{0x100c0, 0x0},
+	{0x100c1, 0x0},
+	{0x101c0, 0x0},
+	{0x101c1, 0x0},
+	{0x102c0, 0x0},
+	{0x102c1, 0x0},
+	{0x103c0, 0x0},
+	{0x103c1, 0x0},
+	{0x104c0, 0x0},
+	{0x104c1, 0x0},
+	{0x105c0, 0x0},
+	{0x105c1, 0x0},
+	{0x106c0, 0x0},
+	{0x106c1, 0x0},
+	{0x107c0, 0x0},
+	{0x107c1, 0x0},
+	{0x108c0, 0x0},
+	{0x108c1, 0x0},
+	{0x100ae, 0x0},
+	{0x100af, 0x0},
+	{0x11020, 0x0},
+	{0x11080, 0x0},
+	{0x11081, 0x0},
+	{0x110d0, 0x0},
+	{0x110d1, 0x0},
+	{0x1108c, 0x0},
+	{0x1108d, 0x0},
+	{0x11180, 0x0},
+	{0x11181, 0x0},
+	{0x111d0, 0x0},
+	{0x111d1, 0x0},
+	{0x1118c, 0x0},
+	{0x1118d, 0x0},
+	{0x110c0, 0x0},
+	{0x110c1, 0x0},
+	{0x111c0, 0x0},
+	{0x111c1, 0x0},
+	{0x112c0, 0x0},
+	{0x112c1, 0x0},
+	{0x113c0, 0x0},
+	{0x113c1, 0x0},
+	{0x114c0, 0x0},
+	{0x114c1, 0x0},
+	{0x115c0, 0x0},
+	{0x115c1, 0x0},
+	{0x116c0, 0x0},
+	{0x116c1, 0x0},
+	{0x117c0, 0x0},
+	{0x117c1, 0x0},
+	{0x118c0, 0x0},
+	{0x118c1, 0x0},
+	{0x110ae, 0x0},
+	{0x110af, 0x0},
+	{0x90201, 0x0},
+	{0x90202, 0x0},
+	{0x90203, 0x0},
+	{0x90205, 0x0},
+	{0x90206, 0x0},
+	{0x90207, 0x0},
+	{0x90208, 0x0},
+	{0x20020, 0x0},
+	{0x100080, 0x0},
+	{0x101080, 0x0},
+	{0x102080, 0x0},
+	{0x110020, 0x0},
+	{0x110080, 0x0},
+	{0x110081, 0x0},
+	{0x1100d0, 0x0},
+	{0x1100d1, 0x0},
+	{0x11008c, 0x0},
+	{0x11008d, 0x0},
+	{0x110180, 0x0},
+	{0x110181, 0x0},
+	{0x1101d0, 0x0},
+	{0x1101d1, 0x0},
+	{0x11018c, 0x0},
+	{0x11018d, 0x0},
+	{0x1100c0, 0x0},
+	{0x1100c1, 0x0},
+	{0x1101c0, 0x0},
+	{0x1101c1, 0x0},
+	{0x1102c0, 0x0},
+	{0x1102c1, 0x0},
+	{0x1103c0, 0x0},
+	{0x1103c1, 0x0},
+	{0x1104c0, 0x0},
+	{0x1104c1, 0x0},
+	{0x1105c0, 0x0},
+	{0x1105c1, 0x0},
+	{0x1106c0, 0x0},
+	{0x1106c1, 0x0},
+	{0x1107c0, 0x0},
+	{0x1107c1, 0x0},
+	{0x1108c0, 0x0},
+	{0x1108c1, 0x0},
+	{0x1100ae, 0x0},
+	{0x1100af, 0x0},
+	{0x111020, 0x0},
+	{0x111080, 0x0},
+	{0x111081, 0x0},
+	{0x1110d0, 0x0},
+	{0x1110d1, 0x0},
+	{0x11108c, 0x0},
+	{0x11108d, 0x0},
+	{0x111180, 0x0},
+	{0x111181, 0x0},
+	{0x1111d0, 0x0},
+	{0x1111d1, 0x0},
+	{0x11118c, 0x0},
+	{0x11118d, 0x0},
+	{0x1110c0, 0x0},
+	{0x1110c1, 0x0},
+	{0x1111c0, 0x0},
+	{0x1111c1, 0x0},
+	{0x1112c0, 0x0},
+	{0x1112c1, 0x0},
+	{0x1113c0, 0x0},
+	{0x1113c1, 0x0},
+	{0x1114c0, 0x0},
+	{0x1114c1, 0x0},
+	{0x1115c0, 0x0},
+	{0x1115c1, 0x0},
+	{0x1116c0, 0x0},
+	{0x1116c1, 0x0},
+	{0x1117c0, 0x0},
+	{0x1117c1, 0x0},
+	{0x1118c0, 0x0},
+	{0x1118c1, 0x0},
+	{0x1110ae, 0x0},
+	{0x1110af, 0x0},
+	{0x190201, 0x0},
+	{0x190202, 0x0},
+	{0x190203, 0x0},
+	{0x190205, 0x0},
+	{0x190206, 0x0},
+	{0x190207, 0x0},
+	{0x190208, 0x0},
+	{0x120020, 0x0},
+	{0x200080, 0x0},
+	{0x201080, 0x0},
+	{0x202080, 0x0},
+	{0x210020, 0x0},
+	{0x210080, 0x0},
+	{0x210081, 0x0},
+	{0x2100d0, 0x0},
+	{0x2100d1, 0x0},
+	{0x21008c, 0x0},
+	{0x21008d, 0x0},
+	{0x210180, 0x0},
+	{0x210181, 0x0},
+	{0x2101d0, 0x0},
+	{0x2101d1, 0x0},
+	{0x21018c, 0x0},
+	{0x21018d, 0x0},
+	{0x2100c0, 0x0},
+	{0x2100c1, 0x0},
+	{0x2101c0, 0x0},
+	{0x2101c1, 0x0},
+	{0x2102c0, 0x0},
+	{0x2102c1, 0x0},
+	{0x2103c0, 0x0},
+	{0x2103c1, 0x0},
+	{0x2104c0, 0x0},
+	{0x2104c1, 0x0},
+	{0x2105c0, 0x0},
+	{0x2105c1, 0x0},
+	{0x2106c0, 0x0},
+	{0x2106c1, 0x0},
+	{0x2107c0, 0x0},
+	{0x2107c1, 0x0},
+	{0x2108c0, 0x0},
+	{0x2108c1, 0x0},
+	{0x2100ae, 0x0},
+	{0x2100af, 0x0},
+	{0x211020, 0x0},
+	{0x211080, 0x0},
+	{0x211081, 0x0},
+	{0x2110d0, 0x0},
+	{0x2110d1, 0x0},
+	{0x21108c, 0x0},
+	{0x21108d, 0x0},
+	{0x211180, 0x0},
+	{0x211181, 0x0},
+	{0x2111d0, 0x0},
+	{0x2111d1, 0x0},
+	{0x21118c, 0x0},
+	{0x21118d, 0x0},
+	{0x2110c0, 0x0},
+	{0x2110c1, 0x0},
+	{0x2111c0, 0x0},
+	{0x2111c1, 0x0},
+	{0x2112c0, 0x0},
+	{0x2112c1, 0x0},
+	{0x2113c0, 0x0},
+	{0x2113c1, 0x0},
+	{0x2114c0, 0x0},
+	{0x2114c1, 0x0},
+	{0x2115c0, 0x0},
+	{0x2115c1, 0x0},
+	{0x2116c0, 0x0},
+	{0x2116c1, 0x0},
+	{0x2117c0, 0x0},
+	{0x2117c1, 0x0},
+	{0x2118c0, 0x0},
+	{0x2118c1, 0x0},
+	{0x2110ae, 0x0},
+	{0x2110af, 0x0},
+	{0x290201, 0x0},
+	{0x290202, 0x0},
+	{0x290203, 0x0},
+	{0x290205, 0x0},
+	{0x290206, 0x0},
+	{0x290207, 0x0},
+	{0x290208, 0x0},
+	{0x220020, 0x0},
+	{0x20077, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
+	{0x400c0, 0x0},
+	{0x10040, 0x0},
+	{0x10140, 0x0},
+	{0x10240, 0x0},
+	{0x10340, 0x0},
+	{0x10440, 0x0},
+	{0x10540, 0x0},
+	{0x10640, 0x0},
+	{0x10740, 0x0},
+	{0x10840, 0x0},
+	{0x11040, 0x0},
+	{0x11140, 0x0},
+	{0x11240, 0x0},
+	{0x11340, 0x0},
+	{0x11440, 0x0},
+	{0x11540, 0x0},
+	{0x11640, 0x0},
+	{0x11740, 0x0},
+	{0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x640},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x52a4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x52a4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xa400},
+	{0x54033, 0x3352},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xa400},
+	{0x54039, 0x3352},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x320},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x3309},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x3309},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x270},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4800},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4800},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x3309},
+	{0x54034, 0x4600},
+	{0x54035, 0x11},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x3309},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x11},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x640},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54010, 0x2080},
+	{0x54012, 0x110},
+	{0x54019, 0x52a4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x52a4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xa400},
+	{0x54033, 0x3352},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xa400},
+	{0x54039, 0x3352},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x30},
+	{0x90051, 0x65a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x45a},
+	{0x90055, 0x9},
+	{0x90056, 0x0},
+	{0x90057, 0x448},
+	{0x90058, 0x109},
+	{0x90059, 0x40},
+	{0x9005a, 0x633},
+	{0x9005b, 0x179},
+	{0x9005c, 0x1},
+	{0x9005d, 0x618},
+	{0x9005e, 0x109},
+	{0x9005f, 0x40c0},
+	{0x90060, 0x633},
+	{0x90061, 0x149},
+	{0x90062, 0x8},
+	{0x90063, 0x4},
+	{0x90064, 0x48},
+	{0x90065, 0x4040},
+	{0x90066, 0x633},
+	{0x90067, 0x149},
+	{0x90068, 0x0},
+	{0x90069, 0x4},
+	{0x9006a, 0x48},
+	{0x9006b, 0x40},
+	{0x9006c, 0x633},
+	{0x9006d, 0x149},
+	{0x9006e, 0x0},
+	{0x9006f, 0x658},
+	{0x90070, 0x109},
+	{0x90071, 0x10},
+	{0x90072, 0x4},
+	{0x90073, 0x18},
+	{0x90074, 0x0},
+	{0x90075, 0x4},
+	{0x90076, 0x78},
+	{0x90077, 0x549},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0xd49},
+	{0x9007b, 0x633},
+	{0x9007c, 0x159},
+	{0x9007d, 0x94a},
+	{0x9007e, 0x633},
+	{0x9007f, 0x159},
+	{0x90080, 0x441},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x42},
+	{0x90084, 0x633},
+	{0x90085, 0x149},
+	{0x90086, 0x1},
+	{0x90087, 0x633},
+	{0x90088, 0x149},
+	{0x90089, 0x0},
+	{0x9008a, 0xe0},
+	{0x9008b, 0x109},
+	{0x9008c, 0xa},
+	{0x9008d, 0x10},
+	{0x9008e, 0x109},
+	{0x9008f, 0x9},
+	{0x90090, 0x3c0},
+	{0x90091, 0x149},
+	{0x90092, 0x9},
+	{0x90093, 0x3c0},
+	{0x90094, 0x159},
+	{0x90095, 0x18},
+	{0x90096, 0x10},
+	{0x90097, 0x109},
+	{0x90098, 0x0},
+	{0x90099, 0x3c0},
+	{0x9009a, 0x109},
+	{0x9009b, 0x18},
+	{0x9009c, 0x4},
+	{0x9009d, 0x48},
+	{0x9009e, 0x18},
+	{0x9009f, 0x4},
+	{0x900a0, 0x58},
+	{0x900a1, 0xb},
+	{0x900a2, 0x10},
+	{0x900a3, 0x109},
+	{0x900a4, 0x1},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x900a7, 0x5},
+	{0x900a8, 0x7c0},
+	{0x900a9, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x790},
+	{0x900ac, 0x11a},
+	{0x900ad, 0x8},
+	{0x900ae, 0x7aa},
+	{0x900af, 0x2a},
+	{0x900b0, 0x10},
+	{0x900b1, 0x7b2},
+	{0x900b2, 0x2a},
+	{0x900b3, 0x0},
+	{0x900b4, 0x7c8},
+	{0x900b5, 0x109},
+	{0x900b6, 0x10},
+	{0x900b7, 0x10},
+	{0x900b8, 0x109},
+	{0x900b9, 0x10},
+	{0x900ba, 0x2a8},
+	{0x900bb, 0x129},
+	{0x900bc, 0x8},
+	{0x900bd, 0x370},
+	{0x900be, 0x129},
+	{0x900bf, 0xa},
+	{0x900c0, 0x3c8},
+	{0x900c1, 0x1a9},
+	{0x900c2, 0xc},
+	{0x900c3, 0x408},
+	{0x900c4, 0x199},
+	{0x900c5, 0x14},
+	{0x900c6, 0x790},
+	{0x900c7, 0x11a},
+	{0x900c8, 0x8},
+	{0x900c9, 0x4},
+	{0x900ca, 0x18},
+	{0x900cb, 0xe},
+	{0x900cc, 0x408},
+	{0x900cd, 0x199},
+	{0x900ce, 0x8},
+	{0x900cf, 0x8568},
+	{0x900d0, 0x108},
+	{0x900d1, 0x18},
+	{0x900d2, 0x790},
+	{0x900d3, 0x16a},
+	{0x900d4, 0x8},
+	{0x900d5, 0x1d8},
+	{0x900d6, 0x169},
+	{0x900d7, 0x10},
+	{0x900d8, 0x8558},
+	{0x900d9, 0x168},
+	{0x900da, 0x1ff8},
+	{0x900db, 0x85a8},
+	{0x900dc, 0x1e8},
+	{0x900dd, 0x50},
+	{0x900de, 0x798},
+	{0x900df, 0x16a},
+	{0x900e0, 0x60},
+	{0x900e1, 0x7a0},
+	{0x900e2, 0x16a},
+	{0x900e3, 0x8},
+	{0x900e4, 0x8310},
+	{0x900e5, 0x168},
+	{0x900e6, 0x8},
+	{0x900e7, 0xa310},
+	{0x900e8, 0x168},
+	{0x900e9, 0xa},
+	{0x900ea, 0x408},
+	{0x900eb, 0x169},
+	{0x900ec, 0x6e},
+	{0x900ed, 0x0},
+	{0x900ee, 0x68},
+	{0x900ef, 0x0},
+	{0x900f0, 0x408},
+	{0x900f1, 0x169},
+	{0x900f2, 0x0},
+	{0x900f3, 0x8310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x0},
+	{0x900f6, 0xa310},
+	{0x900f7, 0x168},
+	{0x900f8, 0x1ff8},
+	{0x900f9, 0x85a8},
+	{0x900fa, 0x1e8},
+	{0x900fb, 0x68},
+	{0x900fc, 0x798},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x78},
+	{0x900ff, 0x7a0},
+	{0x90100, 0x16a},
+	{0x90101, 0x68},
+	{0x90102, 0x790},
+	{0x90103, 0x16a},
+	{0x90104, 0x8},
+	{0x90105, 0x8b10},
+	{0x90106, 0x168},
+	{0x90107, 0x8},
+	{0x90108, 0xab10},
+	{0x90109, 0x168},
+	{0x9010a, 0xa},
+	{0x9010b, 0x408},
+	{0x9010c, 0x169},
+	{0x9010d, 0x58},
+	{0x9010e, 0x0},
+	{0x9010f, 0x68},
+	{0x90110, 0x0},
+	{0x90111, 0x408},
+	{0x90112, 0x169},
+	{0x90113, 0x0},
+	{0x90114, 0x8b10},
+	{0x90115, 0x168},
+	{0x90116, 0x1},
+	{0x90117, 0xab10},
+	{0x90118, 0x168},
+	{0x90119, 0x0},
+	{0x9011a, 0x1d8},
+	{0x9011b, 0x169},
+	{0x9011c, 0x80},
+	{0x9011d, 0x790},
+	{0x9011e, 0x16a},
+	{0x9011f, 0x18},
+	{0x90120, 0x7aa},
+	{0x90121, 0x6a},
+	{0x90122, 0xa},
+	{0x90123, 0x0},
+	{0x90124, 0x1e9},
+	{0x90125, 0x8},
+	{0x90126, 0x8080},
+	{0x90127, 0x108},
+	{0x90128, 0xf},
+	{0x90129, 0x408},
+	{0x9012a, 0x169},
+	{0x9012b, 0xc},
+	{0x9012c, 0x0},
+	{0x9012d, 0x68},
+	{0x9012e, 0x9},
+	{0x9012f, 0x0},
+	{0x90130, 0x1a9},
+	{0x90131, 0x0},
+	{0x90132, 0x408},
+	{0x90133, 0x169},
+	{0x90134, 0x0},
+	{0x90135, 0x8080},
+	{0x90136, 0x108},
+	{0x90137, 0x8},
+	{0x90138, 0x7aa},
+	{0x90139, 0x6a},
+	{0x9013a, 0x0},
+	{0x9013b, 0x8568},
+	{0x9013c, 0x108},
+	{0x9013d, 0xb7},
+	{0x9013e, 0x790},
+	{0x9013f, 0x16a},
+	{0x90140, 0x1f},
+	{0x90141, 0x0},
+	{0x90142, 0x68},
+	{0x90143, 0x8},
+	{0x90144, 0x8558},
+	{0x90145, 0x168},
+	{0x90146, 0xf},
+	{0x90147, 0x408},
+	{0x90148, 0x169},
+	{0x90149, 0xd},
+	{0x9014a, 0x0},
+	{0x9014b, 0x68},
+	{0x9014c, 0x0},
+	{0x9014d, 0x408},
+	{0x9014e, 0x169},
+	{0x9014f, 0x0},
+	{0x90150, 0x8558},
+	{0x90151, 0x168},
+	{0x90152, 0x8},
+	{0x90153, 0x3c8},
+	{0x90154, 0x1a9},
+	{0x90155, 0x3},
+	{0x90156, 0x370},
+	{0x90157, 0x129},
+	{0x90158, 0x20},
+	{0x90159, 0x2aa},
+	{0x9015a, 0x9},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x104},
+	{0x90164, 0x8},
+	{0x90165, 0x448},
+	{0x90166, 0x109},
+	{0x90167, 0xf},
+	{0x90168, 0x7c0},
+	{0x90169, 0x109},
+	{0x9016a, 0x0},
+	{0x9016b, 0xe8},
+	{0x9016c, 0x109},
+	{0x9016d, 0x47},
+	{0x9016e, 0x630},
+	{0x9016f, 0x109},
+	{0x90170, 0x8},
+	{0x90171, 0x618},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0xe0},
+	{0x90175, 0x109},
+	{0x90176, 0x0},
+	{0x90177, 0x7c8},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0x8140},
+	{0x9017b, 0x10c},
+	{0x9017c, 0x0},
+	{0x9017d, 0x478},
+	{0x9017e, 0x109},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x0},
+	{0x90006, 0x8},
+	{0x90007, 0x7c8},
+	{0x90008, 0x109},
+	{0x90009, 0x0},
+	{0x9000a, 0x400},
+	{0x9000b, 0x106},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2b},
+	{0x90026, 0x69},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x200be, 0x3},
+	{0x2000b, 0x1c2},
+	{0x2000c, 0x64},
+	{0x2000d, 0x3e8},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xe1},
+	{0x12000c, 0x32},
+	{0x12000d, 0x1f4},
+	{0x12000e, 0x10},
+	{0x22000b, 0xb0},
+	{0x22000c, 0x27},
+	{0x22000d, 0x186},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x400f1, 0xe},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x0},
+	{0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 800mts 1D */
+		.drate = 800,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 1600mts 2D */
+		.drate = 1600,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1600mts = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 800, 625, },
+	.fsp_cfg = ddr_dram_fsp_cfg,
+	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c
new file mode 100644
index 00000000000..4594ab68aa0
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x4e300110, 0x44100001},
+	{0x4e300000, 0x8000ef},
+	{0x4e300008, 0x0},
+	{0x4e300080, 0x80000512},
+	{0x4e300084, 0x0},
+	{0x4e300114, 0x1012},
+	{0x4e300260, 0x80},
+	{0x4e300f04, 0x80},
+	{0x4e300800, 0x43b30d00},
+	{0x4e300804, 0x1f1f1f1f},
+	{0x4e301000, 0xc0000000},
+	{0x4e301240, 0x0},
+	{0x4e301244, 0x0},
+	{0x4e301248, 0x0},
+	{0x4e30124c, 0x0},
+	{0x4e301250, 0x0},
+	{0x4e301254, 0x0},
+	{0x4e301258, 0x0},
+	{0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+	{
+		{
+			{0x4e300100, 0x02121100},
+			{0x4e300104, 0xF866000C},
+			{0x4e300108, 0xF2FA8088},
+			{0x4e30010C, 0x0061E1A0},
+			{0x4e300124, 0x0C340000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30700000},
+			{0x4e300170, 0x8A0A0508},
+			{0x4e300250, 0x00000011},
+			{0x4e300254, 0x00900090},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+			{0x4e300300, 0x0F220F09},
+			{0x4e300304, 0x00901008},
+			{0x4e300308, 0x063C061A},
+		},
+		{
+			{0x01, 0xA4},
+			{0x02, 0x52},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x00091000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x81820A48},
+			{0x4e30010C, 0x00310110},
+			{0x4e300124, 0x061A0000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30100000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000009},
+			{0x4e300254, 0x00440044},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x00061000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x6E62FA48},
+			{0x4e30010C, 0x0031010D},
+			{0x4e300124, 0x04C50000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30000000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000007},
+			{0x4e300254, 0x00340034},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		1,
+	},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x4},
+	{0x100a1, 0x5},
+	{0x100a2, 0x6},
+	{0x100a3, 0x7},
+	{0x100a4, 0x0},
+	{0x100a5, 0x1},
+	{0x100a6, 0x2},
+	{0x100a7, 0x3},
+	{0x110a0, 0x3},
+	{0x110a1, 0x2},
+	{0x110a2, 0x0},
+	{0x110a3, 0x1},
+	{0x110a4, 0x7},
+	{0x110a5, 0x6},
+	{0x110a6, 0x4},
+	{0x110a7, 0x5},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x200c5, 0xb},
+	{0x1200c5, 0x3},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x1},
+	{0x12002e, 0x1},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x2007d, 0x212},
+	{0x2007c, 0x61},
+	{0x120024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x12007d, 0x212},
+	{0x12007c, 0x61},
+	{0x220024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x22007d, 0x212},
+	{0x22007c, 0x61},
+	{0x20056, 0x3},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
+	{0x1004d, 0x600},
+	{0x1014d, 0x600},
+	{0x1104d, 0x600},
+	{0x1114d, 0x600},
+	{0x11004d, 0x600},
+	{0x11014d, 0x600},
+	{0x11104d, 0x600},
+	{0x11114d, 0x600},
+	{0x21004d, 0x600},
+	{0x21014d, 0x600},
+	{0x21104d, 0x600},
+	{0x21114d, 0x600},
+	{0x10049, 0xe3f},
+	{0x10149, 0xe3f},
+	{0x11049, 0xe3f},
+	{0x11149, 0xe3f},
+	{0x110049, 0xe3f},
+	{0x110149, 0xe3f},
+	{0x111049, 0xe3f},
+	{0x111149, 0xe3f},
+	{0x210049, 0xe3f},
+	{0x210149, 0xe3f},
+	{0x211049, 0xe3f},
+	{0x211149, 0xe3f},
+	{0x43, 0x7f},
+	{0x1043, 0x7f},
+	{0x2043, 0x7f},
+	{0x20018, 0x1},
+	{0x20075, 0x4},
+	{0x20050, 0x11},
+	{0x2009b, 0x2},
+	{0x20008, 0x190},
+	{0x120008, 0xc8},
+	{0x220008, 0x9c},
+	{0x20088, 0x9},
+	{0x200b2, 0x10c},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x1200b2, 0x10c},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x2200b2, 0x10c},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x200fa, 0x2},
+	{0x1200fa, 0x2},
+	{0x2200fa, 0x2},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x600},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5655},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x1004a, 0x500},
+	{0x1104a, 0x500},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0x20021, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x41},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x1005f, 0x0},
+	{0x1015f, 0x0},
+	{0x1105f, 0x0},
+	{0x1115f, 0x0},
+	{0x11005f, 0x0},
+	{0x11015f, 0x0},
+	{0x11105f, 0x0},
+	{0x11115f, 0x0},
+	{0x21005f, 0x0},
+	{0x21015f, 0x0},
+	{0x21105f, 0x0},
+	{0x21115f, 0x0},
+	{0x55, 0x0},
+	{0x1055, 0x0},
+	{0x2055, 0x0},
+	{0x200c5, 0x0},
+	{0x1200c5, 0x0},
+	{0x2200c5, 0x0},
+	{0x2002e, 0x0},
+	{0x12002e, 0x0},
+	{0x22002e, 0x0},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x0},
+	{0x2003a, 0x0},
+	{0x2007d, 0x0},
+	{0x2007c, 0x0},
+	{0x120024, 0x0},
+	{0x12007d, 0x0},
+	{0x12007c, 0x0},
+	{0x220024, 0x0},
+	{0x22007d, 0x0},
+	{0x22007c, 0x0},
+	{0x20056, 0x0},
+	{0x120056, 0x0},
+	{0x220056, 0x0},
+	{0x1004d, 0x0},
+	{0x1014d, 0x0},
+	{0x1104d, 0x0},
+	{0x1114d, 0x0},
+	{0x11004d, 0x0},
+	{0x11014d, 0x0},
+	{0x11104d, 0x0},
+	{0x11114d, 0x0},
+	{0x21004d, 0x0},
+	{0x21014d, 0x0},
+	{0x21104d, 0x0},
+	{0x21114d, 0x0},
+	{0x10049, 0x0},
+	{0x10149, 0x0},
+	{0x11049, 0x0},
+	{0x11149, 0x0},
+	{0x110049, 0x0},
+	{0x110149, 0x0},
+	{0x111049, 0x0},
+	{0x111149, 0x0},
+	{0x210049, 0x0},
+	{0x210149, 0x0},
+	{0x211049, 0x0},
+	{0x211149, 0x0},
+	{0x43, 0x0},
+	{0x1043, 0x0},
+	{0x2043, 0x0},
+	{0x20018, 0x0},
+	{0x20075, 0x0},
+	{0x20050, 0x0},
+	{0x2009b, 0x0},
+	{0x20008, 0x0},
+	{0x120008, 0x0},
+	{0x220008, 0x0},
+	{0x20088, 0x0},
+	{0x200b2, 0x0},
+	{0x10043, 0x0},
+	{0x10143, 0x0},
+	{0x11043, 0x0},
+	{0x11143, 0x0},
+	{0x1200b2, 0x0},
+	{0x110043, 0x0},
+	{0x110143, 0x0},
+	{0x111043, 0x0},
+	{0x111143, 0x0},
+	{0x2200b2, 0x0},
+	{0x210043, 0x0},
+	{0x210143, 0x0},
+	{0x211043, 0x0},
+	{0x211143, 0x0},
+	{0x200fa, 0x0},
+	{0x1200fa, 0x0},
+	{0x2200fa, 0x0},
+	{0x20019, 0x0},
+	{0x120019, 0x0},
+	{0x220019, 0x0},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x0},
+	{0x200f3, 0x0},
+	{0x200f4, 0x0},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0x0},
+	{0x1004a, 0x0},
+	{0x1104a, 0x0},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0xd0000, 0x0},
+	{0x90000, 0x0},
+	{0x90001, 0x0},
+	{0x90002, 0x0},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x0},
+	{0x90029, 0x0},
+	{0x9002a, 0x0},
+	{0x9002b, 0x0},
+	{0x9002c, 0x0},
+	{0x9002d, 0x0},
+	{0x9002e, 0x0},
+	{0x9002f, 0x0},
+	{0x90030, 0x0},
+	{0x90031, 0x0},
+	{0x90032, 0x0},
+	{0x90033, 0x0},
+	{0x90034, 0x0},
+	{0x90035, 0x0},
+	{0x90036, 0x0},
+	{0x90037, 0x0},
+	{0x90038, 0x0},
+	{0x90039, 0x0},
+	{0x9003a, 0x0},
+	{0x9003b, 0x0},
+	{0x9003c, 0x0},
+	{0x9003d, 0x0},
+	{0x9003e, 0x0},
+	{0x9003f, 0x0},
+	{0x90040, 0x0},
+	{0x90041, 0x0},
+	{0x90042, 0x0},
+	{0x90043, 0x0},
+	{0x90044, 0x0},
+	{0x90045, 0x0},
+	{0x90046, 0x0},
+	{0x90047, 0x0},
+	{0x90048, 0x0},
+	{0x90049, 0x0},
+	{0x9004a, 0x0},
+	{0x9004b, 0x0},
+	{0x9004c, 0x0},
+	{0x9004d, 0x0},
+	{0x9004e, 0x0},
+	{0x9004f, 0x0},
+	{0x90050, 0x0},
+	{0x90051, 0x0},
+	{0x90052, 0x0},
+	{0x90053, 0x0},
+	{0x90054, 0x0},
+	{0x90055, 0x0},
+	{0x90056, 0x0},
+	{0x90057, 0x0},
+	{0x90058, 0x0},
+	{0x90059, 0x0},
+	{0x9005a, 0x0},
+	{0x9005b, 0x0},
+	{0x9005c, 0x0},
+	{0x9005d, 0x0},
+	{0x9005e, 0x0},
+	{0x9005f, 0x0},
+	{0x90060, 0x0},
+	{0x90061, 0x0},
+	{0x90062, 0x0},
+	{0x90063, 0x0},
+	{0x90064, 0x0},
+	{0x90065, 0x0},
+	{0x90066, 0x0},
+	{0x90067, 0x0},
+	{0x90068, 0x0},
+	{0x90069, 0x0},
+	{0x9006a, 0x0},
+	{0x9006b, 0x0},
+	{0x9006c, 0x0},
+	{0x9006d, 0x0},
+	{0x9006e, 0x0},
+	{0x9006f, 0x0},
+	{0x90070, 0x0},
+	{0x90071, 0x0},
+	{0x90072, 0x0},
+	{0x90073, 0x0},
+	{0x90074, 0x0},
+	{0x90075, 0x0},
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+	{0x108c1, 0x0},
+	{0x100ae, 0x0},
+	{0x100af, 0x0},
+	{0x11020, 0x0},
+	{0x11080, 0x0},
+	{0x11081, 0x0},
+	{0x110d0, 0x0},
+	{0x110d1, 0x0},
+	{0x1108c, 0x0},
+	{0x1108d, 0x0},
+	{0x11180, 0x0},
+	{0x11181, 0x0},
+	{0x111d0, 0x0},
+	{0x111d1, 0x0},
+	{0x1118c, 0x0},
+	{0x1118d, 0x0},
+	{0x110c0, 0x0},
+	{0x110c1, 0x0},
+	{0x111c0, 0x0},
+	{0x111c1, 0x0},
+	{0x112c0, 0x0},
+	{0x112c1, 0x0},
+	{0x113c0, 0x0},
+	{0x113c1, 0x0},
+	{0x114c0, 0x0},
+	{0x114c1, 0x0},
+	{0x115c0, 0x0},
+	{0x115c1, 0x0},
+	{0x116c0, 0x0},
+	{0x116c1, 0x0},
+	{0x117c0, 0x0},
+	{0x117c1, 0x0},
+	{0x118c0, 0x0},
+	{0x118c1, 0x0},
+	{0x110ae, 0x0},
+	{0x110af, 0x0},
+	{0x90201, 0x0},
+	{0x90202, 0x0},
+	{0x90203, 0x0},
+	{0x90205, 0x0},
+	{0x90206, 0x0},
+	{0x90207, 0x0},
+	{0x90208, 0x0},
+	{0x20020, 0x0},
+	{0x100080, 0x0},
+	{0x101080, 0x0},
+	{0x102080, 0x0},
+	{0x110020, 0x0},
+	{0x110080, 0x0},
+	{0x110081, 0x0},
+	{0x1100d0, 0x0},
+	{0x1100d1, 0x0},
+	{0x11008c, 0x0},
+	{0x11008d, 0x0},
+	{0x110180, 0x0},
+	{0x110181, 0x0},
+	{0x1101d0, 0x0},
+	{0x1101d1, 0x0},
+	{0x11018c, 0x0},
+	{0x11018d, 0x0},
+	{0x1100c0, 0x0},
+	{0x1100c1, 0x0},
+	{0x1101c0, 0x0},
+	{0x1101c1, 0x0},
+	{0x1102c0, 0x0},
+	{0x1102c1, 0x0},
+	{0x1103c0, 0x0},
+	{0x1103c1, 0x0},
+	{0x1104c0, 0x0},
+	{0x1104c1, 0x0},
+	{0x1105c0, 0x0},
+	{0x1105c1, 0x0},
+	{0x1106c0, 0x0},
+	{0x1106c1, 0x0},
+	{0x1107c0, 0x0},
+	{0x1107c1, 0x0},
+	{0x1108c0, 0x0},
+	{0x1108c1, 0x0},
+	{0x1100ae, 0x0},
+	{0x1100af, 0x0},
+	{0x111020, 0x0},
+	{0x111080, 0x0},
+	{0x111081, 0x0},
+	{0x1110d0, 0x0},
+	{0x1110d1, 0x0},
+	{0x11108c, 0x0},
+	{0x11108d, 0x0},
+	{0x111180, 0x0},
+	{0x111181, 0x0},
+	{0x1111d0, 0x0},
+	{0x1111d1, 0x0},
+	{0x11118c, 0x0},
+	{0x11118d, 0x0},
+	{0x1110c0, 0x0},
+	{0x1110c1, 0x0},
+	{0x1111c0, 0x0},
+	{0x1111c1, 0x0},
+	{0x1112c0, 0x0},
+	{0x1112c1, 0x0},
+	{0x1113c0, 0x0},
+	{0x1113c1, 0x0},
+	{0x1114c0, 0x0},
+	{0x1114c1, 0x0},
+	{0x1115c0, 0x0},
+	{0x1115c1, 0x0},
+	{0x1116c0, 0x0},
+	{0x1116c1, 0x0},
+	{0x1117c0, 0x0},
+	{0x1117c1, 0x0},
+	{0x1118c0, 0x0},
+	{0x1118c1, 0x0},
+	{0x1110ae, 0x0},
+	{0x1110af, 0x0},
+	{0x190201, 0x0},
+	{0x190202, 0x0},
+	{0x190203, 0x0},
+	{0x190205, 0x0},
+	{0x190206, 0x0},
+	{0x190207, 0x0},
+	{0x190208, 0x0},
+	{0x120020, 0x0},
+	{0x200080, 0x0},
+	{0x201080, 0x0},
+	{0x202080, 0x0},
+	{0x210020, 0x0},
+	{0x210080, 0x0},
+	{0x210081, 0x0},
+	{0x2100d0, 0x0},
+	{0x2100d1, 0x0},
+	{0x21008c, 0x0},
+	{0x21008d, 0x0},
+	{0x210180, 0x0},
+	{0x210181, 0x0},
+	{0x2101d0, 0x0},
+	{0x2101d1, 0x0},
+	{0x21018c, 0x0},
+	{0x21018d, 0x0},
+	{0x2100c0, 0x0},
+	{0x2100c1, 0x0},
+	{0x2101c0, 0x0},
+	{0x2101c1, 0x0},
+	{0x2102c0, 0x0},
+	{0x2102c1, 0x0},
+	{0x2103c0, 0x0},
+	{0x2103c1, 0x0},
+	{0x2104c0, 0x0},
+	{0x2104c1, 0x0},
+	{0x2105c0, 0x0},
+	{0x2105c1, 0x0},
+	{0x2106c0, 0x0},
+	{0x2106c1, 0x0},
+	{0x2107c0, 0x0},
+	{0x2107c1, 0x0},
+	{0x2108c0, 0x0},
+	{0x2108c1, 0x0},
+	{0x2100ae, 0x0},
+	{0x2100af, 0x0},
+	{0x211020, 0x0},
+	{0x211080, 0x0},
+	{0x211081, 0x0},
+	{0x2110d0, 0x0},
+	{0x2110d1, 0x0},
+	{0x21108c, 0x0},
+	{0x21108d, 0x0},
+	{0x211180, 0x0},
+	{0x211181, 0x0},
+	{0x2111d0, 0x0},
+	{0x2111d1, 0x0},
+	{0x21118c, 0x0},
+	{0x21118d, 0x0},
+	{0x2110c0, 0x0},
+	{0x2110c1, 0x0},
+	{0x2111c0, 0x0},
+	{0x2111c1, 0x0},
+	{0x2112c0, 0x0},
+	{0x2112c1, 0x0},
+	{0x2113c0, 0x0},
+	{0x2113c1, 0x0},
+	{0x2114c0, 0x0},
+	{0x2114c1, 0x0},
+	{0x2115c0, 0x0},
+	{0x2115c1, 0x0},
+	{0x2116c0, 0x0},
+	{0x2116c1, 0x0},
+	{0x2117c0, 0x0},
+	{0x2117c1, 0x0},
+	{0x2118c0, 0x0},
+	{0x2118c1, 0x0},
+	{0x2110ae, 0x0},
+	{0x2110af, 0x0},
+	{0x290201, 0x0},
+	{0x290202, 0x0},
+	{0x290203, 0x0},
+	{0x290205, 0x0},
+	{0x290206, 0x0},
+	{0x290207, 0x0},
+	{0x290208, 0x0},
+	{0x220020, 0x0},
+	{0x20077, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
+	{0x400c0, 0x0},
+	{0x10040, 0x0},
+	{0x10140, 0x0},
+	{0x10240, 0x0},
+	{0x10340, 0x0},
+	{0x10440, 0x0},
+	{0x10540, 0x0},
+	{0x10640, 0x0},
+	{0x10740, 0x0},
+	{0x10840, 0x0},
+	{0x11040, 0x0},
+	{0x11140, 0x0},
+	{0x11240, 0x0},
+	{0x11340, 0x0},
+	{0x11440, 0x0},
+	{0x11540, 0x0},
+	{0x11640, 0x0},
+	{0x11740, 0x0},
+	{0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x640},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x52a4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x52a4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xa400},
+	{0x54033, 0x3352},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xa400},
+	{0x54039, 0x3352},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x320},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x3309},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x3309},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x270},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4800},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4800},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x3309},
+	{0x54034, 0x4600},
+	{0x54035, 0x11},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x3309},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x11},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x640},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54010, 0x2080},
+	{0x54012, 0x110},
+	{0x54019, 0x52a4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x52a4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xa400},
+	{0x54033, 0x3352},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xa400},
+	{0x54039, 0x3352},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x30},
+	{0x90051, 0x65a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x45a},
+	{0x90055, 0x9},
+	{0x90056, 0x0},
+	{0x90057, 0x448},
+	{0x90058, 0x109},
+	{0x90059, 0x40},
+	{0x9005a, 0x633},
+	{0x9005b, 0x179},
+	{0x9005c, 0x1},
+	{0x9005d, 0x618},
+	{0x9005e, 0x109},
+	{0x9005f, 0x40c0},
+	{0x90060, 0x633},
+	{0x90061, 0x149},
+	{0x90062, 0x8},
+	{0x90063, 0x4},
+	{0x90064, 0x48},
+	{0x90065, 0x4040},
+	{0x90066, 0x633},
+	{0x90067, 0x149},
+	{0x90068, 0x0},
+	{0x90069, 0x4},
+	{0x9006a, 0x48},
+	{0x9006b, 0x40},
+	{0x9006c, 0x633},
+	{0x9006d, 0x149},
+	{0x9006e, 0x0},
+	{0x9006f, 0x658},
+	{0x90070, 0x109},
+	{0x90071, 0x10},
+	{0x90072, 0x4},
+	{0x90073, 0x18},
+	{0x90074, 0x0},
+	{0x90075, 0x4},
+	{0x90076, 0x78},
+	{0x90077, 0x549},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0xd49},
+	{0x9007b, 0x633},
+	{0x9007c, 0x159},
+	{0x9007d, 0x94a},
+	{0x9007e, 0x633},
+	{0x9007f, 0x159},
+	{0x90080, 0x441},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x42},
+	{0x90084, 0x633},
+	{0x90085, 0x149},
+	{0x90086, 0x1},
+	{0x90087, 0x633},
+	{0x90088, 0x149},
+	{0x90089, 0x0},
+	{0x9008a, 0xe0},
+	{0x9008b, 0x109},
+	{0x9008c, 0xa},
+	{0x9008d, 0x10},
+	{0x9008e, 0x109},
+	{0x9008f, 0x9},
+	{0x90090, 0x3c0},
+	{0x90091, 0x149},
+	{0x90092, 0x9},
+	{0x90093, 0x3c0},
+	{0x90094, 0x159},
+	{0x90095, 0x18},
+	{0x90096, 0x10},
+	{0x90097, 0x109},
+	{0x90098, 0x0},
+	{0x90099, 0x3c0},
+	{0x9009a, 0x109},
+	{0x9009b, 0x18},
+	{0x9009c, 0x4},
+	{0x9009d, 0x48},
+	{0x9009e, 0x18},
+	{0x9009f, 0x4},
+	{0x900a0, 0x58},
+	{0x900a1, 0xb},
+	{0x900a2, 0x10},
+	{0x900a3, 0x109},
+	{0x900a4, 0x1},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x900a7, 0x5},
+	{0x900a8, 0x7c0},
+	{0x900a9, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x790},
+	{0x900ac, 0x11a},
+	{0x900ad, 0x8},
+	{0x900ae, 0x7aa},
+	{0x900af, 0x2a},
+	{0x900b0, 0x10},
+	{0x900b1, 0x7b2},
+	{0x900b2, 0x2a},
+	{0x900b3, 0x0},
+	{0x900b4, 0x7c8},
+	{0x900b5, 0x109},
+	{0x900b6, 0x10},
+	{0x900b7, 0x10},
+	{0x900b8, 0x109},
+	{0x900b9, 0x10},
+	{0x900ba, 0x2a8},
+	{0x900bb, 0x129},
+	{0x900bc, 0x8},
+	{0x900bd, 0x370},
+	{0x900be, 0x129},
+	{0x900bf, 0xa},
+	{0x900c0, 0x3c8},
+	{0x900c1, 0x1a9},
+	{0x900c2, 0xc},
+	{0x900c3, 0x408},
+	{0x900c4, 0x199},
+	{0x900c5, 0x14},
+	{0x900c6, 0x790},
+	{0x900c7, 0x11a},
+	{0x900c8, 0x8},
+	{0x900c9, 0x4},
+	{0x900ca, 0x18},
+	{0x900cb, 0xe},
+	{0x900cc, 0x408},
+	{0x900cd, 0x199},
+	{0x900ce, 0x8},
+	{0x900cf, 0x8568},
+	{0x900d0, 0x108},
+	{0x900d1, 0x18},
+	{0x900d2, 0x790},
+	{0x900d3, 0x16a},
+	{0x900d4, 0x8},
+	{0x900d5, 0x1d8},
+	{0x900d6, 0x169},
+	{0x900d7, 0x10},
+	{0x900d8, 0x8558},
+	{0x900d9, 0x168},
+	{0x900da, 0x1ff8},
+	{0x900db, 0x85a8},
+	{0x900dc, 0x1e8},
+	{0x900dd, 0x50},
+	{0x900de, 0x798},
+	{0x900df, 0x16a},
+	{0x900e0, 0x60},
+	{0x900e1, 0x7a0},
+	{0x900e2, 0x16a},
+	{0x900e3, 0x8},
+	{0x900e4, 0x8310},
+	{0x900e5, 0x168},
+	{0x900e6, 0x8},
+	{0x900e7, 0xa310},
+	{0x900e8, 0x168},
+	{0x900e9, 0xa},
+	{0x900ea, 0x408},
+	{0x900eb, 0x169},
+	{0x900ec, 0x6e},
+	{0x900ed, 0x0},
+	{0x900ee, 0x68},
+	{0x900ef, 0x0},
+	{0x900f0, 0x408},
+	{0x900f1, 0x169},
+	{0x900f2, 0x0},
+	{0x900f3, 0x8310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x0},
+	{0x900f6, 0xa310},
+	{0x900f7, 0x168},
+	{0x900f8, 0x1ff8},
+	{0x900f9, 0x85a8},
+	{0x900fa, 0x1e8},
+	{0x900fb, 0x68},
+	{0x900fc, 0x798},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x78},
+	{0x900ff, 0x7a0},
+	{0x90100, 0x16a},
+	{0x90101, 0x68},
+	{0x90102, 0x790},
+	{0x90103, 0x16a},
+	{0x90104, 0x8},
+	{0x90105, 0x8b10},
+	{0x90106, 0x168},
+	{0x90107, 0x8},
+	{0x90108, 0xab10},
+	{0x90109, 0x168},
+	{0x9010a, 0xa},
+	{0x9010b, 0x408},
+	{0x9010c, 0x169},
+	{0x9010d, 0x58},
+	{0x9010e, 0x0},
+	{0x9010f, 0x68},
+	{0x90110, 0x0},
+	{0x90111, 0x408},
+	{0x90112, 0x169},
+	{0x90113, 0x0},
+	{0x90114, 0x8b10},
+	{0x90115, 0x168},
+	{0x90116, 0x1},
+	{0x90117, 0xab10},
+	{0x90118, 0x168},
+	{0x90119, 0x0},
+	{0x9011a, 0x1d8},
+	{0x9011b, 0x169},
+	{0x9011c, 0x80},
+	{0x9011d, 0x790},
+	{0x9011e, 0x16a},
+	{0x9011f, 0x18},
+	{0x90120, 0x7aa},
+	{0x90121, 0x6a},
+	{0x90122, 0xa},
+	{0x90123, 0x0},
+	{0x90124, 0x1e9},
+	{0x90125, 0x8},
+	{0x90126, 0x8080},
+	{0x90127, 0x108},
+	{0x90128, 0xf},
+	{0x90129, 0x408},
+	{0x9012a, 0x169},
+	{0x9012b, 0xc},
+	{0x9012c, 0x0},
+	{0x9012d, 0x68},
+	{0x9012e, 0x9},
+	{0x9012f, 0x0},
+	{0x90130, 0x1a9},
+	{0x90131, 0x0},
+	{0x90132, 0x408},
+	{0x90133, 0x169},
+	{0x90134, 0x0},
+	{0x90135, 0x8080},
+	{0x90136, 0x108},
+	{0x90137, 0x8},
+	{0x90138, 0x7aa},
+	{0x90139, 0x6a},
+	{0x9013a, 0x0},
+	{0x9013b, 0x8568},
+	{0x9013c, 0x108},
+	{0x9013d, 0xb7},
+	{0x9013e, 0x790},
+	{0x9013f, 0x16a},
+	{0x90140, 0x1f},
+	{0x90141, 0x0},
+	{0x90142, 0x68},
+	{0x90143, 0x8},
+	{0x90144, 0x8558},
+	{0x90145, 0x168},
+	{0x90146, 0xf},
+	{0x90147, 0x408},
+	{0x90148, 0x169},
+	{0x90149, 0xd},
+	{0x9014a, 0x0},
+	{0x9014b, 0x68},
+	{0x9014c, 0x0},
+	{0x9014d, 0x408},
+	{0x9014e, 0x169},
+	{0x9014f, 0x0},
+	{0x90150, 0x8558},
+	{0x90151, 0x168},
+	{0x90152, 0x8},
+	{0x90153, 0x3c8},
+	{0x90154, 0x1a9},
+	{0x90155, 0x3},
+	{0x90156, 0x370},
+	{0x90157, 0x129},
+	{0x90158, 0x20},
+	{0x90159, 0x2aa},
+	{0x9015a, 0x9},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x104},
+	{0x90164, 0x8},
+	{0x90165, 0x448},
+	{0x90166, 0x109},
+	{0x90167, 0xf},
+	{0x90168, 0x7c0},
+	{0x90169, 0x109},
+	{0x9016a, 0x0},
+	{0x9016b, 0xe8},
+	{0x9016c, 0x109},
+	{0x9016d, 0x47},
+	{0x9016e, 0x630},
+	{0x9016f, 0x109},
+	{0x90170, 0x8},
+	{0x90171, 0x618},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0xe0},
+	{0x90175, 0x109},
+	{0x90176, 0x0},
+	{0x90177, 0x7c8},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0x8140},
+	{0x9017b, 0x10c},
+	{0x9017c, 0x0},
+	{0x9017d, 0x478},
+	{0x9017e, 0x109},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x0},
+	{0x90006, 0x8},
+	{0x90007, 0x7c8},
+	{0x90008, 0x109},
+	{0x90009, 0x0},
+	{0x9000a, 0x400},
+	{0x9000b, 0x106},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2b},
+	{0x90026, 0x69},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x200be, 0x3},
+	{0x2000b, 0x1c2},
+	{0x2000c, 0x64},
+	{0x2000d, 0x3e8},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xe1},
+	{0x12000c, 0x32},
+	{0x12000d, 0x1f4},
+	{0x12000e, 0x10},
+	{0x22000b, 0xb0},
+	{0x22000c, 0x27},
+	{0x22000d, 0x186},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x400f1, 0xe},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x0},
+	{0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 800mts 1D */
+		.drate = 800,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 1600mts 2D */
+		.drate = 1600,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1600mts = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 800, 625, },
+	.fsp_cfg = ddr_dram_fsp_cfg,
+	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c
new file mode 100644
index 00000000000..e0e6f5da3d6
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x4e300110, 0x44100001},
+	{0x4e300000, 0x8000ff},
+	{0x4e300008, 0x0},
+	{0x4e300080, 0x80000512},
+	{0x4e300084, 0x0},
+	{0x4e300114, 0x1002},
+	{0x4e300260, 0x80},
+	{0x4e300f04, 0x80},
+	{0x4e300800, 0x43b30002},
+	{0x4e300804, 0x1f1f1f1f},
+	{0x4e301000, 0x0},
+	{0x4e301240, 0x0},
+	{0x4e301244, 0x0},
+	{0x4e301248, 0x0},
+	{0x4e30124c, 0x0},
+	{0x4e301250, 0x0},
+	{0x4e301254, 0x0},
+	{0x4e301258, 0x0},
+	{0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+	{
+		{
+			{0x4e300100, 0x135C2110},
+			{0x4e300104, 0xF8990011},
+			{0x4e300108, 0x636E08CC},
+			{0x4e30010C, 0x0061E070},
+			{0x4e300124, 0x124E0000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x31D00000},
+			{0x4e300170, 0x8B0B0608},
+			{0x4e300250, 0x0000001A},
+			{0x4e300254, 0x00DC00DC},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+			{0x4e300300, 0x1633160D},
+			{0x4e300304, 0x00DC180C},
+			{0x4e300308, 0x0C3C0927},
+		},
+		{
+			{0x01, 0xC4},
+			{0x02, 0x24},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x010D1100},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0xBABAC068},
+			{0x4e30010C, 0x00610158},
+			{0x4e300124, 0x09270000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30400000},
+			{0x4e300170, 0x8A0A0508},
+			{0x4e300250, 0x0000000D},
+			{0x4e300254, 0x006A006A},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0xA4},
+			{0x02, 0x52},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x00061000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x6E62FA48},
+			{0x4e30010C, 0x0031010D},
+			{0x4e300124, 0x04C50000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30000000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000007},
+			{0x4e300254, 0x00340034},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		1,
+	},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x4},
+	{0x100a1, 0x5},
+	{0x100a2, 0x6},
+	{0x100a3, 0x7},
+	{0x100a4, 0x0},
+	{0x100a5, 0x1},
+	{0x100a6, 0x2},
+	{0x100a7, 0x3},
+	{0x110a0, 0x3},
+	{0x110a1, 0x2},
+	{0x110a2, 0x0},
+	{0x110a3, 0x1},
+	{0x110a4, 0x7},
+	{0x110a5, 0x6},
+	{0x110a6, 0x4},
+	{0x110a7, 0x5},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x200c5, 0xa},
+	{0x1200c5, 0x2},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x2007d, 0x212},
+	{0x2007c, 0x61},
+	{0x120024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x12007d, 0x212},
+	{0x12007c, 0x61},
+	{0x220024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x22007d, 0x212},
+	{0x22007c, 0x61},
+	{0x20056, 0x3},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
+	{0x1004d, 0x600},
+	{0x1014d, 0x600},
+	{0x1104d, 0x600},
+	{0x1114d, 0x600},
+	{0x11004d, 0x600},
+	{0x11014d, 0x600},
+	{0x11104d, 0x600},
+	{0x11114d, 0x600},
+	{0x21004d, 0x600},
+	{0x21014d, 0x600},
+	{0x21104d, 0x600},
+	{0x21114d, 0x600},
+	{0x10049, 0xe3f},
+	{0x10149, 0xe3f},
+	{0x11049, 0xe3f},
+	{0x11149, 0xe3f},
+	{0x110049, 0xe3f},
+	{0x110149, 0xe3f},
+	{0x111049, 0xe3f},
+	{0x111149, 0xe3f},
+	{0x210049, 0xe3f},
+	{0x210149, 0xe3f},
+	{0x211049, 0xe3f},
+	{0x211149, 0xe3f},
+	{0x43, 0x7f},
+	{0x1043, 0x7f},
+	{0x2043, 0x7f},
+	{0x20018, 0x1},
+	{0x20075, 0x4},
+	{0x20050, 0x11},
+	{0x2009b, 0x2},
+	{0x20008, 0x258},
+	{0x120008, 0x12c},
+	{0x220008, 0x9c},
+	{0x20088, 0x9},
+	{0x200b2, 0x10c},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x1200b2, 0x10c},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x2200b2, 0x10c},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x200fa, 0x2},
+	{0x1200fa, 0x2},
+	{0x2200fa, 0x2},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x600},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5655},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x1004a, 0x500},
+	{0x1104a, 0x500},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0x20021, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x41},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x1005f, 0x0},
+	{0x1015f, 0x0},
+	{0x1105f, 0x0},
+	{0x1115f, 0x0},
+	{0x11005f, 0x0},
+	{0x11015f, 0x0},
+	{0x11105f, 0x0},
+	{0x11115f, 0x0},
+	{0x21005f, 0x0},
+	{0x21015f, 0x0},
+	{0x21105f, 0x0},
+	{0x21115f, 0x0},
+	{0x55, 0x0},
+	{0x1055, 0x0},
+	{0x2055, 0x0},
+	{0x200c5, 0x0},
+	{0x1200c5, 0x0},
+	{0x2200c5, 0x0},
+	{0x2002e, 0x0},
+	{0x12002e, 0x0},
+	{0x22002e, 0x0},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x0},
+	{0x2003a, 0x0},
+	{0x2007d, 0x0},
+	{0x2007c, 0x0},
+	{0x120024, 0x0},
+	{0x12007d, 0x0},
+	{0x12007c, 0x0},
+	{0x220024, 0x0},
+	{0x22007d, 0x0},
+	{0x22007c, 0x0},
+	{0x20056, 0x0},
+	{0x120056, 0x0},
+	{0x220056, 0x0},
+	{0x1004d, 0x0},
+	{0x1014d, 0x0},
+	{0x1104d, 0x0},
+	{0x1114d, 0x0},
+	{0x11004d, 0x0},
+	{0x11014d, 0x0},
+	{0x11104d, 0x0},
+	{0x11114d, 0x0},
+	{0x21004d, 0x0},
+	{0x21014d, 0x0},
+	{0x21104d, 0x0},
+	{0x21114d, 0x0},
+	{0x10049, 0x0},
+	{0x10149, 0x0},
+	{0x11049, 0x0},
+	{0x11149, 0x0},
+	{0x110049, 0x0},
+	{0x110149, 0x0},
+	{0x111049, 0x0},
+	{0x111149, 0x0},
+	{0x210049, 0x0},
+	{0x210149, 0x0},
+	{0x211049, 0x0},
+	{0x211149, 0x0},
+	{0x43, 0x0},
+	{0x1043, 0x0},
+	{0x2043, 0x0},
+	{0x20018, 0x0},
+	{0x20075, 0x0},
+	{0x20050, 0x0},
+	{0x2009b, 0x0},
+	{0x20008, 0x0},
+	{0x120008, 0x0},
+	{0x220008, 0x0},
+	{0x20088, 0x0},
+	{0x200b2, 0x0},
+	{0x10043, 0x0},
+	{0x10143, 0x0},
+	{0x11043, 0x0},
+	{0x11143, 0x0},
+	{0x1200b2, 0x0},
+	{0x110043, 0x0},
+	{0x110143, 0x0},
+	{0x111043, 0x0},
+	{0x111143, 0x0},
+	{0x2200b2, 0x0},
+	{0x210043, 0x0},
+	{0x210143, 0x0},
+	{0x211043, 0x0},
+	{0x211143, 0x0},
+	{0x200fa, 0x0},
+	{0x1200fa, 0x0},
+	{0x2200fa, 0x0},
+	{0x20019, 0x0},
+	{0x120019, 0x0},
+	{0x220019, 0x0},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x0},
+	{0x200f3, 0x0},
+	{0x200f4, 0x0},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0x0},
+	{0x1004a, 0x0},
+	{0x1104a, 0x0},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0xd0000, 0x0},
+	{0x90000, 0x0},
+	{0x90001, 0x0},
+	{0x90002, 0x0},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x0},
+	{0x90029, 0x0},
+	{0x9002a, 0x0},
+	{0x9002b, 0x0},
+	{0x9002c, 0x0},
+	{0x9002d, 0x0},
+	{0x9002e, 0x0},
+	{0x9002f, 0x0},
+	{0x90030, 0x0},
+	{0x90031, 0x0},
+	{0x90032, 0x0},
+	{0x90033, 0x0},
+	{0x90034, 0x0},
+	{0x90035, 0x0},
+	{0x90036, 0x0},
+	{0x90037, 0x0},
+	{0x90038, 0x0},
+	{0x90039, 0x0},
+	{0x9003a, 0x0},
+	{0x9003b, 0x0},
+	{0x9003c, 0x0},
+	{0x9003d, 0x0},
+	{0x9003e, 0x0},
+	{0x9003f, 0x0},
+	{0x90040, 0x0},
+	{0x90041, 0x0},
+	{0x90042, 0x0},
+	{0x90043, 0x0},
+	{0x90044, 0x0},
+	{0x90045, 0x0},
+	{0x90046, 0x0},
+	{0x90047, 0x0},
+	{0x90048, 0x0},
+	{0x90049, 0x0},
+	{0x9004a, 0x0},
+	{0x9004b, 0x0},
+	{0x9004c, 0x0},
+	{0x9004d, 0x0},
+	{0x9004e, 0x0},
+	{0x9004f, 0x0},
+	{0x90050, 0x0},
+	{0x90051, 0x0},
+	{0x90052, 0x0},
+	{0x90053, 0x0},
+	{0x90054, 0x0},
+	{0x90055, 0x0},
+	{0x90056, 0x0},
+	{0x90057, 0x0},
+	{0x90058, 0x0},
+	{0x90059, 0x0},
+	{0x9005a, 0x0},
+	{0x9005b, 0x0},
+	{0x9005c, 0x0},
+	{0x9005d, 0x0},
+	{0x9005e, 0x0},
+	{0x9005f, 0x0},
+	{0x90060, 0x0},
+	{0x90061, 0x0},
+	{0x90062, 0x0},
+	{0x90063, 0x0},
+	{0x90064, 0x0},
+	{0x90065, 0x0},
+	{0x90066, 0x0},
+	{0x90067, 0x0},
+	{0x90068, 0x0},
+	{0x90069, 0x0},
+	{0x9006a, 0x0},
+	{0x9006b, 0x0},
+	{0x9006c, 0x0},
+	{0x9006d, 0x0},
+	{0x9006e, 0x0},
+	{0x9006f, 0x0},
+	{0x90070, 0x0},
+	{0x90071, 0x0},
+	{0x90072, 0x0},
+	{0x90073, 0x0},
+	{0x90074, 0x0},
+	{0x90075, 0x0},
+	{0x90076, 0x0},
+	{0x90077, 0x0},
+	{0x90078, 0x0},
+	{0x90079, 0x0},
+	{0x9007a, 0x0},
+	{0x9007b, 0x0},
+	{0x9007c, 0x0},
+	{0x9007d, 0x0},
+	{0x9007e, 0x0},
+	{0x9007f, 0x0},
+	{0x90080, 0x0},
+	{0x90081, 0x0},
+	{0x90082, 0x0},
+	{0x90083, 0x0},
+	{0x90084, 0x0},
+	{0x90085, 0x0},
+	{0x90086, 0x0},
+	{0x90087, 0x0},
+	{0x90088, 0x0},
+	{0x90089, 0x0},
+	{0x9008a, 0x0},
+	{0x9008b, 0x0},
+	{0x9008c, 0x0},
+	{0x9008d, 0x0},
+	{0x9008e, 0x0},
+	{0x9008f, 0x0},
+	{0x90090, 0x0},
+	{0x90091, 0x0},
+	{0x90092, 0x0},
+	{0x90093, 0x0},
+	{0x90094, 0x0},
+	{0x90095, 0x0},
+	{0x90096, 0x0},
+	{0x90097, 0x0},
+	{0x90098, 0x0},
+	{0x90099, 0x0},
+	{0x9009a, 0x0},
+	{0x9009b, 0x0},
+	{0x9009c, 0x0},
+	{0x9009d, 0x0},
+	{0x9009e, 0x0},
+	{0x9009f, 0x0},
+	{0x900a0, 0x0},
+	{0x900a1, 0x0},
+	{0x900a2, 0x0},
+	{0x900a3, 0x0},
+	{0x900a4, 0x0},
+	{0x900a5, 0x0},
+	{0x900a6, 0x0},
+	{0x900a7, 0x0},
+	{0x900a8, 0x0},
+	{0x900a9, 0x0},
+	{0x40000, 0x0},
+	{0x40020, 0x0},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x0},
+	{0x40021, 0x0},
+	{0x40041, 0x0},
+	{0x40061, 0x0},
+	{0x40002, 0x0},
+	{0x40022, 0x0},
+	{0x40042, 0x0},
+	{0x40062, 0x0},
+	{0x40003, 0x0},
+	{0x40023, 0x0},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x0},
+	{0x40024, 0x0},
+	{0x40044, 0x0},
+	{0x40064, 0x0},
+	{0x40005, 0x0},
+	{0x40025, 0x0},
+	{0x40045, 0x0},
+	{0x40065, 0x0},
+	{0x40006, 0x0},
+	{0x40026, 0x0},
+	{0x40046, 0x0},
+	{0x40066, 0x0},
+	{0x40007, 0x0},
+	{0x40027, 0x0},
+	{0x40047, 0x0},
+	{0x40067, 0x0},
+	{0x40008, 0x0},
+	{0x40028, 0x0},
+	{0x40048, 0x0},
+	{0x40068, 0x0},
+	{0x40009, 0x0},
+	{0x40029, 0x0},
+	{0x40049, 0x0},
+	{0x40069, 0x0},
+	{0x4000a, 0x0},
+	{0x4002a, 0x0},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x0},
+	{0x4002b, 0x0},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x0},
+	{0x4002c, 0x0},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0x0},
+	{0x4002d, 0x0},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x0},
+	{0x4002e, 0x0},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x0},
+	{0x4002f, 0x0},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x0},
+	{0x40030, 0x0},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x0},
+	{0x40031, 0x0},
+	{0x40051, 0x0},
+	{0x40071, 0x0},
+	{0x40012, 0x0},
+	{0x40032, 0x0},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x0},
+	{0x40033, 0x0},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x0},
+	{0x40034, 0x0},
+	{0x40054, 0x0},
+	{0x40074, 0x0},
+	{0x40015, 0x0},
+	{0x40035, 0x0},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x0},
+	{0x40036, 0x0},
+	{0x40056, 0x0},
+	{0x40076, 0x0},
+	{0x40017, 0x0},
+	{0x40037, 0x0},
+	{0x40057, 0x0},
+	{0x40077, 0x0},
+	{0x40018, 0x0},
+	{0x40038, 0x0},
+	{0x40058, 0x0},
+	{0x40078, 0x0},
+	{0x40019, 0x0},
+	{0x40039, 0x0},
+	{0x40059, 0x0},
+	{0x40079, 0x0},
+	{0x4001a, 0x0},
+	{0x4003a, 0x0},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x0},
+	{0x900ac, 0x0},
+	{0x900ad, 0x0},
+	{0x900ae, 0x0},
+	{0x900af, 0x0},
+	{0x900b0, 0x0},
+	{0x900b1, 0x0},
+	{0x900b2, 0x0},
+	{0x900b3, 0x0},
+	{0x900b4, 0x0},
+	{0x900b5, 0x0},
+	{0x900b6, 0x0},
+	{0x900b7, 0x0},
+	{0x900b8, 0x0},
+	{0x900b9, 0x0},
+	{0x900ba, 0x0},
+	{0x900bb, 0x0},
+	{0x900bc, 0x0},
+	{0x900bd, 0x0},
+	{0x900be, 0x0},
+	{0x900bf, 0x0},
+	{0x900c0, 0x0},
+	{0x900c1, 0x0},
+	{0x900c2, 0x0},
+	{0x900c3, 0x0},
+	{0x900c4, 0x0},
+	{0x900c5, 0x0},
+	{0x900c6, 0x0},
+	{0x900c7, 0x0},
+	{0x900c8, 0x0},
+	{0x900c9, 0x0},
+	{0x900ca, 0x0},
+	{0x900cb, 0x0},
+	{0x900cc, 0x0},
+	{0x900cd, 0x0},
+	{0x900ce, 0x0},
+	{0x900cf, 0x0},
+	{0x900d0, 0x0},
+	{0x900d1, 0x0},
+	{0x900d2, 0x0},
+	{0x900d3, 0x0},
+	{0x900d4, 0x0},
+	{0x900d5, 0x0},
+	{0x900d6, 0x0},
+	{0x900d7, 0x0},
+	{0x900d8, 0x0},
+	{0x900d9, 0x0},
+	{0x900da, 0x0},
+	{0x900db, 0x0},
+	{0x900dc, 0x0},
+	{0x900dd, 0x0},
+	{0x900de, 0x0},
+	{0x900df, 0x0},
+	{0x900e0, 0x0},
+	{0x900e1, 0x0},
+	{0x900e2, 0x0},
+	{0x900e3, 0x0},
+	{0x900e4, 0x0},
+	{0x900e5, 0x0},
+	{0x900e6, 0x0},
+	{0x900e7, 0x0},
+	{0x900e8, 0x0},
+	{0x900e9, 0x0},
+	{0x900ea, 0x0},
+	{0x900eb, 0x0},
+	{0x900ec, 0x0},
+	{0x900ed, 0x0},
+	{0x900ee, 0x0},
+	{0x900ef, 0x0},
+	{0x900f0, 0x0},
+	{0x900f1, 0x0},
+	{0x900f2, 0x0},
+	{0x900f3, 0x0},
+	{0x900f4, 0x0},
+	{0x900f5, 0x0},
+	{0x900f6, 0x0},
+	{0x900f7, 0x0},
+	{0x900f8, 0x0},
+	{0x900f9, 0x0},
+	{0x900fa, 0x0},
+	{0x900fb, 0x0},
+	{0x900fc, 0x0},
+	{0x900fd, 0x0},
+	{0x900fe, 0x0},
+	{0x900ff, 0x0},
+	{0x90100, 0x0},
+	{0x90101, 0x0},
+	{0x90102, 0x0},
+	{0x90103, 0x0},
+	{0x90104, 0x0},
+	{0x90105, 0x0},
+	{0x90106, 0x0},
+	{0x90107, 0x0},
+	{0x90108, 0x0},
+	{0x90109, 0x0},
+	{0x9010a, 0x0},
+	{0x9010b, 0x0},
+	{0x9010c, 0x0},
+	{0x9010d, 0x0},
+	{0x9010e, 0x0},
+	{0x9010f, 0x0},
+	{0x90110, 0x0},
+	{0x90111, 0x0},
+	{0x90112, 0x0},
+	{0x90113, 0x0},
+	{0x90114, 0x0},
+	{0x90115, 0x0},
+	{0x90116, 0x0},
+	{0x90117, 0x0},
+	{0x90118, 0x0},
+	{0x90119, 0x0},
+	{0x9011a, 0x0},
+	{0x9011b, 0x0},
+	{0x9011c, 0x0},
+	{0x9011d, 0x0},
+	{0x9011e, 0x0},
+	{0x9011f, 0x0},
+	{0x90120, 0x0},
+	{0x90121, 0x0},
+	{0x90122, 0x0},
+	{0x90123, 0x0},
+	{0x90124, 0x0},
+	{0x90125, 0x0},
+	{0x90126, 0x0},
+	{0x90127, 0x0},
+	{0x90128, 0x0},
+	{0x90129, 0x0},
+	{0x9012a, 0x0},
+	{0x9012b, 0x0},
+	{0x9012c, 0x0},
+	{0x9012d, 0x0},
+	{0x9012e, 0x0},
+	{0x9012f, 0x0},
+	{0x90130, 0x0},
+	{0x90131, 0x0},
+	{0x90132, 0x0},
+	{0x90133, 0x0},
+	{0x90134, 0x0},
+	{0x90135, 0x0},
+	{0x90136, 0x0},
+	{0x90137, 0x0},
+	{0x90138, 0x0},
+	{0x90139, 0x0},
+	{0x9013a, 0x0},
+	{0x9013b, 0x0},
+	{0x9013c, 0x0},
+	{0x9013d, 0x0},
+	{0x9013e, 0x0},
+	{0x9013f, 0x0},
+	{0x90140, 0x0},
+	{0x90141, 0x0},
+	{0x90142, 0x0},
+	{0x90143, 0x0},
+	{0x90144, 0x0},
+	{0x90145, 0x0},
+	{0x90146, 0x0},
+	{0x90147, 0x0},
+	{0x90148, 0x0},
+	{0x90149, 0x0},
+	{0x9014a, 0x0},
+	{0x9014b, 0x0},
+	{0x9014c, 0x0},
+	{0x9014d, 0x0},
+	{0x9014e, 0x0},
+	{0x9014f, 0x0},
+	{0x90150, 0x0},
+	{0x90151, 0x0},
+	{0x90152, 0x0},
+	{0x90153, 0x0},
+	{0x90154, 0x0},
+	{0x90155, 0x0},
+	{0x90156, 0x0},
+	{0x90157, 0x0},
+	{0x90158, 0x0},
+	{0x90159, 0x0},
+	{0x9015a, 0x0},
+	{0x9015b, 0x0},
+	{0x9015c, 0x0},
+	{0x9015d, 0x0},
+	{0x9015e, 0x0},
+	{0x9015f, 0x0},
+	{0x90160, 0x0},
+	{0x90161, 0x0},
+	{0x90162, 0x0},
+	{0x90163, 0x0},
+	{0x90164, 0x0},
+	{0x90165, 0x0},
+	{0x90166, 0x0},
+	{0x90167, 0x0},
+	{0x90168, 0x0},
+	{0x90169, 0x0},
+	{0x9016a, 0x0},
+	{0x9016b, 0x0},
+	{0x9016c, 0x0},
+	{0x9016d, 0x0},
+	{0x9016e, 0x0},
+	{0x9016f, 0x0},
+	{0x90170, 0x0},
+	{0x90171, 0x0},
+	{0x90172, 0x0},
+	{0x90173, 0x0},
+	{0x90174, 0x0},
+	{0x90175, 0x0},
+	{0x90176, 0x0},
+	{0x90177, 0x0},
+	{0x90178, 0x0},
+	{0x90179, 0x0},
+	{0x9017a, 0x0},
+	{0x9017b, 0x0},
+	{0x9017c, 0x0},
+	{0x9017d, 0x0},
+	{0x9017e, 0x0},
+	{0x9017f, 0x0},
+	{0x90180, 0x0},
+	{0x90181, 0x0},
+	{0x90182, 0x0},
+	{0x90183, 0x0},
+	{0x90184, 0x0},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x0},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x0},
+	{0x90017, 0x0},
+	{0x9001f, 0x0},
+	{0x90026, 0x0},
+	{0x400d0, 0x0},
+	{0x400d1, 0x0},
+	{0x400d2, 0x0},
+	{0x400d3, 0x0},
+	{0x400d4, 0x0},
+	{0x400d5, 0x0},
+	{0x400d6, 0x0},
+	{0x400d7, 0x0},
+	{0x200be, 0x0},
+	{0x2000b, 0x0},
+	{0x2000c, 0x0},
+	{0x2000d, 0x0},
+	{0x2000e, 0x0},
+	{0x12000b, 0x0},
+	{0x12000c, 0x0},
+	{0x12000d, 0x0},
+	{0x12000e, 0x0},
+	{0x22000b, 0x0},
+	{0x22000c, 0x0},
+	{0x22000d, 0x0},
+	{0x22000e, 0x0},
+	{0x9000c, 0x0},
+	{0x9000d, 0x0},
+	{0x9000e, 0x0},
+	{0x9000f, 0x0},
+	{0x90010, 0x0},
+	{0x90011, 0x0},
+	{0x90012, 0x0},
+	{0x90013, 0x0},
+	{0x20010, 0x0},
+	{0x20011, 0x0},
+	{0x120010, 0x0},
+	{0x120011, 0x0},
+	{0x40080, 0x0},
+	{0x40081, 0x0},
+	{0x40082, 0x0},
+	{0x40083, 0x0},
+	{0x40084, 0x0},
+	{0x40085, 0x0},
+	{0x140080, 0x0},
+	{0x140081, 0x0},
+	{0x140082, 0x0},
+	{0x140083, 0x0},
+	{0x140084, 0x0},
+	{0x140085, 0x0},
+	{0x240080, 0x0},
+	{0x240081, 0x0},
+	{0x240082, 0x0},
+	{0x240083, 0x0},
+	{0x240084, 0x0},
+	{0x240085, 0x0},
+	{0x400fd, 0x0},
+	{0x400f1, 0x0},
+	{0x10011, 0x0},
+	{0x10012, 0x0},
+	{0x10013, 0x0},
+	{0x10018, 0x0},
+	{0x10002, 0x0},
+	{0x100b2, 0x0},
+	{0x101b4, 0x0},
+	{0x102b4, 0x0},
+	{0x103b4, 0x0},
+	{0x104b4, 0x0},
+	{0x105b4, 0x0},
+	{0x106b4, 0x0},
+	{0x107b4, 0x0},
+	{0x108b4, 0x0},
+	{0x11011, 0x0},
+	{0x11012, 0x0},
+	{0x11013, 0x0},
+	{0x11018, 0x0},
+	{0x11002, 0x0},
+	{0x110b2, 0x0},
+	{0x111b4, 0x0},
+	{0x112b4, 0x0},
+	{0x113b4, 0x0},
+	{0x114b4, 0x0},
+	{0x115b4, 0x0},
+	{0x116b4, 0x0},
+	{0x117b4, 0x0},
+	{0x118b4, 0x0},
+	{0x20089, 0x0},
+	{0xc0080, 0x0},
+	{0x200cb, 0x0},
+	{0x10068, 0x0},
+	{0x10069, 0x0},
+	{0x10168, 0x0},
+	{0x10169, 0x0},
+	{0x10268, 0x0},
+	{0x10269, 0x0},
+	{0x10368, 0x0},
+	{0x10369, 0x0},
+	{0x10468, 0x0},
+	{0x10469, 0x0},
+	{0x10568, 0x0},
+	{0x10569, 0x0},
+	{0x10668, 0x0},
+	{0x10669, 0x0},
+	{0x10768, 0x0},
+	{0x10769, 0x0},
+	{0x10868, 0x0},
+	{0x10869, 0x0},
+	{0x100aa, 0x0},
+	{0x10062, 0x0},
+	{0x10001, 0x0},
+	{0x100a0, 0x0},
+	{0x100a1, 0x0},
+	{0x100a2, 0x0},
+	{0x100a3, 0x0},
+	{0x100a4, 0x0},
+	{0x100a5, 0x0},
+	{0x100a6, 0x0},
+	{0x100a7, 0x0},
+	{0x11068, 0x0},
+	{0x11069, 0x0},
+	{0x11168, 0x0},
+	{0x11169, 0x0},
+	{0x11268, 0x0},
+	{0x11269, 0x0},
+	{0x11368, 0x0},
+	{0x11369, 0x0},
+	{0x11468, 0x0},
+	{0x11469, 0x0},
+	{0x11568, 0x0},
+	{0x11569, 0x0},
+	{0x11668, 0x0},
+	{0x11669, 0x0},
+	{0x11768, 0x0},
+	{0x11769, 0x0},
+	{0x11868, 0x0},
+	{0x11869, 0x0},
+	{0x110aa, 0x0},
+	{0x11062, 0x0},
+	{0x11001, 0x0},
+	{0x110a0, 0x0},
+	{0x110a1, 0x0},
+	{0x110a2, 0x0},
+	{0x110a3, 0x0},
+	{0x110a4, 0x0},
+	{0x110a5, 0x0},
+	{0x110a6, 0x0},
+	{0x110a7, 0x0},
+	{0x80, 0x0},
+	{0x1080, 0x0},
+	{0x2080, 0x0},
+	{0x10020, 0x0},
+	{0x10080, 0x0},
+	{0x10081, 0x0},
+	{0x100d0, 0x0},
+	{0x100d1, 0x0},
+	{0x1008c, 0x0},
+	{0x1008d, 0x0},
+	{0x10180, 0x0},
+	{0x10181, 0x0},
+	{0x101d0, 0x0},
+	{0x101d1, 0x0},
+	{0x1018c, 0x0},
+	{0x1018d, 0x0},
+	{0x100c0, 0x0},
+	{0x100c1, 0x0},
+	{0x101c0, 0x0},
+	{0x101c1, 0x0},
+	{0x102c0, 0x0},
+	{0x102c1, 0x0},
+	{0x103c0, 0x0},
+	{0x103c1, 0x0},
+	{0x104c0, 0x0},
+	{0x104c1, 0x0},
+	{0x105c0, 0x0},
+	{0x105c1, 0x0},
+	{0x106c0, 0x0},
+	{0x106c1, 0x0},
+	{0x107c0, 0x0},
+	{0x107c1, 0x0},
+	{0x108c0, 0x0},
+	{0x108c1, 0x0},
+	{0x100ae, 0x0},
+	{0x100af, 0x0},
+	{0x11020, 0x0},
+	{0x11080, 0x0},
+	{0x11081, 0x0},
+	{0x110d0, 0x0},
+	{0x110d1, 0x0},
+	{0x1108c, 0x0},
+	{0x1108d, 0x0},
+	{0x11180, 0x0},
+	{0x11181, 0x0},
+	{0x111d0, 0x0},
+	{0x111d1, 0x0},
+	{0x1118c, 0x0},
+	{0x1118d, 0x0},
+	{0x110c0, 0x0},
+	{0x110c1, 0x0},
+	{0x111c0, 0x0},
+	{0x111c1, 0x0},
+	{0x112c0, 0x0},
+	{0x112c1, 0x0},
+	{0x113c0, 0x0},
+	{0x113c1, 0x0},
+	{0x114c0, 0x0},
+	{0x114c1, 0x0},
+	{0x115c0, 0x0},
+	{0x115c1, 0x0},
+	{0x116c0, 0x0},
+	{0x116c1, 0x0},
+	{0x117c0, 0x0},
+	{0x117c1, 0x0},
+	{0x118c0, 0x0},
+	{0x118c1, 0x0},
+	{0x110ae, 0x0},
+	{0x110af, 0x0},
+	{0x90201, 0x0},
+	{0x90202, 0x0},
+	{0x90203, 0x0},
+	{0x90205, 0x0},
+	{0x90206, 0x0},
+	{0x90207, 0x0},
+	{0x90208, 0x0},
+	{0x20020, 0x0},
+	{0x100080, 0x0},
+	{0x101080, 0x0},
+	{0x102080, 0x0},
+	{0x110020, 0x0},
+	{0x110080, 0x0},
+	{0x110081, 0x0},
+	{0x1100d0, 0x0},
+	{0x1100d1, 0x0},
+	{0x11008c, 0x0},
+	{0x11008d, 0x0},
+	{0x110180, 0x0},
+	{0x110181, 0x0},
+	{0x1101d0, 0x0},
+	{0x1101d1, 0x0},
+	{0x11018c, 0x0},
+	{0x11018d, 0x0},
+	{0x1100c0, 0x0},
+	{0x1100c1, 0x0},
+	{0x1101c0, 0x0},
+	{0x1101c1, 0x0},
+	{0x1102c0, 0x0},
+	{0x1102c1, 0x0},
+	{0x1103c0, 0x0},
+	{0x1103c1, 0x0},
+	{0x1104c0, 0x0},
+	{0x1104c1, 0x0},
+	{0x1105c0, 0x0},
+	{0x1105c1, 0x0},
+	{0x1106c0, 0x0},
+	{0x1106c1, 0x0},
+	{0x1107c0, 0x0},
+	{0x1107c1, 0x0},
+	{0x1108c0, 0x0},
+	{0x1108c1, 0x0},
+	{0x1100ae, 0x0},
+	{0x1100af, 0x0},
+	{0x111020, 0x0},
+	{0x111080, 0x0},
+	{0x111081, 0x0},
+	{0x1110d0, 0x0},
+	{0x1110d1, 0x0},
+	{0x11108c, 0x0},
+	{0x11108d, 0x0},
+	{0x111180, 0x0},
+	{0x111181, 0x0},
+	{0x1111d0, 0x0},
+	{0x1111d1, 0x0},
+	{0x11118c, 0x0},
+	{0x11118d, 0x0},
+	{0x1110c0, 0x0},
+	{0x1110c1, 0x0},
+	{0x1111c0, 0x0},
+	{0x1111c1, 0x0},
+	{0x1112c0, 0x0},
+	{0x1112c1, 0x0},
+	{0x1113c0, 0x0},
+	{0x1113c1, 0x0},
+	{0x1114c0, 0x0},
+	{0x1114c1, 0x0},
+	{0x1115c0, 0x0},
+	{0x1115c1, 0x0},
+	{0x1116c0, 0x0},
+	{0x1116c1, 0x0},
+	{0x1117c0, 0x0},
+	{0x1117c1, 0x0},
+	{0x1118c0, 0x0},
+	{0x1118c1, 0x0},
+	{0x1110ae, 0x0},
+	{0x1110af, 0x0},
+	{0x190201, 0x0},
+	{0x190202, 0x0},
+	{0x190203, 0x0},
+	{0x190205, 0x0},
+	{0x190206, 0x0},
+	{0x190207, 0x0},
+	{0x190208, 0x0},
+	{0x120020, 0x0},
+	{0x200080, 0x0},
+	{0x201080, 0x0},
+	{0x202080, 0x0},
+	{0x210020, 0x0},
+	{0x210080, 0x0},
+	{0x210081, 0x0},
+	{0x2100d0, 0x0},
+	{0x2100d1, 0x0},
+	{0x21008c, 0x0},
+	{0x21008d, 0x0},
+	{0x210180, 0x0},
+	{0x210181, 0x0},
+	{0x2101d0, 0x0},
+	{0x2101d1, 0x0},
+	{0x21018c, 0x0},
+	{0x21018d, 0x0},
+	{0x2100c0, 0x0},
+	{0x2100c1, 0x0},
+	{0x2101c0, 0x0},
+	{0x2101c1, 0x0},
+	{0x2102c0, 0x0},
+	{0x2102c1, 0x0},
+	{0x2103c0, 0x0},
+	{0x2103c1, 0x0},
+	{0x2104c0, 0x0},
+	{0x2104c1, 0x0},
+	{0x2105c0, 0x0},
+	{0x2105c1, 0x0},
+	{0x2106c0, 0x0},
+	{0x2106c1, 0x0},
+	{0x2107c0, 0x0},
+	{0x2107c1, 0x0},
+	{0x2108c0, 0x0},
+	{0x2108c1, 0x0},
+	{0x2100ae, 0x0},
+	{0x2100af, 0x0},
+	{0x211020, 0x0},
+	{0x211080, 0x0},
+	{0x211081, 0x0},
+	{0x2110d0, 0x0},
+	{0x2110d1, 0x0},
+	{0x21108c, 0x0},
+	{0x21108d, 0x0},
+	{0x211180, 0x0},
+	{0x211181, 0x0},
+	{0x2111d0, 0x0},
+	{0x2111d1, 0x0},
+	{0x21118c, 0x0},
+	{0x21118d, 0x0},
+	{0x2110c0, 0x0},
+	{0x2110c1, 0x0},
+	{0x2111c0, 0x0},
+	{0x2111c1, 0x0},
+	{0x2112c0, 0x0},
+	{0x2112c1, 0x0},
+	{0x2113c0, 0x0},
+	{0x2113c1, 0x0},
+	{0x2114c0, 0x0},
+	{0x2114c1, 0x0},
+	{0x2115c0, 0x0},
+	{0x2115c1, 0x0},
+	{0x2116c0, 0x0},
+	{0x2116c1, 0x0},
+	{0x2117c0, 0x0},
+	{0x2117c1, 0x0},
+	{0x2118c0, 0x0},
+	{0x2118c1, 0x0},
+	{0x2110ae, 0x0},
+	{0x2110af, 0x0},
+	{0x290201, 0x0},
+	{0x290202, 0x0},
+	{0x290203, 0x0},
+	{0x290205, 0x0},
+	{0x290206, 0x0},
+	{0x290207, 0x0},
+	{0x290208, 0x0},
+	{0x220020, 0x0},
+	{0x20077, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
+	{0x400c0, 0x0},
+	{0x10040, 0x0},
+	{0x10140, 0x0},
+	{0x10240, 0x0},
+	{0x10340, 0x0},
+	{0x10440, 0x0},
+	{0x10540, 0x0},
+	{0x10640, 0x0},
+	{0x10740, 0x0},
+	{0x10840, 0x0},
+	{0x11040, 0x0},
+	{0x11140, 0x0},
+	{0x11240, 0x0},
+	{0x11340, 0x0},
+	{0x11440, 0x0},
+	{0x11540, 0x0},
+	{0x11640, 0x0},
+	{0x11740, 0x0},
+	{0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x960},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x24c4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x24c4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xc400},
+	{0x54033, 0x3324},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xc400},
+	{0x54039, 0x3324},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x4b0},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x52a4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x52a4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xa400},
+	{0x54033, 0x3352},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xa400},
+	{0x54039, 0x3352},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x270},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4800},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4800},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x3309},
+	{0x54034, 0x4600},
+	{0x54035, 0x11},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x3309},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x11},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x960},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54010, 0x2080},
+	{0x54012, 0x110},
+	{0x54019, 0x24c4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x24c4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xc400},
+	{0x54033, 0x3324},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xc400},
+	{0x54039, 0x3324},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x30},
+	{0x90051, 0x65a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x45a},
+	{0x90055, 0x9},
+	{0x90056, 0x0},
+	{0x90057, 0x448},
+	{0x90058, 0x109},
+	{0x90059, 0x40},
+	{0x9005a, 0x633},
+	{0x9005b, 0x179},
+	{0x9005c, 0x1},
+	{0x9005d, 0x618},
+	{0x9005e, 0x109},
+	{0x9005f, 0x40c0},
+	{0x90060, 0x633},
+	{0x90061, 0x149},
+	{0x90062, 0x8},
+	{0x90063, 0x4},
+	{0x90064, 0x48},
+	{0x90065, 0x4040},
+	{0x90066, 0x633},
+	{0x90067, 0x149},
+	{0x90068, 0x0},
+	{0x90069, 0x4},
+	{0x9006a, 0x48},
+	{0x9006b, 0x40},
+	{0x9006c, 0x633},
+	{0x9006d, 0x149},
+	{0x9006e, 0x0},
+	{0x9006f, 0x658},
+	{0x90070, 0x109},
+	{0x90071, 0x10},
+	{0x90072, 0x4},
+	{0x90073, 0x18},
+	{0x90074, 0x0},
+	{0x90075, 0x4},
+	{0x90076, 0x78},
+	{0x90077, 0x549},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0xd49},
+	{0x9007b, 0x633},
+	{0x9007c, 0x159},
+	{0x9007d, 0x94a},
+	{0x9007e, 0x633},
+	{0x9007f, 0x159},
+	{0x90080, 0x441},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x42},
+	{0x90084, 0x633},
+	{0x90085, 0x149},
+	{0x90086, 0x1},
+	{0x90087, 0x633},
+	{0x90088, 0x149},
+	{0x90089, 0x0},
+	{0x9008a, 0xe0},
+	{0x9008b, 0x109},
+	{0x9008c, 0xa},
+	{0x9008d, 0x10},
+	{0x9008e, 0x109},
+	{0x9008f, 0x9},
+	{0x90090, 0x3c0},
+	{0x90091, 0x149},
+	{0x90092, 0x9},
+	{0x90093, 0x3c0},
+	{0x90094, 0x159},
+	{0x90095, 0x18},
+	{0x90096, 0x10},
+	{0x90097, 0x109},
+	{0x90098, 0x0},
+	{0x90099, 0x3c0},
+	{0x9009a, 0x109},
+	{0x9009b, 0x18},
+	{0x9009c, 0x4},
+	{0x9009d, 0x48},
+	{0x9009e, 0x18},
+	{0x9009f, 0x4},
+	{0x900a0, 0x58},
+	{0x900a1, 0xb},
+	{0x900a2, 0x10},
+	{0x900a3, 0x109},
+	{0x900a4, 0x1},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x900a7, 0x5},
+	{0x900a8, 0x7c0},
+	{0x900a9, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x790},
+	{0x900ac, 0x11a},
+	{0x900ad, 0x8},
+	{0x900ae, 0x7aa},
+	{0x900af, 0x2a},
+	{0x900b0, 0x10},
+	{0x900b1, 0x7b2},
+	{0x900b2, 0x2a},
+	{0x900b3, 0x0},
+	{0x900b4, 0x7c8},
+	{0x900b5, 0x109},
+	{0x900b6, 0x10},
+	{0x900b7, 0x10},
+	{0x900b8, 0x109},
+	{0x900b9, 0x10},
+	{0x900ba, 0x2a8},
+	{0x900bb, 0x129},
+	{0x900bc, 0x8},
+	{0x900bd, 0x370},
+	{0x900be, 0x129},
+	{0x900bf, 0xa},
+	{0x900c0, 0x3c8},
+	{0x900c1, 0x1a9},
+	{0x900c2, 0xc},
+	{0x900c3, 0x408},
+	{0x900c4, 0x199},
+	{0x900c5, 0x14},
+	{0x900c6, 0x790},
+	{0x900c7, 0x11a},
+	{0x900c8, 0x8},
+	{0x900c9, 0x4},
+	{0x900ca, 0x18},
+	{0x900cb, 0xe},
+	{0x900cc, 0x408},
+	{0x900cd, 0x199},
+	{0x900ce, 0x8},
+	{0x900cf, 0x8568},
+	{0x900d0, 0x108},
+	{0x900d1, 0x18},
+	{0x900d2, 0x790},
+	{0x900d3, 0x16a},
+	{0x900d4, 0x8},
+	{0x900d5, 0x1d8},
+	{0x900d6, 0x169},
+	{0x900d7, 0x10},
+	{0x900d8, 0x8558},
+	{0x900d9, 0x168},
+	{0x900da, 0x1ff8},
+	{0x900db, 0x85a8},
+	{0x900dc, 0x1e8},
+	{0x900dd, 0x50},
+	{0x900de, 0x798},
+	{0x900df, 0x16a},
+	{0x900e0, 0x60},
+	{0x900e1, 0x7a0},
+	{0x900e2, 0x16a},
+	{0x900e3, 0x8},
+	{0x900e4, 0x8310},
+	{0x900e5, 0x168},
+	{0x900e6, 0x8},
+	{0x900e7, 0xa310},
+	{0x900e8, 0x168},
+	{0x900e9, 0xa},
+	{0x900ea, 0x408},
+	{0x900eb, 0x169},
+	{0x900ec, 0x6e},
+	{0x900ed, 0x0},
+	{0x900ee, 0x68},
+	{0x900ef, 0x0},
+	{0x900f0, 0x408},
+	{0x900f1, 0x169},
+	{0x900f2, 0x0},
+	{0x900f3, 0x8310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x0},
+	{0x900f6, 0xa310},
+	{0x900f7, 0x168},
+	{0x900f8, 0x1ff8},
+	{0x900f9, 0x85a8},
+	{0x900fa, 0x1e8},
+	{0x900fb, 0x68},
+	{0x900fc, 0x798},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x78},
+	{0x900ff, 0x7a0},
+	{0x90100, 0x16a},
+	{0x90101, 0x68},
+	{0x90102, 0x790},
+	{0x90103, 0x16a},
+	{0x90104, 0x8},
+	{0x90105, 0x8b10},
+	{0x90106, 0x168},
+	{0x90107, 0x8},
+	{0x90108, 0xab10},
+	{0x90109, 0x168},
+	{0x9010a, 0xa},
+	{0x9010b, 0x408},
+	{0x9010c, 0x169},
+	{0x9010d, 0x58},
+	{0x9010e, 0x0},
+	{0x9010f, 0x68},
+	{0x90110, 0x0},
+	{0x90111, 0x408},
+	{0x90112, 0x169},
+	{0x90113, 0x0},
+	{0x90114, 0x8b10},
+	{0x90115, 0x168},
+	{0x90116, 0x1},
+	{0x90117, 0xab10},
+	{0x90118, 0x168},
+	{0x90119, 0x0},
+	{0x9011a, 0x1d8},
+	{0x9011b, 0x169},
+	{0x9011c, 0x80},
+	{0x9011d, 0x790},
+	{0x9011e, 0x16a},
+	{0x9011f, 0x18},
+	{0x90120, 0x7aa},
+	{0x90121, 0x6a},
+	{0x90122, 0xa},
+	{0x90123, 0x0},
+	{0x90124, 0x1e9},
+	{0x90125, 0x8},
+	{0x90126, 0x8080},
+	{0x90127, 0x108},
+	{0x90128, 0xf},
+	{0x90129, 0x408},
+	{0x9012a, 0x169},
+	{0x9012b, 0xc},
+	{0x9012c, 0x0},
+	{0x9012d, 0x68},
+	{0x9012e, 0x9},
+	{0x9012f, 0x0},
+	{0x90130, 0x1a9},
+	{0x90131, 0x0},
+	{0x90132, 0x408},
+	{0x90133, 0x169},
+	{0x90134, 0x0},
+	{0x90135, 0x8080},
+	{0x90136, 0x108},
+	{0x90137, 0x8},
+	{0x90138, 0x7aa},
+	{0x90139, 0x6a},
+	{0x9013a, 0x0},
+	{0x9013b, 0x8568},
+	{0x9013c, 0x108},
+	{0x9013d, 0xb7},
+	{0x9013e, 0x790},
+	{0x9013f, 0x16a},
+	{0x90140, 0x1f},
+	{0x90141, 0x0},
+	{0x90142, 0x68},
+	{0x90143, 0x8},
+	{0x90144, 0x8558},
+	{0x90145, 0x168},
+	{0x90146, 0xf},
+	{0x90147, 0x408},
+	{0x90148, 0x169},
+	{0x90149, 0xd},
+	{0x9014a, 0x0},
+	{0x9014b, 0x68},
+	{0x9014c, 0x0},
+	{0x9014d, 0x408},
+	{0x9014e, 0x169},
+	{0x9014f, 0x0},
+	{0x90150, 0x8558},
+	{0x90151, 0x168},
+	{0x90152, 0x8},
+	{0x90153, 0x3c8},
+	{0x90154, 0x1a9},
+	{0x90155, 0x3},
+	{0x90156, 0x370},
+	{0x90157, 0x129},
+	{0x90158, 0x20},
+	{0x90159, 0x2aa},
+	{0x9015a, 0x9},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x104},
+	{0x90164, 0x8},
+	{0x90165, 0x448},
+	{0x90166, 0x109},
+	{0x90167, 0xf},
+	{0x90168, 0x7c0},
+	{0x90169, 0x109},
+	{0x9016a, 0x0},
+	{0x9016b, 0xe8},
+	{0x9016c, 0x109},
+	{0x9016d, 0x47},
+	{0x9016e, 0x630},
+	{0x9016f, 0x109},
+	{0x90170, 0x8},
+	{0x90171, 0x618},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0xe0},
+	{0x90175, 0x109},
+	{0x90176, 0x0},
+	{0x90177, 0x7c8},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0x8140},
+	{0x9017b, 0x10c},
+	{0x9017c, 0x0},
+	{0x9017d, 0x478},
+	{0x9017e, 0x109},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x0},
+	{0x90006, 0x8},
+	{0x90007, 0x7c8},
+	{0x90008, 0x109},
+	{0x90009, 0x0},
+	{0x9000a, 0x400},
+	{0x9000b, 0x106},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2b},
+	{0x90026, 0x69},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x200be, 0x3},
+	{0x2000b, 0x2a3},
+	{0x2000c, 0x96},
+	{0x2000d, 0x5dc},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x152},
+	{0x12000c, 0x4b},
+	{0x12000d, 0x2ee},
+	{0x12000e, 0x2c},
+	{0x22000b, 0xb0},
+	{0x22000c, 0x27},
+	{0x22000d, 0x186},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x400f1, 0xe},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x0},
+	{0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1200mts 1D */
+		.drate = 1200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1200, 625, },
+	.fsp_cfg = ddr_dram_fsp_cfg,
+	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c
new file mode 100644
index 00000000000..811687170c3
--- /dev/null
+++ b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x4e300110, 0x44100001},
+	{0x4e300000, 0x8000ef},
+	{0x4e300008, 0x0},
+	{0x4e300080, 0x80000512},
+	{0x4e300084, 0x0},
+	{0x4e300114, 0x1012},
+	{0x4e300260, 0x80},
+	{0x4e300f04, 0x80},
+	{0x4e300800, 0x43b30d00},
+	{0x4e300804, 0x1f1f1f1f},
+	{0x4e301000, 0xc0000000},
+	{0x4e301240, 0x0},
+	{0x4e301244, 0x0},
+	{0x4e301248, 0x0},
+	{0x4e30124c, 0x0},
+	{0x4e301250, 0x0},
+	{0x4e301254, 0x0},
+	{0x4e301258, 0x0},
+	{0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+	{
+		{
+			{0x4e300100, 0x135C2110},
+			{0x4e300104, 0xF8990011},
+			{0x4e300108, 0x636E08CC},
+			{0x4e30010C, 0x0061E070},
+			{0x4e300124, 0x124E0000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x31D00000},
+			{0x4e300170, 0x8B0B0608},
+			{0x4e300250, 0x0000001A},
+			{0x4e300254, 0x00DC00DC},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+			{0x4e300300, 0x1633160D},
+			{0x4e300304, 0x00DC180C},
+			{0x4e300308, 0x0C3C0927},
+		},
+		{
+			{0x01, 0xC4},
+			{0x02, 0x24},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x010D1100},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0xBABAC068},
+			{0x4e30010C, 0x00610158},
+			{0x4e300124, 0x09270000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30400000},
+			{0x4e300170, 0x8A0A0508},
+			{0x4e300250, 0x0000000D},
+			{0x4e300254, 0x006A006A},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0xA4},
+			{0x02, 0x52},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x00061000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x6E62FA48},
+			{0x4e30010C, 0x0031010D},
+			{0x4e300124, 0x04C50000},
+			{0x4e300160, 0x00009102},
+			{0x4e30016C, 0x30000000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000007},
+			{0x4e300254, 0x00340034},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x33},
+			{0x0b, 0x46},
+			{0x0c, 0x11},
+			{0x0e, 0x48},
+			{0x16, 0x04},
+		},
+		1,
+	},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x4},
+	{0x100a1, 0x5},
+	{0x100a2, 0x6},
+	{0x100a3, 0x7},
+	{0x100a4, 0x0},
+	{0x100a5, 0x1},
+	{0x100a6, 0x2},
+	{0x100a7, 0x3},
+	{0x110a0, 0x3},
+	{0x110a1, 0x2},
+	{0x110a2, 0x0},
+	{0x110a3, 0x1},
+	{0x110a4, 0x7},
+	{0x110a5, 0x6},
+	{0x110a6, 0x4},
+	{0x110a7, 0x5},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x11005f, 0x1ff},
+	{0x11015f, 0x1ff},
+	{0x11105f, 0x1ff},
+	{0x11115f, 0x1ff},
+	{0x21005f, 0x1ff},
+	{0x21015f, 0x1ff},
+	{0x21105f, 0x1ff},
+	{0x21115f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x200c5, 0xa},
+	{0x1200c5, 0x2},
+	{0x2200c5, 0x7},
+	{0x2002e, 0x2},
+	{0x12002e, 0x1},
+	{0x22002e, 0x2},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x2007d, 0x212},
+	{0x2007c, 0x61},
+	{0x120024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x12007d, 0x212},
+	{0x12007c, 0x61},
+	{0x220024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x22007d, 0x212},
+	{0x22007c, 0x61},
+	{0x20056, 0x3},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
+	{0x1004d, 0x600},
+	{0x1014d, 0x600},
+	{0x1104d, 0x600},
+	{0x1114d, 0x600},
+	{0x11004d, 0x600},
+	{0x11014d, 0x600},
+	{0x11104d, 0x600},
+	{0x11114d, 0x600},
+	{0x21004d, 0x600},
+	{0x21014d, 0x600},
+	{0x21104d, 0x600},
+	{0x21114d, 0x600},
+	{0x10049, 0xe3f},
+	{0x10149, 0xe3f},
+	{0x11049, 0xe3f},
+	{0x11149, 0xe3f},
+	{0x110049, 0xe3f},
+	{0x110149, 0xe3f},
+	{0x111049, 0xe3f},
+	{0x111149, 0xe3f},
+	{0x210049, 0xe3f},
+	{0x210149, 0xe3f},
+	{0x211049, 0xe3f},
+	{0x211149, 0xe3f},
+	{0x43, 0x7f},
+	{0x1043, 0x7f},
+	{0x2043, 0x7f},
+	{0x20018, 0x1},
+	{0x20075, 0x4},
+	{0x20050, 0x11},
+	{0x2009b, 0x2},
+	{0x20008, 0x258},
+	{0x120008, 0x12c},
+	{0x220008, 0x9c},
+	{0x20088, 0x9},
+	{0x200b2, 0x10c},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x1200b2, 0x10c},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x2200b2, 0x10c},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
+	{0x200fa, 0x2},
+	{0x1200fa, 0x2},
+	{0x2200fa, 0x2},
+	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
+	{0x200f0, 0x600},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5655},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x1004a, 0x500},
+	{0x1104a, 0x500},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
+	{0x2002c, 0x0},
+	{0x20021, 0x0},
+	{0x200c7, 0x21},
+	{0x1200c7, 0x41},
+	{0x200ca, 0x24},
+	{0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x1005f, 0x0},
+	{0x1015f, 0x0},
+	{0x1105f, 0x0},
+	{0x1115f, 0x0},
+	{0x11005f, 0x0},
+	{0x11015f, 0x0},
+	{0x11105f, 0x0},
+	{0x11115f, 0x0},
+	{0x21005f, 0x0},
+	{0x21015f, 0x0},
+	{0x21105f, 0x0},
+	{0x21115f, 0x0},
+	{0x55, 0x0},
+	{0x1055, 0x0},
+	{0x2055, 0x0},
+	{0x200c5, 0x0},
+	{0x1200c5, 0x0},
+	{0x2200c5, 0x0},
+	{0x2002e, 0x0},
+	{0x12002e, 0x0},
+	{0x22002e, 0x0},
+	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x20024, 0x0},
+	{0x2003a, 0x0},
+	{0x2007d, 0x0},
+	{0x2007c, 0x0},
+	{0x120024, 0x0},
+	{0x12007d, 0x0},
+	{0x12007c, 0x0},
+	{0x220024, 0x0},
+	{0x22007d, 0x0},
+	{0x22007c, 0x0},
+	{0x20056, 0x0},
+	{0x120056, 0x0},
+	{0x220056, 0x0},
+	{0x1004d, 0x0},
+	{0x1014d, 0x0},
+	{0x1104d, 0x0},
+	{0x1114d, 0x0},
+	{0x11004d, 0x0},
+	{0x11014d, 0x0},
+	{0x11104d, 0x0},
+	{0x11114d, 0x0},
+	{0x21004d, 0x0},
+	{0x21014d, 0x0},
+	{0x21104d, 0x0},
+	{0x21114d, 0x0},
+	{0x10049, 0x0},
+	{0x10149, 0x0},
+	{0x11049, 0x0},
+	{0x11149, 0x0},
+	{0x110049, 0x0},
+	{0x110149, 0x0},
+	{0x111049, 0x0},
+	{0x111149, 0x0},
+	{0x210049, 0x0},
+	{0x210149, 0x0},
+	{0x211049, 0x0},
+	{0x211149, 0x0},
+	{0x43, 0x0},
+	{0x1043, 0x0},
+	{0x2043, 0x0},
+	{0x20018, 0x0},
+	{0x20075, 0x0},
+	{0x20050, 0x0},
+	{0x2009b, 0x0},
+	{0x20008, 0x0},
+	{0x120008, 0x0},
+	{0x220008, 0x0},
+	{0x20088, 0x0},
+	{0x200b2, 0x0},
+	{0x10043, 0x0},
+	{0x10143, 0x0},
+	{0x11043, 0x0},
+	{0x11143, 0x0},
+	{0x1200b2, 0x0},
+	{0x110043, 0x0},
+	{0x110143, 0x0},
+	{0x111043, 0x0},
+	{0x111143, 0x0},
+	{0x2200b2, 0x0},
+	{0x210043, 0x0},
+	{0x210143, 0x0},
+	{0x211043, 0x0},
+	{0x211143, 0x0},
+	{0x200fa, 0x0},
+	{0x1200fa, 0x0},
+	{0x2200fa, 0x0},
+	{0x20019, 0x0},
+	{0x120019, 0x0},
+	{0x220019, 0x0},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x0},
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+	{0x116b4, 0x0},
+	{0x117b4, 0x0},
+	{0x118b4, 0x0},
+	{0x20089, 0x0},
+	{0xc0080, 0x0},
+	{0x200cb, 0x0},
+	{0x10068, 0x0},
+	{0x10069, 0x0},
+	{0x10168, 0x0},
+	{0x10169, 0x0},
+	{0x10268, 0x0},
+	{0x10269, 0x0},
+	{0x10368, 0x0},
+	{0x10369, 0x0},
+	{0x10468, 0x0},
+	{0x10469, 0x0},
+	{0x10568, 0x0},
+	{0x10569, 0x0},
+	{0x10668, 0x0},
+	{0x10669, 0x0},
+	{0x10768, 0x0},
+	{0x10769, 0x0},
+	{0x10868, 0x0},
+	{0x10869, 0x0},
+	{0x100aa, 0x0},
+	{0x10062, 0x0},
+	{0x10001, 0x0},
+	{0x100a0, 0x0},
+	{0x100a1, 0x0},
+	{0x100a2, 0x0},
+	{0x100a3, 0x0},
+	{0x100a4, 0x0},
+	{0x100a5, 0x0},
+	{0x100a6, 0x0},
+	{0x100a7, 0x0},
+	{0x11068, 0x0},
+	{0x11069, 0x0},
+	{0x11168, 0x0},
+	{0x11169, 0x0},
+	{0x11268, 0x0},
+	{0x11269, 0x0},
+	{0x11368, 0x0},
+	{0x11369, 0x0},
+	{0x11468, 0x0},
+	{0x11469, 0x0},
+	{0x11568, 0x0},
+	{0x11569, 0x0},
+	{0x11668, 0x0},
+	{0x11669, 0x0},
+	{0x11768, 0x0},
+	{0x11769, 0x0},
+	{0x11868, 0x0},
+	{0x11869, 0x0},
+	{0x110aa, 0x0},
+	{0x11062, 0x0},
+	{0x11001, 0x0},
+	{0x110a0, 0x0},
+	{0x110a1, 0x0},
+	{0x110a2, 0x0},
+	{0x110a3, 0x0},
+	{0x110a4, 0x0},
+	{0x110a5, 0x0},
+	{0x110a6, 0x0},
+	{0x110a7, 0x0},
+	{0x80, 0x0},
+	{0x1080, 0x0},
+	{0x2080, 0x0},
+	{0x10020, 0x0},
+	{0x10080, 0x0},
+	{0x10081, 0x0},
+	{0x100d0, 0x0},
+	{0x100d1, 0x0},
+	{0x1008c, 0x0},
+	{0x1008d, 0x0},
+	{0x10180, 0x0},
+	{0x10181, 0x0},
+	{0x101d0, 0x0},
+	{0x101d1, 0x0},
+	{0x1018c, 0x0},
+	{0x1018d, 0x0},
+	{0x100c0, 0x0},
+	{0x100c1, 0x0},
+	{0x101c0, 0x0},
+	{0x101c1, 0x0},
+	{0x102c0, 0x0},
+	{0x102c1, 0x0},
+	{0x103c0, 0x0},
+	{0x103c1, 0x0},
+	{0x104c0, 0x0},
+	{0x104c1, 0x0},
+	{0x105c0, 0x0},
+	{0x105c1, 0x0},
+	{0x106c0, 0x0},
+	{0x106c1, 0x0},
+	{0x107c0, 0x0},
+	{0x107c1, 0x0},
+	{0x108c0, 0x0},
+	{0x108c1, 0x0},
+	{0x100ae, 0x0},
+	{0x100af, 0x0},
+	{0x11020, 0x0},
+	{0x11080, 0x0},
+	{0x11081, 0x0},
+	{0x110d0, 0x0},
+	{0x110d1, 0x0},
+	{0x1108c, 0x0},
+	{0x1108d, 0x0},
+	{0x11180, 0x0},
+	{0x11181, 0x0},
+	{0x111d0, 0x0},
+	{0x111d1, 0x0},
+	{0x1118c, 0x0},
+	{0x1118d, 0x0},
+	{0x110c0, 0x0},
+	{0x110c1, 0x0},
+	{0x111c0, 0x0},
+	{0x111c1, 0x0},
+	{0x112c0, 0x0},
+	{0x112c1, 0x0},
+	{0x113c0, 0x0},
+	{0x113c1, 0x0},
+	{0x114c0, 0x0},
+	{0x114c1, 0x0},
+	{0x115c0, 0x0},
+	{0x115c1, 0x0},
+	{0x116c0, 0x0},
+	{0x116c1, 0x0},
+	{0x117c0, 0x0},
+	{0x117c1, 0x0},
+	{0x118c0, 0x0},
+	{0x118c1, 0x0},
+	{0x110ae, 0x0},
+	{0x110af, 0x0},
+	{0x90201, 0x0},
+	{0x90202, 0x0},
+	{0x90203, 0x0},
+	{0x90205, 0x0},
+	{0x90206, 0x0},
+	{0x90207, 0x0},
+	{0x90208, 0x0},
+	{0x20020, 0x0},
+	{0x100080, 0x0},
+	{0x101080, 0x0},
+	{0x102080, 0x0},
+	{0x110020, 0x0},
+	{0x110080, 0x0},
+	{0x110081, 0x0},
+	{0x1100d0, 0x0},
+	{0x1100d1, 0x0},
+	{0x11008c, 0x0},
+	{0x11008d, 0x0},
+	{0x110180, 0x0},
+	{0x110181, 0x0},
+	{0x1101d0, 0x0},
+	{0x1101d1, 0x0},
+	{0x11018c, 0x0},
+	{0x11018d, 0x0},
+	{0x1100c0, 0x0},
+	{0x1100c1, 0x0},
+	{0x1101c0, 0x0},
+	{0x1101c1, 0x0},
+	{0x1102c0, 0x0},
+	{0x1102c1, 0x0},
+	{0x1103c0, 0x0},
+	{0x1103c1, 0x0},
+	{0x1104c0, 0x0},
+	{0x1104c1, 0x0},
+	{0x1105c0, 0x0},
+	{0x1105c1, 0x0},
+	{0x1106c0, 0x0},
+	{0x1106c1, 0x0},
+	{0x1107c0, 0x0},
+	{0x1107c1, 0x0},
+	{0x1108c0, 0x0},
+	{0x1108c1, 0x0},
+	{0x1100ae, 0x0},
+	{0x1100af, 0x0},
+	{0x111020, 0x0},
+	{0x111080, 0x0},
+	{0x111081, 0x0},
+	{0x1110d0, 0x0},
+	{0x1110d1, 0x0},
+	{0x11108c, 0x0},
+	{0x11108d, 0x0},
+	{0x111180, 0x0},
+	{0x111181, 0x0},
+	{0x1111d0, 0x0},
+	{0x1111d1, 0x0},
+	{0x11118c, 0x0},
+	{0x11118d, 0x0},
+	{0x1110c0, 0x0},
+	{0x1110c1, 0x0},
+	{0x1111c0, 0x0},
+	{0x1111c1, 0x0},
+	{0x1112c0, 0x0},
+	{0x1112c1, 0x0},
+	{0x1113c0, 0x0},
+	{0x1113c1, 0x0},
+	{0x1114c0, 0x0},
+	{0x1114c1, 0x0},
+	{0x1115c0, 0x0},
+	{0x1115c1, 0x0},
+	{0x1116c0, 0x0},
+	{0x1116c1, 0x0},
+	{0x1117c0, 0x0},
+	{0x1117c1, 0x0},
+	{0x1118c0, 0x0},
+	{0x1118c1, 0x0},
+	{0x1110ae, 0x0},
+	{0x1110af, 0x0},
+	{0x190201, 0x0},
+	{0x190202, 0x0},
+	{0x190203, 0x0},
+	{0x190205, 0x0},
+	{0x190206, 0x0},
+	{0x190207, 0x0},
+	{0x190208, 0x0},
+	{0x120020, 0x0},
+	{0x200080, 0x0},
+	{0x201080, 0x0},
+	{0x202080, 0x0},
+	{0x210020, 0x0},
+	{0x210080, 0x0},
+	{0x210081, 0x0},
+	{0x2100d0, 0x0},
+	{0x2100d1, 0x0},
+	{0x21008c, 0x0},
+	{0x21008d, 0x0},
+	{0x210180, 0x0},
+	{0x210181, 0x0},
+	{0x2101d0, 0x0},
+	{0x2101d1, 0x0},
+	{0x21018c, 0x0},
+	{0x21018d, 0x0},
+	{0x2100c0, 0x0},
+	{0x2100c1, 0x0},
+	{0x2101c0, 0x0},
+	{0x2101c1, 0x0},
+	{0x2102c0, 0x0},
+	{0x2102c1, 0x0},
+	{0x2103c0, 0x0},
+	{0x2103c1, 0x0},
+	{0x2104c0, 0x0},
+	{0x2104c1, 0x0},
+	{0x2105c0, 0x0},
+	{0x2105c1, 0x0},
+	{0x2106c0, 0x0},
+	{0x2106c1, 0x0},
+	{0x2107c0, 0x0},
+	{0x2107c1, 0x0},
+	{0x2108c0, 0x0},
+	{0x2108c1, 0x0},
+	{0x2100ae, 0x0},
+	{0x2100af, 0x0},
+	{0x211020, 0x0},
+	{0x211080, 0x0},
+	{0x211081, 0x0},
+	{0x2110d0, 0x0},
+	{0x2110d1, 0x0},
+	{0x21108c, 0x0},
+	{0x21108d, 0x0},
+	{0x211180, 0x0},
+	{0x211181, 0x0},
+	{0x2111d0, 0x0},
+	{0x2111d1, 0x0},
+	{0x21118c, 0x0},
+	{0x21118d, 0x0},
+	{0x2110c0, 0x0},
+	{0x2110c1, 0x0},
+	{0x2111c0, 0x0},
+	{0x2111c1, 0x0},
+	{0x2112c0, 0x0},
+	{0x2112c1, 0x0},
+	{0x2113c0, 0x0},
+	{0x2113c1, 0x0},
+	{0x2114c0, 0x0},
+	{0x2114c1, 0x0},
+	{0x2115c0, 0x0},
+	{0x2115c1, 0x0},
+	{0x2116c0, 0x0},
+	{0x2116c1, 0x0},
+	{0x2117c0, 0x0},
+	{0x2117c1, 0x0},
+	{0x2118c0, 0x0},
+	{0x2118c1, 0x0},
+	{0x2110ae, 0x0},
+	{0x2110af, 0x0},
+	{0x290201, 0x0},
+	{0x290202, 0x0},
+	{0x290203, 0x0},
+	{0x290205, 0x0},
+	{0x290206, 0x0},
+	{0x290207, 0x0},
+	{0x290208, 0x0},
+	{0x220020, 0x0},
+	{0x20077, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
+	{0x400c0, 0x0},
+	{0x10040, 0x0},
+	{0x10140, 0x0},
+	{0x10240, 0x0},
+	{0x10340, 0x0},
+	{0x10440, 0x0},
+	{0x10540, 0x0},
+	{0x10640, 0x0},
+	{0x10740, 0x0},
+	{0x10840, 0x0},
+	{0x11040, 0x0},
+	{0x11140, 0x0},
+	{0x11240, 0x0},
+	{0x11340, 0x0},
+	{0x11440, 0x0},
+	{0x11540, 0x0},
+	{0x11640, 0x0},
+	{0x11740, 0x0},
+	{0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x960},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x24c4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x24c4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xc400},
+	{0x54033, 0x3324},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xc400},
+	{0x54039, 0x3324},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x4b0},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x52a4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x52a4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xa400},
+	{0x54033, 0x3352},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xa400},
+	{0x54039, 0x3352},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x270},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4800},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4800},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x3309},
+	{0x54034, 0x4600},
+	{0x54035, 0x11},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x3309},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x11},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0x960},
+	{0x54004, 0x4},
+	{0x54006, 0x15},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54010, 0x2080},
+	{0x54012, 0x110},
+	{0x54019, 0x24c4},
+	{0x5401a, 0x33},
+	{0x5401b, 0x1146},
+	{0x5401c, 0x4808},
+	{0x5401e, 0x4},
+	{0x5401f, 0x24c4},
+	{0x54020, 0x33},
+	{0x54021, 0x1146},
+	{0x54022, 0x4808},
+	{0x54024, 0x4},
+	{0x54032, 0xc400},
+	{0x54033, 0x3324},
+	{0x54034, 0x4600},
+	{0x54035, 0x811},
+	{0x54036, 0x48},
+	{0x54037, 0x400},
+	{0x54038, 0xc400},
+	{0x54039, 0x3324},
+	{0x5403a, 0x4600},
+	{0x5403b, 0x811},
+	{0x5403c, 0x48},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x30},
+	{0x90051, 0x65a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x45a},
+	{0x90055, 0x9},
+	{0x90056, 0x0},
+	{0x90057, 0x448},
+	{0x90058, 0x109},
+	{0x90059, 0x40},
+	{0x9005a, 0x633},
+	{0x9005b, 0x179},
+	{0x9005c, 0x1},
+	{0x9005d, 0x618},
+	{0x9005e, 0x109},
+	{0x9005f, 0x40c0},
+	{0x90060, 0x633},
+	{0x90061, 0x149},
+	{0x90062, 0x8},
+	{0x90063, 0x4},
+	{0x90064, 0x48},
+	{0x90065, 0x4040},
+	{0x90066, 0x633},
+	{0x90067, 0x149},
+	{0x90068, 0x0},
+	{0x90069, 0x4},
+	{0x9006a, 0x48},
+	{0x9006b, 0x40},
+	{0x9006c, 0x633},
+	{0x9006d, 0x149},
+	{0x9006e, 0x0},
+	{0x9006f, 0x658},
+	{0x90070, 0x109},
+	{0x90071, 0x10},
+	{0x90072, 0x4},
+	{0x90073, 0x18},
+	{0x90074, 0x0},
+	{0x90075, 0x4},
+	{0x90076, 0x78},
+	{0x90077, 0x549},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0xd49},
+	{0x9007b, 0x633},
+	{0x9007c, 0x159},
+	{0x9007d, 0x94a},
+	{0x9007e, 0x633},
+	{0x9007f, 0x159},
+	{0x90080, 0x441},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x42},
+	{0x90084, 0x633},
+	{0x90085, 0x149},
+	{0x90086, 0x1},
+	{0x90087, 0x633},
+	{0x90088, 0x149},
+	{0x90089, 0x0},
+	{0x9008a, 0xe0},
+	{0x9008b, 0x109},
+	{0x9008c, 0xa},
+	{0x9008d, 0x10},
+	{0x9008e, 0x109},
+	{0x9008f, 0x9},
+	{0x90090, 0x3c0},
+	{0x90091, 0x149},
+	{0x90092, 0x9},
+	{0x90093, 0x3c0},
+	{0x90094, 0x159},
+	{0x90095, 0x18},
+	{0x90096, 0x10},
+	{0x90097, 0x109},
+	{0x90098, 0x0},
+	{0x90099, 0x3c0},
+	{0x9009a, 0x109},
+	{0x9009b, 0x18},
+	{0x9009c, 0x4},
+	{0x9009d, 0x48},
+	{0x9009e, 0x18},
+	{0x9009f, 0x4},
+	{0x900a0, 0x58},
+	{0x900a1, 0xb},
+	{0x900a2, 0x10},
+	{0x900a3, 0x109},
+	{0x900a4, 0x1},
+	{0x900a5, 0x10},
+	{0x900a6, 0x109},
+	{0x900a7, 0x5},
+	{0x900a8, 0x7c0},
+	{0x900a9, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900aa, 0x0},
+	{0x900ab, 0x790},
+	{0x900ac, 0x11a},
+	{0x900ad, 0x8},
+	{0x900ae, 0x7aa},
+	{0x900af, 0x2a},
+	{0x900b0, 0x10},
+	{0x900b1, 0x7b2},
+	{0x900b2, 0x2a},
+	{0x900b3, 0x0},
+	{0x900b4, 0x7c8},
+	{0x900b5, 0x109},
+	{0x900b6, 0x10},
+	{0x900b7, 0x10},
+	{0x900b8, 0x109},
+	{0x900b9, 0x10},
+	{0x900ba, 0x2a8},
+	{0x900bb, 0x129},
+	{0x900bc, 0x8},
+	{0x900bd, 0x370},
+	{0x900be, 0x129},
+	{0x900bf, 0xa},
+	{0x900c0, 0x3c8},
+	{0x900c1, 0x1a9},
+	{0x900c2, 0xc},
+	{0x900c3, 0x408},
+	{0x900c4, 0x199},
+	{0x900c5, 0x14},
+	{0x900c6, 0x790},
+	{0x900c7, 0x11a},
+	{0x900c8, 0x8},
+	{0x900c9, 0x4},
+	{0x900ca, 0x18},
+	{0x900cb, 0xe},
+	{0x900cc, 0x408},
+	{0x900cd, 0x199},
+	{0x900ce, 0x8},
+	{0x900cf, 0x8568},
+	{0x900d0, 0x108},
+	{0x900d1, 0x18},
+	{0x900d2, 0x790},
+	{0x900d3, 0x16a},
+	{0x900d4, 0x8},
+	{0x900d5, 0x1d8},
+	{0x900d6, 0x169},
+	{0x900d7, 0x10},
+	{0x900d8, 0x8558},
+	{0x900d9, 0x168},
+	{0x900da, 0x1ff8},
+	{0x900db, 0x85a8},
+	{0x900dc, 0x1e8},
+	{0x900dd, 0x50},
+	{0x900de, 0x798},
+	{0x900df, 0x16a},
+	{0x900e0, 0x60},
+	{0x900e1, 0x7a0},
+	{0x900e2, 0x16a},
+	{0x900e3, 0x8},
+	{0x900e4, 0x8310},
+	{0x900e5, 0x168},
+	{0x900e6, 0x8},
+	{0x900e7, 0xa310},
+	{0x900e8, 0x168},
+	{0x900e9, 0xa},
+	{0x900ea, 0x408},
+	{0x900eb, 0x169},
+	{0x900ec, 0x6e},
+	{0x900ed, 0x0},
+	{0x900ee, 0x68},
+	{0x900ef, 0x0},
+	{0x900f0, 0x408},
+	{0x900f1, 0x169},
+	{0x900f2, 0x0},
+	{0x900f3, 0x8310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x0},
+	{0x900f6, 0xa310},
+	{0x900f7, 0x168},
+	{0x900f8, 0x1ff8},
+	{0x900f9, 0x85a8},
+	{0x900fa, 0x1e8},
+	{0x900fb, 0x68},
+	{0x900fc, 0x798},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x78},
+	{0x900ff, 0x7a0},
+	{0x90100, 0x16a},
+	{0x90101, 0x68},
+	{0x90102, 0x790},
+	{0x90103, 0x16a},
+	{0x90104, 0x8},
+	{0x90105, 0x8b10},
+	{0x90106, 0x168},
+	{0x90107, 0x8},
+	{0x90108, 0xab10},
+	{0x90109, 0x168},
+	{0x9010a, 0xa},
+	{0x9010b, 0x408},
+	{0x9010c, 0x169},
+	{0x9010d, 0x58},
+	{0x9010e, 0x0},
+	{0x9010f, 0x68},
+	{0x90110, 0x0},
+	{0x90111, 0x408},
+	{0x90112, 0x169},
+	{0x90113, 0x0},
+	{0x90114, 0x8b10},
+	{0x90115, 0x168},
+	{0x90116, 0x1},
+	{0x90117, 0xab10},
+	{0x90118, 0x168},
+	{0x90119, 0x0},
+	{0x9011a, 0x1d8},
+	{0x9011b, 0x169},
+	{0x9011c, 0x80},
+	{0x9011d, 0x790},
+	{0x9011e, 0x16a},
+	{0x9011f, 0x18},
+	{0x90120, 0x7aa},
+	{0x90121, 0x6a},
+	{0x90122, 0xa},
+	{0x90123, 0x0},
+	{0x90124, 0x1e9},
+	{0x90125, 0x8},
+	{0x90126, 0x8080},
+	{0x90127, 0x108},
+	{0x90128, 0xf},
+	{0x90129, 0x408},
+	{0x9012a, 0x169},
+	{0x9012b, 0xc},
+	{0x9012c, 0x0},
+	{0x9012d, 0x68},
+	{0x9012e, 0x9},
+	{0x9012f, 0x0},
+	{0x90130, 0x1a9},
+	{0x90131, 0x0},
+	{0x90132, 0x408},
+	{0x90133, 0x169},
+	{0x90134, 0x0},
+	{0x90135, 0x8080},
+	{0x90136, 0x108},
+	{0x90137, 0x8},
+	{0x90138, 0x7aa},
+	{0x90139, 0x6a},
+	{0x9013a, 0x0},
+	{0x9013b, 0x8568},
+	{0x9013c, 0x108},
+	{0x9013d, 0xb7},
+	{0x9013e, 0x790},
+	{0x9013f, 0x16a},
+	{0x90140, 0x1f},
+	{0x90141, 0x0},
+	{0x90142, 0x68},
+	{0x90143, 0x8},
+	{0x90144, 0x8558},
+	{0x90145, 0x168},
+	{0x90146, 0xf},
+	{0x90147, 0x408},
+	{0x90148, 0x169},
+	{0x90149, 0xd},
+	{0x9014a, 0x0},
+	{0x9014b, 0x68},
+	{0x9014c, 0x0},
+	{0x9014d, 0x408},
+	{0x9014e, 0x169},
+	{0x9014f, 0x0},
+	{0x90150, 0x8558},
+	{0x90151, 0x168},
+	{0x90152, 0x8},
+	{0x90153, 0x3c8},
+	{0x90154, 0x1a9},
+	{0x90155, 0x3},
+	{0x90156, 0x370},
+	{0x90157, 0x129},
+	{0x90158, 0x20},
+	{0x90159, 0x2aa},
+	{0x9015a, 0x9},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x104},
+	{0x90164, 0x8},
+	{0x90165, 0x448},
+	{0x90166, 0x109},
+	{0x90167, 0xf},
+	{0x90168, 0x7c0},
+	{0x90169, 0x109},
+	{0x9016a, 0x0},
+	{0x9016b, 0xe8},
+	{0x9016c, 0x109},
+	{0x9016d, 0x47},
+	{0x9016e, 0x630},
+	{0x9016f, 0x109},
+	{0x90170, 0x8},
+	{0x90171, 0x618},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0xe0},
+	{0x90175, 0x109},
+	{0x90176, 0x0},
+	{0x90177, 0x7c8},
+	{0x90178, 0x109},
+	{0x90179, 0x8},
+	{0x9017a, 0x8140},
+	{0x9017b, 0x10c},
+	{0x9017c, 0x0},
+	{0x9017d, 0x478},
+	{0x9017e, 0x109},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x0},
+	{0x90006, 0x8},
+	{0x90007, 0x7c8},
+	{0x90008, 0x109},
+	{0x90009, 0x0},
+	{0x9000a, 0x400},
+	{0x9000b, 0x106},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x2b},
+	{0x90026, 0x69},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x200be, 0x3},
+	{0x2000b, 0x2a3},
+	{0x2000c, 0x96},
+	{0x2000d, 0x5dc},
+	{0x2000e, 0x2c},
+	{0x12000b, 0x152},
+	{0x12000c, 0x4b},
+	{0x12000d, 0x2ee},
+	{0x12000e, 0x2c},
+	{0x22000b, 0xb0},
+	{0x22000c, 0x27},
+	{0x22000d, 0x186},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x400f1, 0xe},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x0},
+	{0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1200mts 1D */
+		.drate = 1200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1200, 625, },
+	.fsp_cfg = ddr_dram_fsp_cfg,
+	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx91_evk/spl.c b/board/freescale/imx91_evk/spl.c
new file mode 100644
index 00000000000..46bde93fe3b
--- /dev/null
+++ b/board/freescale/imx91_evk/spl.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch-mx7ulp/gpio.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <linux/delay.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/arch/trdc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = ele_start_rng();
+	if (ret)
+		printf("Fail to start RNG: %d\n", ret);
+
+	puts("Normal Boot\n");
+}
+
+extern struct dram_timing_info dram_timing_1600mts;
+void spl_dram_init(void)
+{
+	struct dram_timing_info *ptiming = &dram_timing;
+
+	if (is_voltage_mode(VOLT_LOW_DRIVE))
+		ptiming = &dram_timing_1600mts;
+
+	printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
+	ddr_init(ptiming);
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int val = 0, buck_val;
+
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("ERROR: Get PMIC PCA9451A failed!\n");
+		return ret;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+	/* enable DVS control through PMIC_STBY_REQ */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+	if (ret < 0)
+		return ret;
+
+	val = ret;
+
+	if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+		buck_val = 0x0c; /* 0.8V for Low drive mode */
+		printf("PMIC: Low Drive Voltage Mode\n");
+	} else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+		buck_val = 0x10; /* 0.85V for Nominal drive mode */
+		printf("PMIC: Nominal Voltage Mode\n");
+	} else {
+		buck_val = 0x14; /* 0.9V for Over drive mode */
+		printf("PMIC: Over Drive Voltage Mode\n");
+	}
+
+	if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
+	} else {
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+	}
+
+	/* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
+
+	/* set standby voltage to 0.65V */
+	if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+	else
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+	/* I2C_LT_EN*/
+	pmic_reg_write(dev, 0xa, 0x3);
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	timer_init();
+
+	arch_cpu_init();
+
+	spl_early_init();
+
+	preloader_console_init();
+
+	ret = imx9_probe_mu();
+	if (ret) {
+		printf("Fail to init ELE API\n");
+	} else {
+		debug("SOC: 0x%x\n", gd->arch.soc_rev);
+		debug("LC: 0x%x\n", gd->arch.lifecycle);
+	}
+
+	clock_init_late();
+
+	power_init_board();
+
+	if (!is_voltage_mode(VOLT_LOW_DRIVE))
+		set_arm_clk(get_cpu_speed_grade_hz());
+
+	/* Init power of mix */
+	soc_power_init();
+
+	/* Setup TRDC for DDR access */
+	trdc_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 002d7bbf864..bcdc1a2a468 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -144,7 +144,7 @@ static int power_init_board(struct udevice *gsc)
 	if ((!strncmp(model, "GW71", 4)) ||
 	    (!strncmp(model, "GW72", 4)) ||
 	    (!strncmp(model, "GW73", 4)) ||
-	    (!strncmp(model, "GW7905", 6))) {
+	    (!strncmp(model, "GW75", 4))) {
 		ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
 		if (ret) {
 			printf("PMIC    : failed I2C1 probe: %d\n", ret);
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 3443dc91885..db96534857c 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -151,8 +151,8 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val)
 		return -ENOSYS;
 
 	switch (id) {
-	case SYSINFO_ID_SMBIOS_SYSTEM_VERSION:
-	case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: {
+	case SYSID_SM_SYSTEM_VERSION:
+	case SYSID_SM_BASEBOARD_VERSION: {
 		ret = get_skuconfig(dev);
 
 		if (ret < 0)
@@ -162,7 +162,7 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val)
 		sprintf(val, "rev%d", ret);
 		break;
 	}
-	case SYSINFO_ID_BOARD_MODEL: {
+	case SYSID_BOARD_MODEL: {
 		int mem_config, sku_config;
 		const char *model;
 
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index f3df83ed6c9..0ec88447384 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -97,15 +97,16 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
 }
 #endif
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
 	/*
 	 * The ECME management processor loads the DTB from NOR flash
 	 * into DRAM (at 4KB), where it gets patched to contain the
 	 * detected memory size.
 	 */
-	return (void *)0x1000;
+	*fdtp = (void *)0x1000;
+
+	return 0;
 }
 
 static int is_highbank(void)
diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile
index e989e7aacc5..700e26daa2b 100644
--- a/board/hoperun/hihope-rzg2/Makefile
+++ b/board/hoperun/hihope-rzg2/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y	:= hihope-rzg2.o ../../renesas/rcar-common/common.o
+obj-y	:= hihope-rzg2.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index f394ace786a..bc5511707ac 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -19,6 +19,14 @@ config PHYTEC_IMX8M_SOM_DETECTION
 	  Support of I2C EEPROM based SoM detection. Supported
 	  for PHYTEC i.MX8MM/i.MX8MP boards
 
+config PHYTEC_IMX93_SOM_DETECTION
+	bool "Support SoM detection for i.MX93 PHYTEC platforms"
+	depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
+	default y
+	help
+	  Support of I2C EEPROM based SoM detection. Supported
+	  for PHYTEC i.MX93 based boards
+
 config PHYTEC_AM62_SOM_DETECTION
 	bool "Support SoM detection for AM62x PHYTEC platforms"
 	depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile
index cd78f7686fe..8126f7356e1 100644
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -10,3 +10,4 @@ endif
 obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
 obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
 obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
+obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx93_som_detection.c
new file mode 100644
index 00000000000..eb9574d43b5
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <[email protected]>
+ */
+
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <u-boot/crc.h>
+
+#include "imx93_som_detection.h"
+
+extern struct phytec_eeprom_data eeprom_data;
+
+#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
+
+/* Check if the SoM is actually one of the following products:
+ * - i.MX93
+ *
+ * Returns 0 in case it's a known SoM. Otherwise, returns 1.
+ */
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+	u8 som;
+
+	if (!data)
+		data = &eeprom_data;
+
+	/* Early API revisions are not supported */
+	if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+		return 1;
+
+	som = data->payload.data.data_api2.som_no;
+	debug("%s: som id: %u\n", __func__, som);
+
+	if (som == PHYTEC_IMX93_SOM && is_imx93())
+		return 0;
+
+	pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
+	return 1;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM options by option index
+ *
+ * Returns:
+ *  - option value
+ *  - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+				       enum phytec_imx93_option_index idx)
+{
+	char *opt;
+	u8 opt_id;
+
+	if (!data)
+		data = &eeprom_data;
+
+	if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
+		return PHYTEC_EEPROM_INVAL;
+
+	opt = phytec_get_opt(data);
+	if (opt)
+		opt_id = PHYTEC_GET_OPTION(opt[idx]);
+	else
+		opt_id = PHYTEC_EEPROM_INVAL;
+
+	debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id);
+	return opt_id;
+}
+
+/*
+ * Filter PHYTEC i.MX93 SoM voltage
+ *
+ * Returns:
+ *  - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3
+ *  - PHYTEC_EEPROM_INVAL when the data is invalid
+ *
+ */
+enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data)
+{
+	u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
+
+	if (option == PHYTEC_EEPROM_INVAL)
+		return PHYTEC_IMX93_VOLTAGE_INVALID;
+	return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3;
+}
+
+#else
+
+inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+{
+	return 1;
+}
+
+inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+					      enum phytec_imx93_option_index idx)
+{
+	return PHYTEC_EEPROM_INVAL;
+}
+
+inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+	(struct phytec_eeprom_data *data)
+{
+	return PHYTEC_EEPROM_INVAL;
+}
+
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h
new file mode 100644
index 00000000000..a0803b47cbe
--- /dev/null
+++ b/board/phytec/common/imx93_som_detection.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <[email protected]>
+ */
+
+#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
+#define _PHYTEC_IMX93_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX93_SOM	77
+
+enum phytec_imx93_option_index {
+	PHYTEC_IMX93_OPT_DDR = 0,
+	PHYTEC_IMX93_OPT_EMMC = 1,
+	PHYTEC_IMX93_OPT_CPU = 2,
+	PHYTEC_IMX93_OPT_FREQ = 3,
+	PHYTEC_IMX93_OPT_NPU = 4,
+	PHYTEC_IMX93_OPT_DISP = 5,
+	PHYTEC_IMX93_OPT_ETH = 6,
+	PHYTEC_IMX93_OPT_FEAT = 7,
+	PHYTEC_IMX93_OPT_TEMP = 8,
+	PHYTEC_IMX93_OPT_BOOT = 9,
+	PHYTEC_IMX93_OPT_LED = 10,
+	PHYTEC_IMX93_OPT_EEPROM = 11,
+};
+
+enum phytec_imx93_voltage {
+	PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX93_VOLTAGE_3V3 = 0,
+	PHYTEC_IMX93_VOLTAGE_1V8 = 1,
+};
+
+enum phytec_imx93_ddr_eeprom_code {
+	PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX93_LPDDR4X_512MB = 0,
+	PHYTEC_IMX93_LPDDR4X_1GB = 1,
+	PHYTEC_IMX93_LPDDR4X_2GB = 2,
+	PHYTEC_IMX93_LPDDR4_512MB = 3,
+	PHYTEC_IMX93_LPDDR4_1GB = 4,
+	PHYTEC_IMX93_LPDDR4_2GB = 5,
+};
+
+u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
+				       enum phytec_imx93_option_index idx);
+enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+	(struct phytec_eeprom_data *data);
+
+#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig
new file mode 100644
index 00000000000..282f4b79742
--- /dev/null
+++ b/board/phytec/common/k3/Kconfig
@@ -0,0 +1,5 @@
+config PHYTEC_K3_DDR_PATCH
+	bool "Patch DDR timings on PHYTEC K3 SoMs"
+	help
+	   Allow to override default DDR timings prior to
+	   DDRSS driver probing.
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile
index 40e91a43e99..6861c70e17e 100644
--- a/board/phytec/common/k3/Makefile
+++ b/board/phytec/common/k3/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0+
 obj-y += board.o
-obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o
+obj-$(CONFIG_PHYTEC_K3_DDR_PATCH) += k3_ddrss_patch.o
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 346b2b6491a..9ff861cd3f4 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -4,15 +4,92 @@
  * Author: Wadim Egorov <[email protected]>
  */
 
+#include <efi_loader.h>
 #include <env_internal.h>
 #include <fdt_support.h>
 #include <dm/ofnode.h>
+#include <mtd.h>
 #include <spl.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
 
 #include "../am6_som_detection.h"
 
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+struct efi_fw_image fw_images[] = {
+	{
+		.fw_name = PHYCORE_AM6XX_FW_NAME_TIBOOT3,
+		.image_index = 1,
+	},
+	{
+		.fw_name = PHYCORE_AM6XX_FW_NAME_SPL,
+		.image_index = 2,
+	},
+	{
+		.fw_name = PHYCORE_AM6XX_FW_NAME_UBOOT,
+		.image_index = 3,
+	}
+};
+
+struct efi_capsule_update_info update_info = {
+	.dfu_string = NULL,
+	.num_images = ARRAY_SIZE(fw_images),
+	.images = fw_images,
+};
+
+/**
+ * configure_capsule_updates() - Set up the DFU string for capsule updates
+ *
+ * Configures all three bootloader binaries for updates on the current
+ * booted flash device, which may be eMMC, OSPI NOR, or a uSD card. If
+ * booting from USB or Serial, capsule updates will be performed on the
+ * eMMC device.
+ *
+ * Note: Currently, eMMC hardware partitions are not differentiated; Updates
+ * are always applied to the first boot partition.
+ */
+void configure_capsule_updates(void)
+{
+	static char dfu_string[128] = { 0 };
+	const char *dfu_raw = "tiboot3.bin raw 0x0 0x400 mmcpart 1;"
+			      "tispl.bin raw 0x400 0x1000 mmcpart 1;"
+			      "u-boot.img.raw raw 0x1400 0x2000 mmcpart 1";
+	const char *dfu_fat = "tiboot3.bin fat 1 1;"
+			      "tispl.bin fat 1 1;"
+			      "u-boot.img fat 1 1";
+	const char *dfu_spi = "tiboot3.bin part 1;"
+			     "tispl.bin part 2;"
+			     "u-boot.img part 3";
+	u32 boot_device = get_boot_device();
+
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		snprintf(dfu_string, 128, "mmc 0=%s", dfu_raw);
+		break;
+	case BOOT_DEVICE_MMC2:
+		snprintf(dfu_string, 128, "mmc 1=%s", dfu_fat);
+		break;
+	case BOOT_DEVICE_SPI:
+		mtd_probe_devices();
+		snprintf(dfu_string, 128, "mtd nor0=%s", dfu_spi);
+		break;
+	default:
+		snprintf(dfu_string, 128, "mmc 0=%s", dfu_raw);
+		break;
+	};
+
+	update_info.dfu_string = dfu_string;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+		env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
 #if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC)
 int mmc_get_env_dev(void)
 {
@@ -94,6 +171,10 @@ int board_late_init(void)
 		}
 	}
 
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+	configure_capsule_updates();
+#endif
+
 	return 0;
 }
 #endif
diff --git a/board/phytec/phycore_am62ax/Kconfig b/board/phytec/phycore_am62ax/Kconfig
new file mode 100644
index 00000000000..516dc8e2020
--- /dev/null
+++ b/board/phytec/phycore_am62ax/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#
+# Copyright (C) 2024 PHYTEC America LLC
+# Author: Garrett Giordano <[email protected]>
+
+if TARGET_PHYCORE_AM62AX_A53
+
+config SYS_BOARD
+       default "phycore_am62ax"
+
+config SYS_VENDOR
+       default "phytec"
+
+config SYS_CONFIG_NAME
+       default "phycore_am62ax"
+
+source "board/phytec/common/Kconfig"
+
+endif
+
+if TARGET_PHYCORE_AM62AX_R5
+
+config SYS_BOARD
+       default "phycore_am62ax"
+
+config SYS_VENDOR
+       default "phytec"
+
+config SYS_CONFIG_NAME
+       default "phycore_am62ax"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/phytec/common/Kconfig"
+
+endif
diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS
new file mode 100644
index 00000000000..3e4e2feff4e
--- /dev/null
+++ b/board/phytec/phycore_am62ax/MAINTAINERS
@@ -0,0 +1,14 @@
+phyCORE-AM62ax
+M:	Garrett Giordano <[email protected]>
+M:	Wadim Egorov <[email protected]>
+W:	https://www.phytec.com/product/phycore-am62a
+S:	Maintained
+F:	arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
+F:	arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsit.dtsi
+F:	arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+F:	arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
+F:	board/phytec/phycore_am62ax/
+F:	configs/phycore_am62ax_a53_defconfig
+F:	configs/phycore_am62ax_r5_defconfig
+F:	include/configs/phycore_am62ax.h
+F:	doc/board/phytec/phycore-am62ax.rst
diff --git a/board/phytec/phycore_am62ax/Makefile b/board/phytec/phycore_am62ax/Makefile
new file mode 100644
index 00000000000..61e7c92c1c9
--- /dev/null
+++ b/board/phytec/phycore_am62ax/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#
+# Copyright (C) 2024 PHYTEC America LLC
+# Author: Garrett Giordano <[email protected]>
+
+obj-y += phycore-am62ax.o
diff --git a/board/phytec/phycore_am62ax/board-cfg.yaml b/board/phytec/phycore_am62ax/board-cfg.yaml
new file mode 100644
index 00000000000..a0930d69b88
--- /dev/null
+++ b/board/phytec/phycore_am62ax/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62ax
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable: 0x5A
+        main_isolation_hostid: 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor: 0x1
+        scaling_profile: 0x1
+        disable_main_nav_secure_proxy: 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size: 0x10
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables: 0x00
+        trace_src_enables: 0x00
diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c
new file mode 100644
index 00000000000..14b8959c07a
--- /dev/null
+++ b/board/phytec/phycore_am62ax/phycore-am62ax.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <[email protected]>
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <fdt_support.h>
+
+#include "../common/am6_som_detection.h"
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#define CTRLMMR_USB0_PHY_CTRL   0x43004008
+#define CTRLMMR_USB1_PHY_CTRL   0x43004018
+#define CORE_VOLTAGE            0x80000000
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	u32 val;
+
+	/* Set USB0 PHY core voltage to 0.85V */
+	val = readl(CTRLMMR_USB0_PHY_CTRL);
+	val &= ~(CORE_VOLTAGE);
+	writel(val, CTRLMMR_USB0_PHY_CTRL);
+
+	/* Set USB1 PHY core voltage to 0.85V */
+	val = readl(CTRLMMR_USB1_PHY_CTRL);
+	val &= ~(CORE_VOLTAGE);
+	writel(val, CTRLMMR_USB1_PHY_CTRL);
+
+	if (IS_ENABLED(CONFIG_SPL_ETH))
+		/* Init DRAM size for R5/A53 SPL */
+		dram_init_banksize();
+
+	/* We have 32k crystal, so lets enable it */
+	val = readl(MCU_CTRL_LFXOSC_CTRL);
+	val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
+	writel(val, MCU_CTRL_LFXOSC_CTRL);
+	/* Add any TRIM needed for the crystal here.. */
+	/* Make sure to mux up to take the SoC 32k from the crystal */
+	writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+	       MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+
+	/* Init DRAM size for R5/A53 SPL */
+	dram_init_banksize();
+}
+#endif
diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env
new file mode 100644
index 00000000000..77c5ea8d99a
--- /dev/null
+++ b/board/phytec/phycore_am62ax/phycore_am62ax.env
@@ -0,0 +1,14 @@
+fdtaddr=0x88000000
+loadaddr=0x82000000
+scriptaddr=0x80000000
+fdt_addr_r=0x88000000
+kernel_addr_r=0x82000000
+ramdisk_addr_r=0x88080000
+fdtoverlay_addr_r=0x89000000
+
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+mmcdev=1
+mmcroot=2
+mmcpart=1
+console=ttyS2,115200n8
+earlycon=ns16550a,mmio32,0x02800000
diff --git a/board/phytec/phycore_am62ax/pm-cfg.yaml b/board/phytec/phycore_am62ax/pm-cfg.yaml
new file mode 100644
index 00000000000..4031af2f4d3
--- /dev/null
+++ b/board/phytec/phycore_am62ax/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62ax
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml
new file mode 100644
index 00000000000..cbd087de797
--- /dev/null
+++ b/board/phytec/phycore_am62ax/rm-cfg.yaml
@@ -0,0 +1,1047 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62A
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size: 356
+            host_cfg_entries:
+                -   #  1
+                    host_id: 12
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -   #  2
+                    host_id: 20
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 3
+                    host_id: 30
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 4
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 5
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 6
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 7
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 8
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 9
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 10
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 11
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 12
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 13
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 14
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 15
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 16
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 17
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 18
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 19
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 20
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 21
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 22
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 23
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 24
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 25
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 26
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 27
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 28
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 29
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 30
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 31
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 32
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size: 8
+            resasg_entries_size: 1064
+            reserved: 0
+    resasg_entries:
+        -
+            start_resource: 0
+            num_resource: 16
+            type: 64
+            host_id: 12
+            reserved: 0
+        -
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+            type: 64
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+            reserved: 0
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+            reserved: 0
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+            num_resource: 64
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 83
+            num_resource: 8
+            type: 1938
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 91
+            num_resource: 8
+            type: 1939
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 99
+            num_resource: 10
+            type: 1942
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 112
+            num_resource: 3
+            type: 1942
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 115
+            num_resource: 3
+            type: 1942
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1944
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1945
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1946
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1947
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1955
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1955
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1955
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 27
+            num_resource: 1
+            type: 1957
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 28
+            num_resource: 1
+            type: 1958
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1961
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1961
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1961
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1962
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1962
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1962
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 1
+            type: 1965
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1966
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 21
+            num_resource: 1
+            type: 1967
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1968
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 1
+            type: 1969
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1970
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 1
+            type: 1971
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1972
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 2112
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 2
+            type: 2122
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 51200
+            num_resource: 12
+            type: 12738
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 12739
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
+            type: 12750
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
+            type: 12769
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 8
+            type: 12810
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 12288
+            num_resource: 128
+            type: 12813
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 3072
+            num_resource: 6
+            type: 12828
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 3584
+            num_resource: 6
+            type: 12829
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 6
+            type: 12830
+            host_id: 128
+            reserved: 0
diff --git a/board/phytec/phycore_am62ax/sec-cfg.yaml b/board/phytec/phycore_am62ax/sec-cfg.yaml
new file mode 100644
index 00000000000..ae6939eee9a
--- /dev/null
+++ b/board/phytec/phycore_am62ax/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for AM62ax
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            -  # 1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            -  # 1
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 2
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 3
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 4
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 5
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 6
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 7
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 8
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 9
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 10
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 11
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 12
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 13
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 14
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 15
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 16
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 17
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 18
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 19
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 20
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 21
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 22
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 23
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 24
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 25
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 26
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 27
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 28
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 29
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 30
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 31
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id: 0
+        otp_entry:
+            -  # 1
+                host_id: 0
+                host_perms: 0
+            -  # 2
+                host_id: 0
+                host_perms: 0
+            -  # 3
+                host_id: 0
+                host_perms: 0
+            -  # 4
+                host_id: 0
+                host_perms: 0
+            -  # 5
+                host_id: 0
+                host_perms: 0
+            -  # 6
+                host_id: 0
+                host_perms: 0
+            -  # 7
+                host_id: 0
+                host_perms: 0
+            -  # 8
+                host_id: 0
+                host_perms: 0
+            -  # 9
+                host_id: 0
+                host_perms: 0
+            -  # 10
+                host_id: 0
+                host_perms: 0
+            -  # 11
+                host_id: 0
+                host_perms: 0
+            -  # 12
+                host_id: 0
+                host_perms: 0
+            -  # 13
+                host_id: 0
+                host_perms: 0
+            -  # 14
+                host_id: 0
+                host_perms: 0
+            -  # 15
+                host_id: 0
+                host_perms: 0
+            -  # 16
+                host_id: 0
+                host_perms: 0
+            -  # 17
+                host_id: 0
+                host_perms: 0
+            -  # 18
+                host_id: 0
+                host_perms: 0
+            -  # 19
+                host_id: 0
+                host_perms: 0
+            -  # 20
+                host_id: 0
+                host_perms: 0
+            -  # 21
+                host_id: 0
+                host_perms: 0
+            -  # 22
+                host_id: 0
+                host_perms: 0
+            -  # 23
+                host_id: 0
+                host_perms: 0
+            -  # 24
+                host_id: 0
+                host_perms: 0
+            -  # 25
+                host_id: 0
+                host_perms: 0
+            -  # 26
+                host_id: 0
+                host_perms: 0
+            -  # 27
+                host_id: 0
+                host_perms: 0
+            -  # 28
+                host_id: 0
+                host_perms: 0
+            -  # 29
+                host_id: 0
+                host_perms: 0
+            -  # 30
+                host_id: 0
+                host_perms: 0
+            -  # 31
+                host_id: 0
+                host_perms: 0
+            -  # 32
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci: 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size: 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0x5A
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock: 0x5A
+        allow_wildcard_unlock: 0x5A
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev: 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender: 0
+        handover_to_host_id: 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
new file mode 100644
index 00000000000..151cd599b1b
--- /dev/null
+++ b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
@@ -0,0 +1,903 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62AX
+#
+
+---
+
+tifs-rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size: 356
+            host_cfg_entries:
+                -  # 1
+                    host_id: 12
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 2
+                    host_id: 30
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 3
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -  # 4
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 5
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 6
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 7
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 8
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 9
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 10
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 11
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 12
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 13
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 14
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 15
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 16
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 17
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 18
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 19
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 20
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 21
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 22
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 23
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 24
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 25
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 26
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 27
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 28
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 29
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 30
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 31
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -  # 32
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size: 8
+            resasg_entries_size: 872
+            reserved: 0
+    resasg_entries:
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1677
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1677
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1677
+            host_id: 36
+            reserved: 0
+        -
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+            num_resource: 2
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+            reserved: 0
+        -
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+            num_resource: 6
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+            reserved: 0
+        -
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+            num_resource: 18
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+            host_id: 12
+            reserved: 0
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+            num_resource: 6
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+            host_id: 35
+            reserved: 0
+        -
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+            reserved: 0
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+            num_resource: 2
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+            host_id: 30
+            reserved: 0
+        -
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+            num_resource: 2
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+            reserved: 0
+        -
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+            num_resource: 12
+            type: 1679
+            host_id: 12
+            reserved: 0
+        -
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+            num_resource: 6
+            type: 1679
+            host_id: 35
+            reserved: 0
+        -
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+            num_resource: 6
+            type: 1679
+            host_id: 36
+            reserved: 0
+        -
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+            num_resource: 2
+            type: 1679
+            host_id: 30
+            reserved: 0
+        -
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+            num_resource: 2
+            type: 1679
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1696
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1696
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1696
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1696
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 6
+            type: 1696
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 18
+            type: 1697
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1697
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 6
+            type: 1697
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 24
+            num_resource: 2
+            type: 1697
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 26
+            num_resource: 2
+            type: 1697
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 12
+            type: 1698
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 12
+            num_resource: 6
+            type: 1698
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 18
+            num_resource: 2
+            type: 1698
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 2
+            type: 1698
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6
+            num_resource: 34
+            type: 1802
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 36
+            type: 1802
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 44
+            num_resource: 36
+            type: 1802
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 168
+            num_resource: 8
+            type: 1802
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1024
+            type: 1807
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 29
+            type: 1808
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4608
+            num_resource: 99
+            type: 1809
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5120
+            num_resource: 24
+            type: 1810
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 5632
+            num_resource: 51
+            type: 1811
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 6144
+            num_resource: 51
+            type: 1812
+            host_id: 128
+            reserved: 0
+        -
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+            num_resource: 51
+            type: 1813
+            host_id: 128
+            reserved: 0
+        -
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+            num_resource: 32
+            type: 1814
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 8704
+            num_resource: 32
+            type: 1815
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9216
+            num_resource: 32
+            type: 1816
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 9728
+            num_resource: 22
+            type: 1817
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10240
+            num_resource: 22
+            type: 1818
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 10752
+            num_resource: 22
+            type: 1819
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11264
+            num_resource: 28
+            type: 1820
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 11776
+            num_resource: 28
+            type: 1821
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 12288
+            num_resource: 28
+            type: 1822
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1936
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1936
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1936
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1936
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 64
+            type: 1937
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 83
+            num_resource: 8
+            type: 1938
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 91
+            num_resource: 8
+            type: 1939
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 99
+            num_resource: 10
+            type: 1942
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 109
+            num_resource: 3
+            type: 1942
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 112
+            num_resource: 3
+            type: 1942
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 115
+            num_resource: 3
+            type: 1942
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 118
+            num_resource: 16
+            type: 1943
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1944
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 134
+            num_resource: 8
+            type: 1945
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1946
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 142
+            num_resource: 8
+            type: 1947
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1955
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1955
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1955
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1955
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 8
+            type: 1956
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 27
+            num_resource: 1
+            type: 1957
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 28
+            num_resource: 1
+            type: 1958
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1961
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1961
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1961
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1961
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 10
+            type: 1962
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 10
+            num_resource: 3
+            type: 1962
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 13
+            num_resource: 3
+            type: 1962
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 3
+            type: 1962
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 1
+            type: 1963
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 19
+            num_resource: 16
+            type: 1964
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 20
+            num_resource: 1
+            type: 1965
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1966
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 21
+            num_resource: 1
+            type: 1967
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 35
+            num_resource: 8
+            type: 1968
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 22
+            num_resource: 1
+            type: 1969
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1970
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 1
+            type: 1971
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 43
+            num_resource: 8
+            type: 1972
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 2112
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 2
+            type: 2122
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
+            type: 12750
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 6
+            type: 12769
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 8
+            type: 12810
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 3072
+            num_resource: 6
+            type: 12828
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 3584
+            num_resource: 6
+            type: 12829
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 4096
+            num_resource: 6
+            type: 12830
+            host_id: 128
+            reserved: 0
diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig
index 7c179ef0078..ecee5873c0c 100644
--- a/board/phytec/phycore_am62x/Kconfig
+++ b/board/phytec/phycore_am62x/Kconfig
@@ -33,6 +33,7 @@ config SPL_LDSCRIPT
 	default "arch/arm/mach-omap2/u-boot-spl.lds"
 
 source "board/phytec/common/Kconfig"
+source "board/phytec/common/k3/Kconfig"
 
 endif
 
diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig
index 25e4bf2f836..06449128ba8 100644
--- a/board/phytec/phycore_imx8mm/Kconfig
+++ b/board/phytec/phycore_imx8mm/Kconfig
@@ -12,4 +12,5 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
 
+source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env
new file mode 100644
index 00000000000..a7d14e774a0
--- /dev/null
+++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env
@@ -0,0 +1,65 @@
+#include <env/phytec/rauc.env>
+
+bootcmd=
+	mmc dev ${mmcdev};
+	if mmc rescan; then
+		if test ${doraucboot} = 1; then
+			run raucinit;
+		fi;
+		if run loadimage; then
+			run mmcboot;
+		else
+			run netboot;
+		fi;
+	fi;
+console=ttymxc2,115200
+emmc_dev=2
+fdt_addr_r=0x48000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+ip_dyn=yes
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+mmcargs=
+	setenv bootargs console=${console}
+	root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
+mmcautodetect=yes
+mmcboot=
+	echo Booting from mmc ...;
+	run mmcargs;
+	if run loadfdt; then
+		if test ${dofitboot} = 1; then
+			booti ${loadaddr} - ${fdt_addr_r}
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	fi;
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcpart=1
+mmcroot=2
+netargs=
+	setenv bootargs console=${console} root=/dev/nfs ip=dhcp
+	nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+	echo Booting from net ...;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	${get_cmd} ${loadaddr} ${image};
+	run netargs;
+	if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+		booti ${loadaddr} - ${fdt_addr_r};
+	else
+		echo WARN: Cannot load the DT;
+	fi;
+nfsroot=/srv/nfs
+update_bootimg=
+	mmc dev ${mmcdev};
+	if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then
+		setexpr fw_sz ${filesize} / 0x200;
+		mmc write ${loadaddr} ${update_offset} ${fw_sz};
+	fi;
+update_filename=flash.bin
+update_offset=0x42
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index 8d858590a39..faff064779c 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -17,8 +17,13 @@
 #include <log.h>
 #include <spl.h>
 
+#include "../common/imx8m_som_detection.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define EEPROM_ADDR		0x51
+#define EEPROM_ADDR_FALLBACK	0x59
+
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
@@ -39,6 +44,18 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 
 static void spl_dram_init(void)
 {
+	int ret;
+
+	ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
+			EEPROM_ADDR_FALLBACK);
+	if (ret)
+		goto out;
+
+	ret = phytec_imx8m_detect(NULL);
+	if (!ret)
+		phytec_print_som_info(NULL);
+
+out:
 	ddr_init(&dram_timing);
 }
 
diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig
index a70104cb798..09f26e89e33 100644
--- a/board/phytec/phycore_imx93/Kconfig
+++ b/board/phytec/phycore_imx93/Kconfig
@@ -10,4 +10,32 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "phycore_imx93"
 
+config PHYCORE_IMX93_RAM_TYPE_FIX
+	bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
+	default false
+	help
+	  RAM type and size is being automatically detected with the help
+	  of the PHYTEC EEPROM introspection data.
+	  Set RAM type to a fix value instead.
+
+choice
+	prompt "phyCORE-i.MX93 RAM type"
+	depends on PHYCORE_IMX93_RAM_TYPE_FIX
+	default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
+	bool "LPDDR4X 1GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
+	  for phyCORE-i.MX93.
+
+config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
+	bool "LPDDR4X 2GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
+	  for phyCORE-i.MX93.
+
+endchoice
+
+source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS
index 9e91a29dc31..718f89a084a 100644
--- a/board/phytec/phycore_imx93/MAINTAINERS
+++ b/board/phytec/phycore_imx93/MAINTAINERS
@@ -1,10 +1,13 @@
 phyCORE-i.MX93
-M:	Mathieu Othacehe <[email protected]>
+M:      Mathieu Othacehe <[email protected]>
+R:      Christoph Stoidner <[email protected]>
 W:      https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
 S:      Maintained
 F:      arch/arm/dts/imx93-phyboard-segin.dts
 F:      arch/arm/dts/imx93-phycore-som.dtsi
 F:      arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
 F:      board/phytec/phycore_imx93/
-F:      configs/imx93-phyboard-segin_defconfig
+F:      board/phytec/common/imx93_som_detection.c
+F:      board/phytec/common/imx93_som_detection.h
+F:      configs/imx93-phycore_defconfig
 F:      include/configs/phycore_imx93.h
diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c
index 2111972a40e..f1261f6a92a 100644
--- a/board/phytec/phycore_imx93/lpddr4_timing.c
+++ b/board/phytec/phycore_imx93/lpddr4_timing.c
@@ -1,24 +1,24 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2023 NXP
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Copyright 2024 NXP
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  * Christoph Stoidner <[email protected]>
  *
- * Code generated with DDR Tool v1.0.0.
+ * Code generated with DDR Tool v3.1.0_7.4.
  */
 
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
 
+/* Initialize DDRC registers */
 static struct dram_cfg_param ddr_ddrc_cfg[] = {
-	/** Initialize DDRC registers **/
 	{0x4e300110, 0x44100001},
 	{0x4e300000, 0x8000bf},
 	{0x4e300008, 0x0},
 	{0x4e300080, 0x80000412},
 	{0x4e300084, 0x0},
 	{0x4e300114, 0x1002},
-	{0x4e300260, 0x4080},
+	{0x4e300260, 0x80},
 	{0x4e300f04, 0x80},
 	{0x4e300800, 0x43b30002},
 	{0x4e300804, 0x1f1f1f1f},
@@ -31,18 +31,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x4e301254, 0x0},
 	{0x4e301258, 0x0},
 	{0x4e30125c, 0x0},
-
 };
 
 /* dram fsp cfg */
 static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
 	{
 		{
-			{0x4e300100, 0x24A0421B},
+			{0x4e300100, 0x24A0321B},
 			{0x4e300104, 0xF8EE001B},
-			{0x4e300108, 0x2F263233},
-			{0x4e30010C, 0x0005E18B},
-			{0x4e300124, 0x1C770000},
+			{0x4e300108, 0x2F2E3233},
+			{0x4e30010C, 0x0005C18B},
+			{0x4e300124, 0x1C790000},
 			{0x4e300160, 0x00009102},
 			{0x4e30016C, 0x35F00000},
 			{0x4e300170, 0x8B0B0608},
@@ -50,21 +49,73 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
 			{0x4e300254, 0x00FE00FE},
 			{0x4e300258, 0x00000008},
 			{0x4e30025C, 0x00000400},
-			{0x4e300300, 0x224F2215},
+			{0x4e300300, 0x224F2213},
 			{0x4e300304, 0x00FE2213},
-			{0x4e300308, 0x0A3C0E3C},
+			{0x4e300308, 0x0A380E3D},
 		},
 		{
 			{0x01, 0xE4},
 			{0x02, 0x36},
-			{0x03, 0xF2},
-			{0x0b, 0x46},
-			{0x0c, 0x11},
-			{0x0e, 0x11},
+			{0x03, 0x22},
+			{0x0b, 0x44},
+			{0x0c, 0x1E},
+			{0x0e, 0x12},
+			{0x16, 0x04},
+		},
+		0,
+	},
+	{
+		{
+			{0x4e300100, 0x124F2100},
+			{0x4e300104, 0xF877000E},
+			{0x4e300108, 0x1816E4AA},
+			{0x4e30010C, 0x005101E6},
+			{0x4e300124, 0x0E3C0000},
+			{0x4e300160, 0x00009101},
+			{0x4e30016C, 0x30900000},
+			{0x4e300170, 0x8A0A0508},
+			{0x4e300250, 0x00000014},
+			{0x4e300254, 0x007B007B},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0xB4},
+			{0x02, 0x1B},
+			{0x03, 0x22},
+			{0x0b, 0x44},
+			{0x0c, 0x1E},
+			{0x0e, 0x12},
 			{0x16, 0x04},
 		},
 		0,
 	},
+	{
+		{
+			{0x4e300100, 0x00051000},
+			{0x4e300104, 0xF855000A},
+			{0x4e300108, 0x6E620A48},
+			{0x4e30010C, 0x0031010D},
+			{0x4e300124, 0x04C50000},
+			{0x4e300160, 0x00009100},
+			{0x4e30016C, 0x30000000},
+			{0x4e300170, 0x89090408},
+			{0x4e300250, 0x00000007},
+			{0x4e300254, 0x00240024},
+			{0x4e300258, 0x00000008},
+			{0x4e30025C, 0x00000400},
+		},
+		{
+			{0x01, 0x94},
+			{0x02, 0x9},
+			{0x03, 0x22},
+			{0x0b, 0x44},
+			{0x0c, 0x1E},
+			{0x0e, 0x12},
+			{0x16, 0x04},
+		},
+		1,
+	},
 
 };
 
@@ -90,25 +141,65 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x1015f, 0x5ff},
 	{0x1105f, 0x5ff},
 	{0x1115f, 0x5ff},
+	{0x11005f, 0x5ff},
+	{0x11015f, 0x5ff},
+	{0x11105f, 0x5ff},
+	{0x11115f, 0x5ff},
+	{0x21005f, 0x5ff},
+	{0x21015f, 0x5ff},
+	{0x21105f, 0x5ff},
+	{0x21115f, 0x5ff},
 	{0x55, 0x1ff},
 	{0x1055, 0x1ff},
 	{0x2055, 0x1ff},
 	{0x200c5, 0x19},
+	{0x1200c5, 0xb},
+	{0x2200c5, 0x7},
 	{0x2002e, 0x2},
+	{0x12002e, 0x2},
+	{0x22002e, 0x2},
 	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
 	{0x20024, 0x1e3},
 	{0x2003a, 0x2},
 	{0x2007d, 0x212},
 	{0x2007c, 0x61},
+	{0x120024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x12007d, 0x212},
+	{0x12007c, 0x61},
+	{0x220024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x22007d, 0x212},
+	{0x22007c, 0x61},
 	{0x20056, 0x3},
+	{0x120056, 0x3},
+	{0x220056, 0x3},
 	{0x1004d, 0x600},
 	{0x1014d, 0x600},
 	{0x1104d, 0x600},
 	{0x1114d, 0x600},
-	{0x10049, 0xe00},
-	{0x10149, 0xe00},
-	{0x11049, 0xe00},
-	{0x11149, 0xe00},
+	{0x11004d, 0x600},
+	{0x11014d, 0x600},
+	{0x11104d, 0x600},
+	{0x11114d, 0x600},
+	{0x21004d, 0x600},
+	{0x21014d, 0x600},
+	{0x21104d, 0x600},
+	{0x21114d, 0x600},
+	{0x10049, 0x604},
+	{0x10149, 0x604},
+	{0x11049, 0x604},
+	{0x11149, 0x604},
+	{0x110049, 0x604},
+	{0x110149, 0x604},
+	{0x111049, 0x604},
+	{0x111149, 0x604},
+	{0x210049, 0x604},
+	{0x210149, 0x604},
+	{0x211049, 0x604},
+	{0x211149, 0x604},
 	{0x43, 0x60},
 	{0x1043, 0x60},
 	{0x2043, 0x60},
@@ -117,14 +208,30 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x20050, 0x0},
 	{0x2009b, 0x2},
 	{0x20008, 0x3a5},
+	{0x120008, 0x1d3},
+	{0x220008, 0x9c},
 	{0x20088, 0x9},
-	{0x200b2, 0x10c},
+	{0x200b2, 0x104},
 	{0x10043, 0x5a1},
 	{0x10143, 0x5a1},
 	{0x11043, 0x5a1},
 	{0x11143, 0x5a1},
+	{0x1200b2, 0x104},
+	{0x110043, 0x5a1},
+	{0x110143, 0x5a1},
+	{0x111043, 0x5a1},
+	{0x111143, 0x5a1},
+	{0x2200b2, 0x104},
+	{0x210043, 0x5a1},
+	{0x210143, 0x5a1},
+	{0x211043, 0x5a1},
+	{0x211143, 0x5a1},
 	{0x200fa, 0x2},
+	{0x1200fa, 0x2},
+	{0x2200fa, 0x2},
 	{0x20019, 0x1},
+	{0x120019, 0x1},
+	{0x220019, 0x1},
 	{0x200f0, 0x600},
 	{0x200f1, 0x0},
 	{0x200f2, 0x4444},
@@ -133,42 +240,83 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x200f5, 0x0},
 	{0x200f6, 0x0},
 	{0x200f7, 0xf000},
+	{0x1004a, 0x500},
+	{0x1104a, 0x500},
 	{0x20025, 0x0},
-	{0x2002d, 0x1},
+	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
 	{0x2002c, 0x0},
 	{0x20021, 0x0},
 	{0x200c7, 0x21},
 	{0x1200c7, 0x21},
 	{0x200ca, 0x24},
 	{0x1200ca, 0x24},
-
 };
 
-/* ddr phy trained csr */
+/* PHY trained csr */
 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x1005f, 0x0},
 	{0x1015f, 0x0},
 	{0x1105f, 0x0},
 	{0x1115f, 0x0},
+	{0x11005f, 0x0},
+	{0x11015f, 0x0},
+	{0x11105f, 0x0},
+	{0x11115f, 0x0},
+	{0x21005f, 0x0},
+	{0x21015f, 0x0},
+	{0x21105f, 0x0},
+	{0x21115f, 0x0},
 	{0x55, 0x0},
 	{0x1055, 0x0},
 	{0x2055, 0x0},
 	{0x200c5, 0x0},
+	{0x1200c5, 0x0},
+	{0x2200c5, 0x0},
 	{0x2002e, 0x0},
+	{0x12002e, 0x0},
+	{0x22002e, 0x0},
 	{0x90204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
 	{0x20024, 0x0},
 	{0x2003a, 0x0},
 	{0x2007d, 0x0},
 	{0x2007c, 0x0},
+	{0x120024, 0x0},
+	{0x12007d, 0x0},
+	{0x12007c, 0x0},
+	{0x220024, 0x0},
+	{0x22007d, 0x0},
+	{0x22007c, 0x0},
 	{0x20056, 0x0},
+	{0x120056, 0x0},
+	{0x220056, 0x0},
 	{0x1004d, 0x0},
 	{0x1014d, 0x0},
 	{0x1104d, 0x0},
 	{0x1114d, 0x0},
+	{0x11004d, 0x0},
+	{0x11014d, 0x0},
+	{0x11104d, 0x0},
+	{0x11114d, 0x0},
+	{0x21004d, 0x0},
+	{0x21014d, 0x0},
+	{0x21104d, 0x0},
+	{0x21114d, 0x0},
 	{0x10049, 0x0},
 	{0x10149, 0x0},
 	{0x11049, 0x0},
 	{0x11149, 0x0},
+	{0x110049, 0x0},
+	{0x110149, 0x0},
+	{0x111049, 0x0},
+	{0x111149, 0x0},
+	{0x210049, 0x0},
+	{0x210149, 0x0},
+	{0x211049, 0x0},
+	{0x211149, 0x0},
 	{0x43, 0x0},
 	{0x1043, 0x0},
 	{0x2043, 0x0},
@@ -177,14 +325,30 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x20050, 0x0},
 	{0x2009b, 0x0},
 	{0x20008, 0x0},
+	{0x120008, 0x0},
+	{0x220008, 0x0},
 	{0x20088, 0x0},
 	{0x200b2, 0x0},
 	{0x10043, 0x0},
 	{0x10143, 0x0},
 	{0x11043, 0x0},
 	{0x11143, 0x0},
+	{0x1200b2, 0x0},
+	{0x110043, 0x0},
+	{0x110143, 0x0},
+	{0x111043, 0x0},
+	{0x111143, 0x0},
+	{0x2200b2, 0x0},
+	{0x210043, 0x0},
+	{0x210143, 0x0},
+	{0x211043, 0x0},
+	{0x211143, 0x0},
 	{0x200fa, 0x0},
+	{0x1200fa, 0x0},
+	{0x2200fa, 0x0},
 	{0x20019, 0x0},
+	{0x120019, 0x0},
+	{0x220019, 0x0},
 	{0x200f0, 0x0},
 	{0x200f1, 0x0},
 	{0x200f2, 0x0},
@@ -193,8 +357,12 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x200f5, 0x0},
 	{0x200f6, 0x0},
 	{0x200f7, 0x0},
+	{0x1004a, 0x0},
+	{0x1104a, 0x0},
 	{0x20025, 0x0},
 	{0x2002d, 0x0},
+	{0x12002d, 0x0},
+	{0x22002d, 0x0},
 	{0x2002c, 0x0},
 	{0xd0000, 0x0},
 	{0x90000, 0x0},
@@ -682,6 +850,14 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x2000c, 0x0},
 	{0x2000d, 0x0},
 	{0x2000e, 0x0},
+	{0x12000b, 0x0},
+	{0x12000c, 0x0},
+	{0x12000d, 0x0},
+	{0x12000e, 0x0},
+	{0x22000b, 0x0},
+	{0x22000c, 0x0},
+	{0x22000d, 0x0},
+	{0x22000e, 0x0},
 	{0x9000c, 0x0},
 	{0x9000d, 0x0},
 	{0x9000e, 0x0},
@@ -692,12 +868,26 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x90013, 0x0},
 	{0x20010, 0x0},
 	{0x20011, 0x0},
+	{0x120010, 0x0},
+	{0x120011, 0x0},
 	{0x40080, 0x0},
 	{0x40081, 0x0},
 	{0x40082, 0x0},
 	{0x40083, 0x0},
 	{0x40084, 0x0},
 	{0x40085, 0x0},
+	{0x140080, 0x0},
+	{0x140081, 0x0},
+	{0x140082, 0x0},
+	{0x140083, 0x0},
+	{0x140084, 0x0},
+	{0x140085, 0x0},
+	{0x240080, 0x0},
+	{0x240081, 0x0},
+	{0x240082, 0x0},
+	{0x240083, 0x0},
+	{0x240084, 0x0},
+	{0x240085, 0x0},
 	{0x400fd, 0x0},
 	{0x400f1, 0x0},
 	{0x10011, 0x0},
@@ -866,6 +1056,160 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x90207, 0x0},
 	{0x90208, 0x0},
 	{0x20020, 0x0},
+	{0x100080, 0x0},
+	{0x101080, 0x0},
+	{0x102080, 0x0},
+	{0x110020, 0x0},
+	{0x110080, 0x0},
+	{0x110081, 0x0},
+	{0x1100d0, 0x0},
+	{0x1100d1, 0x0},
+	{0x11008c, 0x0},
+	{0x11008d, 0x0},
+	{0x110180, 0x0},
+	{0x110181, 0x0},
+	{0x1101d0, 0x0},
+	{0x1101d1, 0x0},
+	{0x11018c, 0x0},
+	{0x11018d, 0x0},
+	{0x1100c0, 0x0},
+	{0x1100c1, 0x0},
+	{0x1101c0, 0x0},
+	{0x1101c1, 0x0},
+	{0x1102c0, 0x0},
+	{0x1102c1, 0x0},
+	{0x1103c0, 0x0},
+	{0x1103c1, 0x0},
+	{0x1104c0, 0x0},
+	{0x1104c1, 0x0},
+	{0x1105c0, 0x0},
+	{0x1105c1, 0x0},
+	{0x1106c0, 0x0},
+	{0x1106c1, 0x0},
+	{0x1107c0, 0x0},
+	{0x1107c1, 0x0},
+	{0x1108c0, 0x0},
+	{0x1108c1, 0x0},
+	{0x1100ae, 0x0},
+	{0x1100af, 0x0},
+	{0x111020, 0x0},
+	{0x111080, 0x0},
+	{0x111081, 0x0},
+	{0x1110d0, 0x0},
+	{0x1110d1, 0x0},
+	{0x11108c, 0x0},
+	{0x11108d, 0x0},
+	{0x111180, 0x0},
+	{0x111181, 0x0},
+	{0x1111d0, 0x0},
+	{0x1111d1, 0x0},
+	{0x11118c, 0x0},
+	{0x11118d, 0x0},
+	{0x1110c0, 0x0},
+	{0x1110c1, 0x0},
+	{0x1111c0, 0x0},
+	{0x1111c1, 0x0},
+	{0x1112c0, 0x0},
+	{0x1112c1, 0x0},
+	{0x1113c0, 0x0},
+	{0x1113c1, 0x0},
+	{0x1114c0, 0x0},
+	{0x1114c1, 0x0},
+	{0x1115c0, 0x0},
+	{0x1115c1, 0x0},
+	{0x1116c0, 0x0},
+	{0x1116c1, 0x0},
+	{0x1117c0, 0x0},
+	{0x1117c1, 0x0},
+	{0x1118c0, 0x0},
+	{0x1118c1, 0x0},
+	{0x1110ae, 0x0},
+	{0x1110af, 0x0},
+	{0x190201, 0x0},
+	{0x190202, 0x0},
+	{0x190203, 0x0},
+	{0x190205, 0x0},
+	{0x190206, 0x0},
+	{0x190207, 0x0},
+	{0x190208, 0x0},
+	{0x120020, 0x0},
+	{0x200080, 0x0},
+	{0x201080, 0x0},
+	{0x202080, 0x0},
+	{0x210020, 0x0},
+	{0x210080, 0x0},
+	{0x210081, 0x0},
+	{0x2100d0, 0x0},
+	{0x2100d1, 0x0},
+	{0x21008c, 0x0},
+	{0x21008d, 0x0},
+	{0x210180, 0x0},
+	{0x210181, 0x0},
+	{0x2101d0, 0x0},
+	{0x2101d1, 0x0},
+	{0x21018c, 0x0},
+	{0x21018d, 0x0},
+	{0x2100c0, 0x0},
+	{0x2100c1, 0x0},
+	{0x2101c0, 0x0},
+	{0x2101c1, 0x0},
+	{0x2102c0, 0x0},
+	{0x2102c1, 0x0},
+	{0x2103c0, 0x0},
+	{0x2103c1, 0x0},
+	{0x2104c0, 0x0},
+	{0x2104c1, 0x0},
+	{0x2105c0, 0x0},
+	{0x2105c1, 0x0},
+	{0x2106c0, 0x0},
+	{0x2106c1, 0x0},
+	{0x2107c0, 0x0},
+	{0x2107c1, 0x0},
+	{0x2108c0, 0x0},
+	{0x2108c1, 0x0},
+	{0x2100ae, 0x0},
+	{0x2100af, 0x0},
+	{0x211020, 0x0},
+	{0x211080, 0x0},
+	{0x211081, 0x0},
+	{0x2110d0, 0x0},
+	{0x2110d1, 0x0},
+	{0x21108c, 0x0},
+	{0x21108d, 0x0},
+	{0x211180, 0x0},
+	{0x211181, 0x0},
+	{0x2111d0, 0x0},
+	{0x2111d1, 0x0},
+	{0x21118c, 0x0},
+	{0x21118d, 0x0},
+	{0x2110c0, 0x0},
+	{0x2110c1, 0x0},
+	{0x2111c0, 0x0},
+	{0x2111c1, 0x0},
+	{0x2112c0, 0x0},
+	{0x2112c1, 0x0},
+	{0x2113c0, 0x0},
+	{0x2113c1, 0x0},
+	{0x2114c0, 0x0},
+	{0x2114c1, 0x0},
+	{0x2115c0, 0x0},
+	{0x2115c1, 0x0},
+	{0x2116c0, 0x0},
+	{0x2116c1, 0x0},
+	{0x2117c0, 0x0},
+	{0x2117c1, 0x0},
+	{0x2118c0, 0x0},
+	{0x2118c1, 0x0},
+	{0x2110ae, 0x0},
+	{0x2110af, 0x0},
+	{0x290201, 0x0},
+	{0x290202, 0x0},
+	{0x290203, 0x0},
+	{0x290205, 0x0},
+	{0x290206, 0x0},
+	{0x290207, 0x0},
+	{0x290208, 0x0},
+	{0x220020, 0x0},
 	{0x20077, 0x0},
 	{0x20072, 0x0},
 	{0x20073, 0x0},
@@ -888,7 +1232,6 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 	{0x11640, 0x0},
 	{0x11740, 0x0},
 	{0x11840, 0x0},
-
 };
 
 /* P0 message block parameter for training firmware */
@@ -896,7 +1239,7 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{0xd0000, 0x0},
 	{0x54003, 0xe94},
 	{0x54004, 0x4},
-	{0x54006, 0x15},
+	{0x54006, 0x14},
 	{0x54008, 0x131f},
 	{0x54009, 0xc8},
 	{0x5400b, 0x4},
@@ -904,26 +1247,102 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{0x5400f, 0x100},
 	{0x54012, 0x110},
 	{0x54019, 0x36e4},
-	{0x5401a, 0xf2},
-	{0x5401b, 0x1146},
-	{0x5401c, 0x1108},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1208},
 	{0x5401e, 0x4},
 	{0x5401f, 0x36e4},
-	{0x54020, 0xf2},
-	{0x54021, 0x1146},
-	{0x54022, 0x1108},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1208},
 	{0x54024, 0x4},
 	{0x54032, 0xe400},
-	{0x54033, 0xf236},
-	{0x54034, 0x4600},
-	{0x54035, 0x811},
-	{0x54036, 0x11},
+	{0x54033, 0x2236},
+	{0x54034, 0x4400},
+	{0x54035, 0x81e},
+	{0x54036, 0x12},
 	{0x54037, 0x400},
 	{0x54038, 0xe400},
-	{0x54039, 0xf236},
-	{0x5403a, 0x4600},
-	{0x5403b, 0x811},
-	{0x5403c, 0x11},
+	{0x54039, 0x2236},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x81e},
+	{0x5403c, 0x12},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x1},
+	{0x54003, 0x74a},
+	{0x54004, 0x4},
+	{0x54006, 0x14},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x1bb4},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1208},
+	{0x5401e, 0x4},
+	{0x5401f, 0x1bb4},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1208},
+	{0x54024, 0x4},
+	{0x54032, 0xb400},
+	{0x54033, 0x221b},
+	{0x54034, 0x4400},
+	{0x54035, 0x81e},
+	{0x54036, 0x12},
+	{0x54037, 0x400},
+	{0x54038, 0xb400},
+	{0x54039, 0x221b},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x81e},
+	{0x5403c, 0x12},
+	{0x5403d, 0x400},
+	{0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002, 0x102},
+	{0x54003, 0x270},
+	{0x54004, 0x4},
+	{0x54006, 0x14},
+	{0x54008, 0x121f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x4},
+	{0x5400d, 0x100},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x994},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1200},
+	{0x5401e, 0x4},
+	{0x5401f, 0x994},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1200},
+	{0x54024, 0x4},
+	{0x54032, 0x9400},
+	{0x54033, 0x2209},
+	{0x54034, 0x4400},
+	{0x54035, 0x1e},
+	{0x54036, 0x12},
+	{0x54037, 0x400},
+	{0x54038, 0x9400},
+	{0x54039, 0x2209},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x1e},
+	{0x5403c, 0x12},
 	{0x5403d, 0x400},
 	{0xd0000, 0x1}
 };
@@ -933,7 +1352,7 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{0xd0000, 0x0},
 	{0x54003, 0xe94},
 	{0x54004, 0x4},
-	{0x54006, 0x15},
+	{0x54006, 0x14},
 	{0x54008, 0x61},
 	{0x54009, 0xc8},
 	{0x5400b, 0x4},
@@ -942,26 +1361,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{0x54010, 0x2080},
 	{0x54012, 0x110},
 	{0x54019, 0x36e4},
-	{0x5401a, 0xf2},
-	{0x5401b, 0x1146},
-	{0x5401c, 0x1108},
+	{0x5401a, 0x22},
+	{0x5401b, 0x1e44},
+	{0x5401c, 0x1208},
 	{0x5401e, 0x4},
 	{0x5401f, 0x36e4},
-	{0x54020, 0xf2},
-	{0x54021, 0x1146},
-	{0x54022, 0x1108},
+	{0x54020, 0x22},
+	{0x54021, 0x1e44},
+	{0x54022, 0x1208},
 	{0x54024, 0x4},
 	{0x54032, 0xe400},
-	{0x54033, 0xf236},
-	{0x54034, 0x4600},
-	{0x54035, 0x811},
-	{0x54036, 0x11},
+	{0x54033, 0x2236},
+	{0x54034, 0x4400},
+	{0x54035, 0x81e},
+	{0x54036, 0x12},
 	{0x54037, 0x400},
 	{0x54038, 0xe400},
-	{0x54039, 0xf236},
-	{0x5403a, 0x4600},
-	{0x5403b, 0x811},
-	{0x5403c, 0x11},
+	{0x54039, 0x2236},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x81e},
+	{0x5403c, 0x12},
 	{0x5403d, 0x400},
 	{0xd0000, 0x1}
 };
@@ -1451,10 +1870,18 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x400d7, 0x20b},
 	{0x2003a, 0x2},
 	{0x200be, 0x3},
-	{0x2000b, 0x75},
+	{0x2000b, 0x41a},
 	{0x2000c, 0xe9},
 	{0x2000d, 0x91c},
 	{0x2000e, 0x2c},
+	{0x12000b, 0x20d},
+	{0x12000c, 0x74},
+	{0x12000d, 0x48e},
+	{0x12000e, 0x2c},
+	{0x22000b, 0xb0},
+	{0x22000c, 0x27},
+	{0x22000d, 0x186},
+	{0x22000e, 0x10},
 	{0x9000c, 0x0},
 	{0x9000d, 0x173},
 	{0x9000e, 0x60},
@@ -1465,12 +1892,26 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x90013, 0x6152},
 	{0x20010, 0x5a},
 	{0x20011, 0x3},
+	{0x120010, 0x5a},
+	{0x120011, 0x3},
 	{0x40080, 0xe0},
 	{0x40081, 0x12},
 	{0x40082, 0xe0},
 	{0x40083, 0x12},
 	{0x40084, 0xe0},
 	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
 	{0x400fd, 0xf},
 	{0x400f1, 0xe},
 	{0x10011, 0x1},
@@ -1505,7 +1946,6 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{0x20088, 0x19},
 	{0xc0080, 0x0},
 	{0xd0000, 0x1},
-
 };
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1515,9 +1955,21 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 		.fw_type = FW_1D_IMAGE,
 		.fsp_cfg = ddr_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
-
 	},
-
+	{
+		/* P1 1866mts 1D */
+		.drate = 1866,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 625mts 1D */
+		.drate = 625,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
 	{
 		/* P0 3733mts 2D */
 		.drate = 3733,
@@ -1525,7 +1977,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 		.fsp_cfg = ddr_fsp0_2d_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
 	},
-
 };
 
 /* ddr timing config params */
@@ -1540,7 +1991,227 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3733, },
+	.fsp_table = { 3733, 1866, 625, },
 	.fsp_cfg = ddr_dram_fsp_cfg,
 	.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
 };
+
+void set_dram_timings_2gb_lpddr4x(void)
+{
+	/* Initialize DDRC registers */
+	dram_timing.ddrc_cfg[1].val = 0x8000ff;
+	dram_timing.ddrc_cfg[3].val = 0x80000512;
+
+	/* dram fsp cfg */
+	dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233;
+	dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213;
+	dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13;
+
+	dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100;
+	dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA;
+	dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA;
+	dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13;
+
+	dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000;
+	dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48;
+	dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034;
+	dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13;
+
+	/* P0 message block parameter for training firmware */
+	dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308;
+	dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13;
+
+	/* P1 message block parameter for training firmware */
+	dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308;
+	dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308;
+	dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13;
+	dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13;
+
+	/* P2 message block parameter for training firmware */
+	dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300;
+	dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300;
+	dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13;
+	dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13;
+
+	/* P0 2D message block parameter for training firmware */
+	dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308;
+	dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308;
+	dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13;
+	dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13;
+}
+
+/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */
+void set_dram_timings_1gb_lpddr4x_900mhz(void)
+{
+	/* Initialize DDRC registers */
+	dram_timing.ddrc_cfg[6].val = 0x4080;
+
+	/* dram fsp cfg */
+	dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100;
+	dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E;
+	dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA;
+	dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6;
+	dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000;
+	dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101;
+	dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000;
+	dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508;
+	dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014;
+	dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B;
+	dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A;
+	dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E;
+	dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4;
+	dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B;
+	dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2;
+	dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15;
+
+	dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA;
+	dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2;
+	dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15;
+
+	dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48;
+	dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2;
+	dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20;
+	dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15;
+
+	/* PHY Initialize Configuration */
+	dram_timing.ddrphy_cfg[31].val = 0xb;
+	dram_timing.ddrphy_cfg[86].val = 0x1d3;
+	dram_timing.ddrphy_cfg[90].val = 0x10c;
+	dram_timing.ddrphy_cfg[95].val = 0x10c;
+	dram_timing.ddrphy_cfg[100].val = 0x10c;
+	dram_timing.ddrphy_cfg[122].val = 0x1;
+	/**
+	 * NOTE:
+	 * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119
+	 * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not
+	 * present in the ddr_ddrphy_cfg array. However they were present in array
+	 * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+	 * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid
+	 * any negative side-effects.
+	 */
+	dram_timing.ddrphy_cfg[119].val = 0x400;
+	dram_timing.ddrphy_cfg[120].val = 0x400;
+
+	/**
+	 * NOTE:
+	 * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101
+	 * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present
+	 * in the ddr_ddrphy_trained_csr array. However they were present in array
+	 * generated with previous DDR Tool v3.1.0_7.4. We simply set both values
+	 * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid
+	 * any negative side-effects.
+	 */
+	/* PHY trained csr */
+	dram_timing.ddrphy_trained_csr[101].val = 0x0;
+	dram_timing.ddrphy_trained_csr[102].val = 0x0;
+
+	/* P0 message block parameter for training firmware */
+	dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a;
+	dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15;
+	dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4;
+	dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2;
+	dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508;
+	dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4;
+	dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2;
+	dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044;
+	dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508;
+	dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400;
+	dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15;
+	dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400;
+	dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820;
+	dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15;
+
+	/* P1 message block parameter for training firmware */
+	dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15;
+	dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2;
+	dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508;
+	dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2;
+	dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508;
+	dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b;
+	dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15;
+	dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b;
+	dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15;
+
+	/* P2 message block parameter for training firmware */
+	dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15;
+	dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2;
+	dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500;
+	dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2;
+	dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500;
+	dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209;
+	dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15;
+	dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209;
+	dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20;
+	dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15;
+
+	/* P0 2D message block parameter for training firmware */
+	dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a;
+	dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15;
+	dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4;
+	dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2;
+	dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508;
+	dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4;
+	dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2;
+	dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044;
+	dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508;
+	dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400;
+	dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b;
+	dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15;
+	dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400;
+	dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b;
+	dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820;
+	dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15;
+
+	/* DRAM PHY init engine image */
+	dram_timing.ddrphy_pie[483].val = 0x20d;
+	dram_timing.ddrphy_pie[484].val = 0x74;
+	dram_timing.ddrphy_pie[485].val = 0x48e;
+
+	/* P0 3733mts 1D */
+	dram_timing.fsp_msg[0].drate = 1866;
+
+	/* P0 1866mts 2D */
+	dram_timing.fsp_msg[3].drate = 1866;
+
+	/* ddr timing config params */
+	dram_timing.fsp_table[0] = 1866;
+}
diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c
index 085c8e195a6..a55795e0603 100644
--- a/board/phytec/phycore_imx93/phycore-imx93.c
+++ b/board/phytec/phycore_imx93/phycore-imx93.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  * Author: Christoph Stoidner <[email protected]>
  * Copyright (C) 2024 Mathieu Othacehe <[email protected]>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  */
 
 #include <asm/arch-imx9/ccm_regs.h>
@@ -12,11 +13,21 @@
 #include <asm/global_data.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <env.h>
+#include <fdt_support.h>
+
+#include "../common/imx93_som_detection.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define EEPROM_ADDR            0x50
+
 int board_init(void)
 {
+	int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
+
+	if (ret)
+		printf("%s: EEPROM data init failed\n", __func__);
+
 	return 0;
 }
 
@@ -40,3 +51,43 @@ int board_late_init(void)
 
 	return 0;
 }
+
+static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
+{
+	enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data);
+	int offset;
+
+	if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID)
+		goto err;
+
+	if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) {
+		offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
+						       0x42850000);
+		if (offset)
+			fdt_delprop(blob, offset, "no-1-8-v");
+		else
+			goto err;
+	}
+
+	return;
+err:
+	printf("Could not detect eMMC VDD-IO. Fall back to default.\n");
+}
+
+int board_fix_fdt(void *blob)
+{
+	struct phytec_eeprom_data data;
+
+	phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
+
+	emmc_fixup(blob, &data);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	emmc_fixup(blob, NULL);
+
+	return 0;
+}
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 17a8736c73f..a4d2aaac320 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  * Author: Christoph Stoidner <[email protected]>
  * Copyright (C) 2024 Mathieu Othacehe <[email protected]>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  */
 
 #include <asm/arch/clock.h>
@@ -20,6 +21,8 @@
 #include <power/pca9450.h>
 #include <spl.h>
 
+#include "../common/imx93_som_detection.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -27,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
  * when pca9451a support is added.
  */
 #define PCA9450_REG_PWRCTRL_TOFF_DEB    BIT(5)
+#define EEPROM_ADDR            0x50
+
+/*
+ * Prototypes of automatically generated ram config file
+ */
+void set_dram_timings_2gb_lpddr4x(void);
+void set_dram_timings_1gb_lpddr4x_900mhz(void);
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
@@ -46,6 +56,44 @@ void spl_board_init(void)
 
 void spl_dram_init(void)
 {
+	int ret;
+	enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
+
+	/* NOTE: In SPL lpi2c3 is mapped to bus 0 */
+	ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
+		goto out;
+
+	ret = phytec_imx93_detect(NULL);
+	if (!ret)
+		phytec_print_som_info(NULL);
+
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
+			ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
+			ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
+	} else {
+		ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
+	}
+
+	switch (ddr_opt) {
+	case PHYTEC_IMX93_LPDDR4X_1GB:
+		if (is_voltage_mode(VOLT_LOW_DRIVE))
+			set_dram_timings_1gb_lpddr4x_900mhz();
+		break;
+	case PHYTEC_IMX93_LPDDR4X_2GB:
+		set_dram_timings_2gb_lpddr4x();
+		break;
+	default:
+		goto out;
+	}
+	ddr_init(&dram_timing);
+	return;
+out:
+	puts("Could not detect correct RAM type and size. Fall back to default.\n");
+	if (is_voltage_mode(VOLT_LOW_DRIVE))
+		set_dram_timings_1gb_lpddr4x_900mhz();
 	ddr_init(&dram_timing);
 }
 
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 18be244aa79..aa39afa338a 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -521,15 +521,14 @@ int board_init(void)
 /*
  * If the firmware passed a device tree use it for U-Boot.
  */
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) {
-		*err = -ENXIO;
-		return NULL;
-	}
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return -ENXIO;
 
-	return (void *)fw_dtb_pointer;
+	*fdtp = (void *)fw_dtb_pointer;
+
+	return 0;
 }
 
 int copy_property(void *dst, void *src, char *path, char *property)
diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile
index cb965cde35f..fe3a2fd3b7a 100644
--- a/board/renesas/condor/Makefile
+++ b/board/renesas/condor/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ../rcar-common/common.o
+obj-y	:= ../rcar-common/gen3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile
index 8859cf902ca..3ed7800b0e9 100644
--- a/board/renesas/draak/Makefile
+++ b/board/renesas/draak/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= draak.o ../rcar-common/common.o
+obj-y	:= draak.o ../rcar-common/gen3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile
index 98164b5ea29..3f5fdab1bc2 100644
--- a/board/renesas/eagle/Makefile
+++ b/board/renesas/eagle/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile
index 283d3a4ae36..8139391029d 100644
--- a/board/renesas/ebisu/Makefile
+++ b/board/renesas/ebisu/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ../rcar-common/common.o
+obj-y	:= ../rcar-common/gen3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile
index 2e240d3bad6..48fcfac9105 100644
--- a/board/renesas/falcon/Makefile
+++ b/board/renesas/falcon/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= falcon.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/gen4-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c
deleted file mode 100644
index c88257d9677..00000000000
--- a/board/renesas/falcon/falcon.c
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/falcon/falcon.c
- *     This file is Falcon board support.
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
-
-#include <asm/arch/renesas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/processor.h>
-#include <linux/errno.h>
-#include <asm/system.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CPGWPR		0xE6150000
-#define CPGWPCR		0xE6150004
-
-#define EXTAL_CLK	16666600u
-#define CNTCR_BASE	0xE6080000
-#define CNTFID0		(CNTCR_BASE + 0x020)
-#define CNTCR_EN	BIT(0)
-
-static void init_generic_timer(void)
-{
-	u32 freq;
-
-	/* Set frequency data in CNTFID0 */
-	freq = EXTAL_CLK;
-
-	/* Update memory mapped and register based freqency */
-	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
-	writel(freq, CNTFID0);
-
-	/* Enable counter */
-	setbits_le32(CNTCR_BASE, CNTCR_EN);
-}
-
-/* Distributor Registers */
-#define GICD_BASE	0xF1000000
-
-/* ReDistributor Registers for Control and Physical LPIs */
-#define GICR_LPI_BASE	0xF1060000
-#define GICR_WAKER	0x0014
-#define GICR_PWRR	0x0024
-#define GICR_LPI_WAKER	(GICR_LPI_BASE + GICR_WAKER)
-#define GICR_LPI_PWRR	(GICR_LPI_BASE + GICR_PWRR)
-
-/* ReDistributor Registers for SGIs and PPIs */
-#define GICR_SGI_BASE	0xF1070000
-#define GICR_IGROUPR0	0x0080
-
-static void init_gic_v3(void)
-{
-	 /* GIC v3 power on */
-	writel(0x00000002, (GICR_LPI_PWRR));
-
-	/* Wait till the WAKER_CA_BIT changes to 0 */
-	writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
-	while (readl(GICR_LPI_WAKER) & 0x00000004)
-		;
-
-	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
-}
-
-void s_init(void)
-{
-	if (current_el() == 3)
-		init_generic_timer();
-}
-
-int board_early_init_f(void)
-{
-	/* Unlock CPG access */
-	writel(0x5A5AFFFF, CPGWPR);
-	writel(0xA5A50000, CPGWPCR);
-
-	return 0;
-}
-
-#define RST_BASE	0xE6160000 /* Domain0 */
-#define RST_WDTRSTCR	(RST_BASE + 0x10)
-#define RST_RWDT	0xA55A8002
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
-
-	if (current_el() == 3) {
-		init_gic_v3();
-
-		/* Enable RWDT reset */
-		writel(RST_RWDT, RST_WDTRSTCR);
-	}
-
-	return 0;
-}
diff --git a/board/renesas/grayhawk/Makefile b/board/renesas/grayhawk/Makefile
index 9c5b8c9a12f..7414b773326 100644
--- a/board/renesas/grayhawk/Makefile
+++ b/board/renesas/grayhawk/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y	:= grayhawk.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/gen4-common.o ../rcar-common/common.o
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index 499c31408f6..90eb468e4c4 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -15,201 +15,57 @@
 #include <asm/io.h>
 #include <dm/uclass-internal.h>
 #include <asm/arch/renesas.h>
+#include <asm/system.h>
 #include <linux/libfdt.h>
 
 #ifdef CONFIG_RCAR_64
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */
-extern u64 rcar_atf_boot_args[];
-
-#define FDT_RPC_PATH	"/soc/spi@ee200000"
-
-static void apply_atf_overlay(void *fdt_blob)
-{
-	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
-
-	if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
-		fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0);
-}
-
-int fdtdec_board_setup(const void *fdt_blob)
-{
-	apply_atf_overlay((void *)fdt_blob);
-
-	return 0;
-}
-
 int dram_init(void)
 {
-	return fdtdec_setup_mem_size_base();
-}
-
-int dram_init_banksize(void)
-{
-	fdtdec_setup_memory_banksize();
-
-	return 0;
-}
-
-int __weak board_init(void)
-{
-	return 0;
-}
-
-#if defined(CONFIG_RCAR_GEN3)
-#define RST_BASE	0xE6160000
-#define RST_CA57RESCNT	(RST_BASE + 0x40)
-#define RST_CA53RESCNT	(RST_BASE + 0x44)
-#define RST_RSTOUTCR	(RST_BASE + 0x58)
-#define RST_CA57_CODE	0xA5A5000F
-#define RST_CA53_CODE	0x5A5A000F
-
-void __weak reset_cpu(void)
-{
-	unsigned long midr, cputype;
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
-		writel(RST_CA53_CODE, RST_CA53RESCNT);
-	else if (cputype == 0xd07)
-		writel(RST_CA57_CODE, RST_CA57RESCNT);
-	else
-		hang();
-}
-#elif defined(CONFIG_RCAR_GEN4)
-#define RST_BASE	0xE6160000 /* Domain0 */
-#define RST_SRESCR0	(RST_BASE + 0x18)
-#define RST_SPRES	0x5AA58000
+	int ret = fdtdec_setup_mem_size_base();
 
-void __weak reset_cpu(void)
-{
-	writel(RST_SPRES, RST_SRESCR0);
-}
-#else
-#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
-{
-	struct fdt_resource first_mem_res, curr_mem_res;
-	int curr_mem_reg, first_mem_reg = 0;
-	int ret;
-
-	for (;;) {
-		ret = fdt_get_resource(blob, first_mem_node, "reg",
-				       first_mem_reg++, &first_mem_res);
-		if (ret) /* No more entries, no overlap found */
-			return 0;
-
-		curr_mem_reg = 0;
-		for (;;) {
-			ret = fdt_get_resource(blob, curr_mem_node, "reg",
-					       curr_mem_reg++, &curr_mem_res);
-			if (ret) /* No more entries, check next tuple */
-				break;
-
-			if (curr_mem_res.end < first_mem_res.start)
-				continue;
-
-			if (curr_mem_res.start >= first_mem_res.end)
-				continue;
-
-			log_debug("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n",
-				  first_mem_res.start, first_mem_res.end,
-				  curr_mem_res.start, curr_mem_res.end);
-
-			return 1;
-		}
+	if (current_el() == 3 && gd->ram_base == 0x48000000) {
+		/*
+		 * If this U-Boot runs in EL3, make the bottom 128 MiB
+		 * available for loading of follow up firmware blobs.
+		 */
+		gd->ram_base -= 0x8000000;
+		gd->ram_size += 0x8000000;
 	}
 
-	return 0;
+	return ret;
 }
 
-static void scrub_duplicate_memory(void *blob)
+int dram_init_banksize(void)
 {
-	/*
-	 * Scrub duplicate /memory@* node entries here. Some R-Car DTs might
-	 * contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
-	 * either generates single /memory node or updates the first /memory
-	 * node. Any remaining memory nodes are thus potential duplicates.
-	 *
-	 * However, it is not possible to delete all the memory nodes right
-	 * away, since some of those might not be DRAM memory nodes, but some
-	 * sort of other memory. Thus, delete only the memory nodes which are
-	 * in the R-Car3 DBSC ranges.
-	 */
-	int mem = 0, first_mem_node = 0;
+	int bank;
 
-	for (;;) {
-		mem = fdt_node_offset_by_prop_value(blob, mem,
-						    "device_type", "memory", 7);
-		if (mem < 0)
-			break;
-		if (!fdtdec_get_is_enabled(blob, mem))
-			continue;
+	fdtdec_setup_memory_banksize();
 
-		/* First memory node, patched by U-Boot */
-		if (!first_mem_node) {
-			first_mem_node = mem;
-			continue;
-		}
+	if (current_el() != 3)
+		return 0;
 
-		/* Check the remaining nodes and delete duplicates */
-		if (!is_mem_overlap(blob, first_mem_node, mem))
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		if (gd->bd->bi_dram[bank].start != 0x48000000)
 			continue;
 
-		/* Delete duplicate node, start again */
-		fdt_del_node(blob, mem);
-		first_mem_node = 0;
-		mem = 0;
+		/*
+		 * If this U-Boot runs in EL3, make the bottom 128 MiB
+		 * available for loading of follow up firmware blobs.
+		 */
+		gd->bd->bi_dram[bank].start -= 0x8000000;
+		gd->bd->bi_dram[bank].size += 0x8000000;
+		break;
 	}
-}
-
-static void update_rpc_status(void *blob)
-{
-	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
-	int offset, enabled;
-
-	/*
-	 * Check if the DT fragment received from TF-A had its RPC-IF device node
-	 * enabled.
-	 */
-	if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
-		return;
-
-	offset = fdt_path_offset(atf_fdt_blob, FDT_RPC_PATH);
-	if (offset < 0)
-		return;
-
-	enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset);
-	if (!enabled)
-		return;
 
-	/*
-	 * Find the RPC-IF device node, and enable it if it has a flash subnode.
-	 */
-	offset = fdt_path_offset(blob, FDT_RPC_PATH);
-	if (offset < 0)
-		return;
-
-	if (fdt_subnode_offset(blob, offset, "flash") < 0)
-		return;
-
-	fdt_status_okay(blob, offset);
+	return 0;
 }
 
-int ft_board_setup(void *blob, struct bd_info *bd)
+int __weak board_init(void)
 {
-	apply_atf_overlay(blob);
-	scrub_duplicate_memory(blob);
-	update_rpc_status(blob);
-
 	return 0;
 }
-#endif
+
 #endif
diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/rcar-common/gen3-common.c
new file mode 100644
index 00000000000..4291e1d5bcb
--- /dev/null
+++ b/board/renesas/rcar-common/gen3-common.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * board/renesas/rcar-common/gen3-common.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <[email protected]>
+ * Copyright (C) 2015 Nobuhiro Iwamatsu <[email protected]>
+ */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/uclass-internal.h>
+#include <asm/arch/renesas.h>
+#include <linux/libfdt.h>
+
+#ifdef CONFIG_RCAR_64
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */
+extern u64 rcar_atf_boot_args[];
+
+#define FDT_RPC_PATH	"/soc/spi@ee200000"
+
+static void apply_atf_overlay(void *fdt_blob)
+{
+	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+	if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+		fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0);
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+	apply_atf_overlay((void *)fdt_blob);
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CA57_CODE	0xA5A5000F
+#define RST_CA53_CODE	0x5A5A000F
+
+void __weak reset_cpu(void)
+{
+	unsigned long midr, cputype;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (midr));
+	cputype = (midr >> 4) & 0xfff;
+
+	if (cputype == 0xd03)
+		writel(RST_CA53_CODE, RST_CA53RESCNT);
+	else if (cputype == 0xd07)
+		writel(RST_CA57_CODE, RST_CA57RESCNT);
+	else
+		hang();
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
+{
+	struct fdt_resource first_mem_res, curr_mem_res;
+	int curr_mem_reg, first_mem_reg = 0;
+	int ret;
+
+	for (;;) {
+		ret = fdt_get_resource(blob, first_mem_node, "reg",
+				       first_mem_reg++, &first_mem_res);
+		if (ret) /* No more entries, no overlap found */
+			return 0;
+
+		curr_mem_reg = 0;
+		for (;;) {
+			ret = fdt_get_resource(blob, curr_mem_node, "reg",
+					       curr_mem_reg++, &curr_mem_res);
+			if (ret) /* No more entries, check next tuple */
+				break;
+
+			if (curr_mem_res.end < first_mem_res.start)
+				continue;
+
+			if (curr_mem_res.start >= first_mem_res.end)
+				continue;
+
+			log_debug("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n",
+				  first_mem_res.start, first_mem_res.end,
+				  curr_mem_res.start, curr_mem_res.end);
+
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static void scrub_duplicate_memory(void *blob)
+{
+	/*
+	 * Scrub duplicate /memory@* node entries here. Some R-Car DTs might
+	 * contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
+	 * either generates single /memory node or updates the first /memory
+	 * node. Any remaining memory nodes are thus potential duplicates.
+	 *
+	 * However, it is not possible to delete all the memory nodes right
+	 * away, since some of those might not be DRAM memory nodes, but some
+	 * sort of other memory. Thus, delete only the memory nodes which are
+	 * in the R-Car3 DBSC ranges.
+	 */
+	int mem = 0, first_mem_node = 0;
+
+	for (;;) {
+		mem = fdt_node_offset_by_prop_value(blob, mem,
+						    "device_type", "memory", 7);
+		if (mem < 0)
+			break;
+		if (!fdtdec_get_is_enabled(blob, mem))
+			continue;
+
+		/* First memory node, patched by U-Boot */
+		if (!first_mem_node) {
+			first_mem_node = mem;
+			continue;
+		}
+
+		/* Check the remaining nodes and delete duplicates */
+		if (!is_mem_overlap(blob, first_mem_node, mem))
+			continue;
+
+		/* Delete duplicate node, start again */
+		fdt_del_node(blob, mem);
+		first_mem_node = 0;
+		mem = 0;
+	}
+}
+
+static void update_rpc_status(void *blob)
+{
+	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+	int offset, enabled;
+
+	/*
+	 * Check if the DT fragment received from TF-A had its RPC-IF device node
+	 * enabled.
+	 */
+	if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+		return;
+
+	offset = fdt_path_offset(atf_fdt_blob, FDT_RPC_PATH);
+	if (offset < 0)
+		return;
+
+	enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset);
+	if (!enabled)
+		return;
+
+	/*
+	 * Find the RPC-IF device node, and enable it if it has a flash subnode.
+	 */
+	offset = fdt_path_offset(blob, FDT_RPC_PATH);
+	if (offset < 0)
+		return;
+
+	if (fdt_subnode_offset(blob, offset, "flash") < 0)
+		return;
+
+	fdt_status_okay(blob, offset);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	apply_atf_overlay(blob);
+	scrub_duplicate_memory(blob);
+	update_rpc_status(blob);
+
+	return 0;
+}
+#endif
+#endif
diff --git a/board/renesas/grayhawk/grayhawk.c b/board/renesas/rcar-common/gen4-common.c
index 6c8fca89679..2abe9660cf8 100644
--- a/board/renesas/grayhawk/grayhawk.c
+++ b/board/renesas/rcar-common/gen4-common.c
@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * board/renesas/grayhawk/grayhawk.c
- *     This file is Gray Hawk board support.
+ * board/renesas/rcar-common/gen4-common.c
  *
- * Copyright (C) 2023 Renesas Electronics Corp.
+ * Copyright (C) 2021-2024 Renesas Electronics Corp.
  */
 
 #include <asm/arch/renesas.h>
@@ -12,8 +11,12 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/processor.h>
-#include <linux/errno.h>
 #include <asm/system.h>
+#include <linux/errno.h>
+
+#define RST_BASE	0xE6160000 /* Domain0 */
+#define RST_WDTRSTCR	(RST_BASE + 0x10)
+#define RST_RWDT	0xA55A8002
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,8 +62,29 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	if (current_el() == 3)
-		init_gic_v3();
+	if (current_el() != 3)
+		return 0;
+	init_gic_v3();
 
+	/* Enable RWDT reset on V3U in EL3 */
+	if (IS_ENABLED(CONFIG_R8A779A0) &&
+	    renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779A0) {
+		writel(RST_RWDT, RST_WDTRSTCR);
+	}
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000 /* Domain0 */
+#define RST_SRESCR0	(RST_BASE + 0x18)
+#define RST_SPRES	0x5AA58000
+
+void __weak reset_cpu(void)
+{
+	writel(RST_SPRES, RST_SRESCR0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
 	return 0;
 }
diff --git a/board/renesas/rcar-common/gen4-spl.c b/board/renesas/rcar-common/gen4-spl.c
new file mode 100644
index 00000000000..2aca8baf3dd
--- /dev/null
+++ b/board/renesas/rcar-common/gen4-spl.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car Gen4 Cortex-R52 SPL
+ *
+ * Copyright (C) 2024 Marek Vasut <[email protected]>
+ */
+
+#include <asm/arch/renesas.h>
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <dm/uclass.h>
+#include <dm/util.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <linux/bitops.h>
+#include <log.h>
+#include <mapmem.h>
+#include <spl.h>
+
+#define CNTCR_EN	BIT(0)
+
+#ifdef CONFIG_SPL_BUILD
+void board_debug_uart_init(void)
+{
+}
+#endif
+
+static void init_generic_timer(void)
+{
+	const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+	/* Update memory mapped and register based freqency */
+	if (IS_ENABLED(CONFIG_ARM64))
+		asm volatile("msr cntfrq_el0, %0" :: "r" (freq));
+	else
+		asm volatile("mcr p15, 0, %0, c14, c0, 0" :: "r" (freq));
+
+	writel(freq, CNTFID0);
+
+	/* Enable counter */
+	setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+		ret = spl_early_init();
+		if (ret) {
+			debug("spl_early_init() failed: %d\n", ret);
+			hang();
+		}
+	}
+
+	preloader_console_init();
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e6780000", &dev);
+	if (ret)
+		printf("DBSC5 init failed: %d\n", ret);
+
+	ret = uclass_get_device_by_name(UCLASS_RAM, "ram@ffec0000", &dev);
+	if (ret)
+		printf("RTVRAM init failed: %d\n", ret);
+};
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_SPI;
+}
+
+struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	debug("image entry point: 0x%lx\n", spl_image->entry_point);
+	if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) {
+		typedef void (*image_entry_arg_t)(int, int, int, int)
+			__attribute__ ((noreturn));
+		image_entry_arg_t image_entry =
+			(image_entry_arg_t)(uintptr_t) spl_image->entry_point;
+		image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0);
+	} else {
+		typedef void __noreturn (*image_entry_noargs_t)(void);
+		image_entry_noargs_t image_entry =
+			(image_entry_noargs_t)spl_image->entry_point;
+		image_entry();
+	}
+}
+
+#define APMU_BASE 0xe6170000U
+#define CL0GRP3_BIT			BIT(3)
+#define CL1GRP3_BIT			BIT(7)
+#define RTGRP3_BIT			BIT(19)
+#define APMU_ACC_ENB_FOR_ARM_CPU	(CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
+
+void s_init(void)
+{
+	/* Unlock CPG access */
+	writel(0x5A5AFFFF, CPGWPR);
+	writel(0xA5A50000, CPGWPCR);
+	init_generic_timer();
+
+	/* Define for Work Around of APMU */
+	writel(0x00ff00ff, APMU_BASE + 0x10);
+	writel(0x00ff00ff, APMU_BASE + 0x14);
+	writel(0x00ff00ff, APMU_BASE + 0x18);
+	writel(0x00ff00ff, APMU_BASE + 0x1c);
+	clrbits_le32(APMU_BASE + 0x68, BIT(29));
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile
index 0fc69ba9de6..fe7c78ef2ff 100644
--- a/board/renesas/salvator-x/Makefile
+++ b/board/renesas/salvator-x/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= salvator-x.o ../rcar-common/common.o
+obj-y	:= salvator-x.o ../rcar-common/gen3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/spider/Makefile b/board/renesas/spider/Makefile
index 545cb58a98f..9489917278c 100644
--- a/board/renesas/spider/Makefile
+++ b/board/renesas/spider/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y	:= spider.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/gen4-common.o ../rcar-common/common.o
diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c
deleted file mode 100644
index 414948f1831..00000000000
--- a/board/renesas/spider/spider.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/spider/spider.c
- *     This file is Spider board support.
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <asm/arch/renesas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <linux/errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void init_generic_timer(void)
-{
-	const u32 freq = CONFIG_SYS_CLK_FREQ;
-
-	/* Update memory mapped and register based freqency */
-	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
-	writel(freq, CNTFID0);
-
-	/* Enable counter */
-	setbits_le32(CNTCR_BASE, CNTCR_EN);
-}
-
-static void init_gic_v3(void)
-{
-	 /* GIC v3 power on */
-	writel(BIT(1), GICR_LPI_PWRR);
-
-	/* Wait till the WAKER_CA_BIT changes to 0 */
-	clrbits_le32(GICR_LPI_WAKER, BIT(1));
-	while (readl(GICR_LPI_WAKER) & BIT(2))
-		;
-
-	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
-}
-
-void s_init(void)
-{
-	if (current_el() == 3)
-		init_generic_timer();
-}
-
-int board_early_init_f(void)
-{
-	/* Unlock CPG access */
-	writel(0x5A5AFFFF, CPGWPR);
-	writel(0xA5A50000, CPGWPCR);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	if (current_el() == 3)
-		init_gic_v3();
-
-	return 0;
-}
diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile
index ec2f161feae..c3c2f391e55 100644
--- a/board/renesas/ulcb/Makefile
+++ b/board/renesas/ulcb/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ulcb.o cpld.o ../rcar-common/common.o
+obj-y	:= ulcb.o cpld.o ../rcar-common/gen3-common.o ../rcar-common/common.o
 endif
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
index b29114c7239..ee04f67d986 100644
--- a/board/renesas/v3hsk/Makefile
+++ b/board/renesas/v3hsk/Makefile
@@ -10,6 +10,6 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o
 obj-$(CONFIG_SYSRESET)	+= cpld.o
 endif
diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile
index f8c4bcdcf9f..63e06a4b5fd 100644
--- a/board/renesas/v3msk/Makefile
+++ b/board/renesas/v3msk/Makefile
@@ -10,6 +10,6 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../rcar-common/gen3-spl.o
 else
-obj-y	:= ../rcar-common/v3-common.o ../rcar-common/common.o
+obj-y	:= ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o
 obj-$(CONFIG_SYSRESET)	+= cpld.o
 endif
diff --git a/board/renesas/whitehawk/Makefile b/board/renesas/whitehawk/Makefile
index ed5bdc04e01..80f92e6b041 100644
--- a/board/renesas/whitehawk/Makefile
+++ b/board/renesas/whitehawk/Makefile
@@ -6,4 +6,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y	:= whitehawk.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y	:= ../rcar-common/gen4-spl.o
+else
+obj-y	:= ../rcar-common/gen4-common.o ../rcar-common/common.o
+endif
diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c
deleted file mode 100644
index 3a10b0220d1..00000000000
--- a/board/renesas/whitehawk/whitehawk.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board/renesas/whitehawk/whitehawk.c
- *     This file is White Hawk board support.
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-#include <asm/arch/renesas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/processor.h>
-#include <linux/errno.h>
-#include <asm/system.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void init_generic_timer(void)
-{
-	const u32 freq = CONFIG_SYS_CLK_FREQ;
-
-	/* Update memory mapped and register based freqency */
-	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
-	writel(freq, CNTFID0);
-
-	/* Enable counter */
-	setbits_le32(CNTCR_BASE, CNTCR_EN);
-}
-
-static void init_gic_v3(void)
-{
-	/* GIC v3 power on */
-	writel(BIT(1), GICR_LPI_PWRR);
-
-	/* Wait till the WAKER_CA_BIT changes to 0 */
-	clrbits_le32(GICR_LPI_WAKER, BIT(1));
-	while (readl(GICR_LPI_WAKER) & BIT(2))
-		;
-
-	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
-}
-
-void s_init(void)
-{
-	if (current_el() == 3)
-		init_generic_timer();
-}
-
-int board_early_init_f(void)
-{
-	/* Unlock CPG access */
-	writel(0x5A5AFFFF, CPGWPR);
-	writel(0xA5A50000, CPGWPCR);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	if (current_el() == 3)
-		init_gic_v3();
-
-	return 0;
-}
diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig
index c5a28ff0220..fe230971e97 100644
--- a/board/siemens/capricorn/Kconfig
+++ b/board/siemens/capricorn/Kconfig
@@ -1,4 +1,5 @@
-if TARGET_GIEDI
+if TARGET_CAPRICORN
+
 
 config SYS_BOARD
 	default "capricorn"
@@ -7,24 +8,18 @@ config SYS_VENDOR
 	default "siemens"
 
 config SYS_CONFIG_NAME
-	default "giedi"
+	default "capricorn-common"
 
 config IMX_CONFIG
 	default "board/siemens/capricorn/imximage.cfg"
-endif
 
-if TARGET_DENEB
-
-config SYS_BOARD
-	default "capricorn"
-
-config SYS_VENDOR
-	default "siemens"
+endif
 
-config SYS_CONFIG_NAME
-	default "deneb"
 
-config IMX_CONFIG
-	default "board/siemens/capricorn/imximage.cfg"
+config SPL_CMT
+	bool "Enable Siemens SPL RAM test"
+	depends on SPL
+	help
+	  Enable SIemens SPL RAM test.
 
-endif
+source "board/siemens/common/Kconfig"
diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS
index b4c52032cc9..5f467aa9b6e 100644
--- a/board/siemens/capricorn/MAINTAINERS
+++ b/board/siemens/capricorn/MAINTAINERS
@@ -1,10 +1,12 @@
 CAPRICORN BOARD
+M:	Alexander Sverdlin <[email protected]>
 M:	Anatolij Gustschin <[email protected]>
+M:	Heiko Schocher <[email protected]>
+M:	Walter Schweizer <[email protected]>
 S:	Maintained
+F:	arch/arm/dts/imx8-capricorn-cxg3.dts
+F:	arch/arm/dts/imx8-capricorn-u-boot.dtsi
+F:	arch/arm/dts/imx8-capricorn.dtsi
 F:	board/siemens/capricorn/
+F:	configs/capricorn_cxg3_defconfig
 F:	include/configs/capricorn-common.h
-F:	include/configs/deneb.h
-F:	include/configs/giedi.h
-F:	include/configs/siemens-env-common.h
-F:	configs/deneb_defconfig
-F:	configs/giedi_defconfig
diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile
index e8a24c448b9..a03d54ef3b3 100644
--- a/board/siemens/capricorn/Makefile
+++ b/board/siemens/capricorn/Makefile
@@ -8,6 +8,8 @@ obj-y += ../common/eeprom.o
 
 ifdef CONFIG_XPL_BUILD
 obj-y += spl.o
+obj-$(CONFIG_SPL_CMT) += spl_memory_test.o
 else
 obj-y += ../common/factoryset.o
+obj-$(CONFIG_DDR_SI_TEST) += ../common/ddr_si_test.o
 endif
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c
index ad474d9baa0..390a7b0d841 100644
--- a/board/siemens/capricorn/board.c
+++ b/board/siemens/capricorn/board.c
@@ -26,6 +26,7 @@
 #include <asm/arch-imx8/clock.h>
 #endif
 #include <linux/delay.h>
+#include "../common/board.h"
 #include "../common/eeprom.h"
 #include "../common/factoryset.h"
 
@@ -63,8 +64,7 @@ int board_early_init_f(void)
 	sc_pm_clock_rate_t rate = SC_80MHZ;
 	int ret;
 
-	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
-	ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
+	ret = sc_pm_setup_uart(SC_R_UART_2, rate);
 	if (ret)
 		return ret;
 
@@ -73,6 +73,40 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifndef CONFIG_XPL_BUILD
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	sc_faddr_t addr_start, addr_end;
+	sc_faddr_t sdram_1_size, sdram_2_size;
+	sc_err_t sc_err;
+
+	sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end);
+	if (sc_err == SC_ERR_NONE) {
+		if (addr_end < 0x100000000) {
+			/* only lower RAM available */
+			sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1;
+			sdram_2_size = 0;
+		} else {
+			/* lower RAM (2 GB) und upper RAM available */
+			sdram_1_size = SZ_2G;
+			sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2;
+		}
+	} else {
+		/* Get default in case it would fail */
+		sdram_1_size = PHYS_SDRAM_1_SIZE;
+		sdram_2_size = PHYS_SDRAM_2_SIZE;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	*phys_sdram_1_size = sdram_1_size;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = sdram_2_size;
+}
+#endif /* ! CONFIG_XPL_BUILD */
+
 #define ENET_PHY_RESET	IMX_GPIO_NR(0, 3)
 #define ENET_TEST_1	IMX_GPIO_NR(0, 8)
 #define ENET_TEST_2	IMX_GPIO_NR(0, 9)
@@ -271,11 +305,7 @@ int checkboard(void)
 {
 	puts("Board: Capricorn\n");
 
-	/*
-	 * Running build_info() doesn't work with current SCFW blob.
-	 * Uncomment below call when new blob is available.
-	 */
-	/*build_info();*/
+	build_info();
 
 	print_bootinfo();
 	return 0;
@@ -283,6 +313,32 @@ int checkboard(void)
 
 int board_init(void)
 {
+	struct chip_data eeprom_data = {};
+	char module_name[16];
+	int ret;
+
+	ret = siemens_ee_setup();
+	if (ret) {
+		printf("'siemens_ee_setup' failed, ret: %d\n", ret);
+		goto skip;
+	}
+
+	/* Get module name from EEPROM */
+	siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, module_name,
+			     sizeof(module_name));
+	printf("CPU module: %s\n", module_name);
+
+	ret = siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP,
+				   (uchar *)&eeprom_data,
+				   sizeof(eeprom_data));
+	if (ret) {
+		printf("'siemens_ee_read_data' failed, ret: %d\n", ret);
+		goto skip;
+	}
+
+	printf("HW Version: %s\n", eeprom_data.shwver);
+skip:
+
 	setup_fec();
 	return 0;
 }
diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg
index 4350e2967cc..7fd3fb8b72e 100644
--- a/board/siemens/capricorn/imximage.cfg
+++ b/board/siemens/capricorn/imximage.cfg
@@ -9,13 +9,24 @@
 
 /* Boot from SD, sector size 0x400 */
 BOOT_FROM	sd
+
+/* skip DCD data, as firmware initializes the RAM */
+DCD_SKIP true
+
 /* SoC type IMX8QX */
 SOC_TYPE IMX8QX
-/* Append seco container image */
-APPEND ahab-container.img
+/*
+ * Append seco container image,
+ * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi
+ */
+APPEND mx8qxc0-ahab-container.img
 /* Create the 2nd container */
 CONTAINER
-/* Add scfw image with exec attribute */
-IMAGE SCU capricorn-scfw-tcm.bin
-/* Add ATF image with exec attribute */
+/*
+ * Add scfw image with exec attribute
+ * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi
+ */
+IMAGE SCU mx8qx-mek-scfw-tcm.bin
+
+/* Add SPL image with exec attribute */
 IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c
index 696b5ebd340..5865cde80b4 100644
--- a/board/siemens/capricorn/spl.c
+++ b/board/siemens/capricorn/spl.c
@@ -15,12 +15,31 @@
 #include <dm/uclass-internal.h>
 #include <dm/device-internal.h>
 
+#include <firmware/imx/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include "spl_memory_test.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19)
+static iomux_cfg_t usdhc2_sd_pwr[] = {
+	SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
 void spl_board_init(void)
 {
 	struct udevice *dev;
 
+	uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
 	uclass_find_first_device(UCLASS_MISC, &dev);
 
 	for (; dev; uclass_find_next_device(&dev)) {
@@ -34,8 +53,32 @@ void spl_board_init(void)
 
 	timer_init();
 
+	imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr));
+	gpio_direction_output(USDHC2_SD_PWR, 0);
+
 	preloader_console_init();
+
+	puts("Normal Boot\n");
+
+#if IS_ENABLED(CONFIG_SPL_CMT)
+	spl_siemens_memory_full_test();
+#endif
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	imx8_power_off_pd_devices(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
 }
+#endif
 
 void board_init_f(ulong dummy)
 {
diff --git a/board/siemens/capricorn/spl_memory_test.c b/board/siemens/capricorn/spl_memory_test.c
new file mode 100644
index 00000000000..84c97e7853c
--- /dev/null
+++ b/board/siemens/capricorn/spl_memory_test.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Siemens AG 2020
+ *
+ * SPL Full Memory Test
+ * - memory test through the full DDR area
+ * - refresh over temperature torture (write all, read all)
+ *
+ * Remark:
+ * This test has ran properly with the definition of the RAM sizes in board
+ * headers. Since these headers are removed it's necessary to set the correct
+ * values to PHYS_SDRAM_1_SIZE & PHYS_SDRAM_2_SIZE before to recompile.
+ *
+ * An alternative is to refactor the code to get the size info from system
+ * controller
+ */
+
+#include <init.h>
+#include <log.h>
+
+/* ----- Defines ----- */
+#define CHECK_LOWER_UPPER
+
+#define LEVEL2_PRINT    0x0FFFFFFF
+
+/* use 0x7FFF0000 for shorter loop test */
+#define BASE_OFFSET	0x00000000
+
+/* ----- Types ----- */
+struct ct_t {
+	unsigned long *start;
+	unsigned long *end;
+};
+
+/* ----- Variables ----- */
+static struct ct_t ct;
+static unsigned long error_counter;
+
+static void print_parameters(void)
+{
+	printf("\nstart addr: %p\n", ct.start);
+	printf("end addr  : %p\n", ct.end);
+}
+
+static void run_test(void)
+{
+	/* moved full test in one void */
+	unsigned long *address; /* 512 */
+	unsigned long ebyte1;
+	unsigned long ebyte2;
+	unsigned int i;
+	unsigned long rpattern;
+
+	for (i = 0; i <= 255; i++) {
+		memset(&ebyte1, i, sizeof(ebyte1));
+		ebyte2 = ~ebyte1;
+		printf("LWord: %016lx  #LWord: %016lx\n", ebyte1, ebyte2);
+
+		/* write  all bytes -> duration ~ 150 s */
+		for (address = ct.start; address <= ct.end; address++) {
+#ifdef LEVEL2_PRINT
+			if (((unsigned long)address & LEVEL2_PRINT) == 0)
+				printf("write to %p - %p\n", address,
+				       (void *)((unsigned long)address +
+				       LEVEL2_PRINT));
+#endif
+			*address = ebyte1;
+			address++;
+			*address = ebyte2;
+		}
+
+		/* check all bytes */
+		for (address = ct.start; address <= ct.end; address++) {
+#ifdef LEVEL2_PRINT
+			if (((unsigned long)address & LEVEL2_PRINT) == 0)
+				printf("check from %p - %p\n", address,
+				       (void *)((unsigned long)address +
+				       LEVEL2_PRINT));
+#endif
+
+			rpattern = *address;
+			if (rpattern != ebyte1) {
+				error_counter++;
+				printf("Error! Read: %016lX Wrote: %016lX Address: %p\n",
+				       rpattern, ebyte1, address);
+			}
+
+			address++;
+			rpattern = *address;
+			if (rpattern != ebyte2) {
+				error_counter++;
+				printf("Error! Read: %016lX Wrote: %016lX Address: %p\n",
+				       rpattern, ebyte2, address);
+			}
+		}
+	}
+}
+
+#ifdef CHECK_LOWER_UPPER
+void test_lower_upper(void)
+{
+	/*
+	 * write different values at the same address of both memory areas
+	 * and check them
+	 */
+#define TEST_ADDRESS	 0x12345670UL
+#define LOWER_ADDRESS	(PHYS_SDRAM_1 + TEST_ADDRESS)
+#define UPPER_ADDRESS	(PHYS_SDRAM_2 + TEST_ADDRESS)
+#define LOWER_VALUE	0x0011223344556677
+#define UPPER_VALUE	0x89ab89abffeeddcc
+
+	*(unsigned long *)LOWER_ADDRESS = LOWER_VALUE;
+	*(unsigned long *)UPPER_ADDRESS = UPPER_VALUE;
+
+	puts("\nlower-upper memory area test\n");
+	printf("write %016lx to   lower address %010lx\n", LOWER_VALUE,
+	       LOWER_ADDRESS);
+	printf("write %016lx to   upper address %010lx\n", UPPER_VALUE,
+	       UPPER_ADDRESS);
+	printf("read  %016lx from lower address %010lx\n",
+	       *(unsigned long *)LOWER_ADDRESS, LOWER_ADDRESS);
+	printf("read  %016lx from upper address %010lx\n",
+	       *(unsigned long *)UPPER_ADDRESS, UPPER_ADDRESS);
+}
+#endif
+
+void spl_siemens_memory_full_test(void)
+{
+	unsigned long loopc = 0;
+
+	puts("\nSPL: memory cell test\n");
+
+#ifdef CHECK_LOWER_UPPER
+	if (PHYS_SDRAM_2_SIZE != 0)
+		test_lower_upper();
+#endif
+
+	while (true) {
+		/* imx8x has 2 memory areas up to 2 GB */
+
+		/* 1st memory area @ 0x80000000 */
+		ct.start = (unsigned long *)(PHYS_SDRAM_1 + BASE_OFFSET);
+		ct.end = (unsigned long *)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - 1);
+		print_parameters();
+		run_test();
+
+		/* 2nd memory area @ 0x880000000 */
+		if (PHYS_SDRAM_2_SIZE != 0) {
+			ct.start = (unsigned long *)(PHYS_SDRAM_2 + BASE_OFFSET);
+			ct.end = (unsigned long *)(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE - 1);
+			print_parameters();
+			run_test();
+		}
+
+		loopc++;
+		printf("loop: %ld, errors: %ld\n\n", loopc, error_counter);
+	};
+}
diff --git a/board/siemens/capricorn/spl_memory_test.h b/board/siemens/capricorn/spl_memory_test.h
new file mode 100644
index 00000000000..28df284b6d5
--- /dev/null
+++ b/board/siemens/capricorn/spl_memory_test.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Siemens AG 2020
+ *
+ */
+
+void spl_siemens_memory_full_test(void);
diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig
index 131439fcfea..4ae12b1c973 100644
--- a/board/siemens/common/Kconfig
+++ b/board/siemens/common/Kconfig
@@ -1,2 +1,6 @@
 config FACTORYSET
 	bool
+
+config DDR_SI_TEST
+	bool "DDR signal integrity test implementations"
+	default y
diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h
new file mode 100644
index 00000000000..db34bc78711
--- /dev/null
+++ b/board/siemens/common/board.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common board functions for siemens based boards
+ * (C) Copyright 2022 Siemens Schweiz AG
+ */
+
+#ifndef __COMMON_BOARD_H
+#define __COMMON_BOARD_H
+
+/*
+ * Chip data
+ * Offset in EEPROM: 0x120 - 0x14F
+ *
+ * -----------------------------------------------------------------------------------
+ * | Address range |                          Content                                |
+ * -----------------------------------------------------------------------------------
+ * | 0x120 - 0x123 |  Magic Number - 0x43484950 (4 byte)                             |
+ * -----------------------------------------------------------------------------------
+ * | 0x124 - 0x133 |  Device Nomenclature (15 + 1 byte)                              |
+ * -----------------------------------------------------------------------------------
+ * | 0x134 - 0x13A |  HW Version of the form "v00.00" (6 + 1 byte)                 |
+ * |               |   - First 2 digits: Layout revision (starting from 1)           |
+ * |               |   - Last 2 digits: Assembly variant revision (starting from 1)  |
+ * -----------------------------------------------------------------------------------
+ * | 0x13B - 0x13F |  Flash Size in Gibit (4 + 1 byte)                               |
+ * -----------------------------------------------------------------------------------
+ * | 0x140 - 0x144 |  Ram Size in Gibit (4 + 1 byte)                                 |
+ * -----------------------------------------------------------------------------------
+ * | 0x145 - 0x14F |  Sequence number, equals DMC-code (10 + 1 byte) [OBSOLETE]      |
+ * -----------------------------------------------------------------------------------
+ */
+
+#define MAGIC_CHIP		0x50494843
+#define EEPROM_CHIP_OFFSET	0x120
+
+struct chip_data {
+	unsigned int magic;
+	char sdevname[16];
+	char shwver[7];
+	char flash_size[5];
+	char ram_size[5];
+};
+
+#endif /* __COMMON_BOARD_H */
diff --git a/board/siemens/common/ddr_si_test.c b/board/siemens/common/ddr_si_test.c
new file mode 100644
index 00000000000..c1f523eb3f4
--- /dev/null
+++ b/board/siemens/common/ddr_si_test.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Siemens AG 2023
+ *
+ * DDR signal integrity test
+ *   Check signals on DDR lines
+ *   - signals must be as fast as possible and generate long burst
+ *   - signals must be unidirectional (to DDR or from DDR only)
+ *
+ *   Set pattern: define 2^n 32-bit patterns (up to 4)
+ *   Addresses: must be multiple of 16 to avoid checks in loops
+ *   Test functions
+ *   - write: write pattern to memory area for iteration times
+ *   - read: write pattern once to memory area, read for iteration times
+ */
+
+#include <command.h>
+#include <exports.h>
+#include <time.h>
+#if CONFIG_IS_ENABLED(AM33XX)
+#include <asm/arch-am33xx/hardware_am33xx.h>
+#include <asm/arch-am33xx/cpu.h>
+#include <asm/io.h>
+#endif
+
+/* enable some print for debugging */
+#ifdef PR_DEBUG
+	#define PDEBUG(fmt, args...) printf(fmt, ## args)
+#else
+	#define PDEBUG(fmt, args...)
+#endif
+
+/* define 4 32-bit patterns */
+#define MAX_PTN_SIZE (128)
+#define PTN_ARRAY_SIZE (MAX_PTN_SIZE / (8 * sizeof(u32)))
+
+/* define test direction */
+#define DIR_READ	0
+#define DIR_WRITE	1
+
+static union {
+	u64 l[2];
+	u32 s[4];
+	} test_pattern;
+static int num_ptn32;
+
+#if CONFIG_IS_ENABLED(AM33XX)
+static inline void wdt_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+static inline void wdt_enable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xBBBB, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x4444, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+#else /* ! */
+static inline void wdt_disable(void) {}
+
+static inline void wdt_enable(void) {}
+#endif /* CONFIG_IS_ENABLED(AM33XX) */
+
+static int do_ddr_set_ptn(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	int i, n;
+
+	if (argc < 1)
+		return CMD_RET_USAGE;
+
+	/* number of patterns: 2 exponent */
+	n = argc - 1;
+	if (n > PTN_ARRAY_SIZE || (n & (n - 1)))
+		return CMD_RET_USAGE;
+	num_ptn32 = n;
+
+	/* get patterns */
+	for (i = 0; i < n; i++)
+		test_pattern.s[i] = simple_strtoul(argv[i + 1], NULL, 0);
+
+	printf("Test pattern set\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_ddr_show_ptn(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	if (!num_ptn32) {
+		printf("No pattern available\n");
+	} else {
+		u32 *buf = test_pattern.s;
+		int len = num_ptn32;
+		int i;
+
+		printf("Pattern: ");
+		for (i = 0 ; i < len; i++)
+			printf("0x%08X ", *buf++);
+
+		printf("\n");
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static void ddr_read32(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register volatile u32 *addr = (u32 *)start_addr;
+		register u64 count = n_word;
+
+		while (count) {
+			(void)*addr++;
+			PDEBUG("Read 0x%08X from 0x%p\n", val, addr - 1);
+			count--;
+		}
+	}
+}
+
+static void ddr_read64(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register volatile u64 *addr = (u64 *)start_addr;
+		register u64 count = n_word;
+
+		if (num_ptn32 == 4)
+			count *= 2;
+
+		/*
+		 * 64 & 128 bit pattern. Increase the nummber of read
+		 * commands in the loop to generate longer burst signal
+		 */
+		while (count) {
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			(void)*addr++;
+			PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1);
+			/*
+			 * underflow cannot happen since n_word = end -
+			 * start, end & start addresses are checked to be
+			 * multiple of 16
+			 */
+			count -= 8;
+		}
+	}
+}
+
+static void ddr_write32(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register u32 *addr = (u32 *)start_addr;
+		register u32 ptn = *test_pattern.s;
+		register u64 count = n_word;
+
+		while (count) {
+			PDEBUG("Write 0x%08X to 0x%p\n", ptn, addr);
+			*addr++ = ptn;
+			count--;
+		}
+	}
+}
+
+static void ddr_write64(u64 start_addr, u64 n_word, unsigned long iter)
+{
+	while (iter--) {
+		register u64 *addr = (u64 *)start_addr;
+		register u64 ptnA = test_pattern.l[0];
+		register u64 ptnB = test_pattern.l[1];
+		register u64 count = n_word;
+
+		if (num_ptn32 == 2)
+			ptnB = ptnA;
+		else
+			count *= 2;
+
+		/*
+		 * 64 & 128 bit pattern. Increase the nummber of write
+		 * commands in the loop to generate longer burst signal
+		 */
+		while (count) {
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr);
+			*addr++ = ptnA;
+			PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr);
+			*addr++ = ptnB;
+			/*
+			 * underflow cannot happen since n_word = end -
+			 * start, end & start addresses are checked to be
+			 * multiple of 16
+			 */
+			count -= 8;
+		}
+	}
+}
+
+static int do_ddr_si_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	u64 start_addr, end_addr, n_word;
+	u64 ts_start, ts_end;
+	unsigned long iteration, wr_iter;
+	int direction, i;
+
+	if (argc < 3 || argc > 4)
+		return CMD_RET_USAGE;
+
+	/* get arguments */
+	direction = strcmp(argv[0], "read") ? DIR_WRITE : DIR_READ;
+	start_addr = simple_strtoul(argv[1], NULL, 0);
+	end_addr = simple_strtoul(argv[2], NULL, 0);
+	iteration = simple_strtoul(argv[3], NULL, 10);
+
+	n_word = (end_addr - start_addr) / (num_ptn32 * 4);
+	printf("\nDDR signal integrity %s test: start\n", argv[0]);
+	/* checks */
+	if (start_addr & 0xF) {
+		printf("ERROR: start_address should be 16 bytes aligned\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (end_addr & 0xF) {
+		printf("ERROR: end_address should be 16 bytes aligned\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (start_addr >= end_addr) {
+		printf("ERROR: end_address is not bigger than start_address\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (!iteration) {
+		printf("ERROR: no iteration specified\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (!num_ptn32) {
+		printf("ERROR: no test pattern specified\n\n");
+		return CMD_RET_USAGE;
+	}
+
+	/* print parameters */
+	printf("start_address = 0x%016llX\n", start_addr);
+	printf("end_address   = 0x%016llX\n", end_addr);
+	printf("iterations = %lu\n", iteration);
+
+	/* print pattern */
+	printf("test pattern 0x");
+	for (i = 0; i < num_ptn32; i++)
+		printf("%08X", test_pattern.s[i]);
+
+	printf("\n");
+
+	wdt_disable();
+
+	/* writing */
+	printf("Writing..\n");
+	ts_start = get_timer_us(0);
+
+	if (direction == DIR_READ)
+		wr_iter = 1;
+	else
+		wr_iter = iteration;
+
+	if (num_ptn32 == 1)
+		ddr_write32(start_addr, n_word, wr_iter);
+	else
+		ddr_write64(start_addr, n_word, wr_iter);
+
+	ts_end = get_timer_us(0);
+
+	/* reading */
+	if (direction == DIR_READ) {
+		printf("Reading..\n");
+		/* we need read time, just overwrite */
+		ts_start = get_timer_us(0);
+
+		if (num_ptn32 == 1)
+			ddr_read32(start_addr, n_word, iteration);
+		else
+			ddr_read64(start_addr, n_word, iteration);
+
+		ts_end = get_timer_us(0);
+	}
+
+	wdt_enable();
+
+	/* print stats */
+	printf("DONE.");
+	printf(" Bytes=%llu ", n_word * num_ptn32 * 4 * iteration);
+	printf(" Time=%llu us ", ts_end - ts_start);
+	printf("\nDDR signal integrity %s test: end\n", argv[0]);
+
+	return CMD_RET_SUCCESS;
+}
+
+static char ddr_si_help_text[] =
+	"- DDR signal integrity test\n\n"
+	"ddr_si setptn <pattern> [<pattern>] : set [1,2,4] 32-bit patterns\n"
+	"ddr_si showptn : show patterns\n"
+	"ddr_si read <start> <end> <iterations> : run test for reading\n"
+	"ddr_si write <start> <end> <iterations> : run test for writing\n"
+	"\nWith\n"
+	"\t<pattern>: 32-bit pattern in hex format\n"
+	"\t<start>: test start address in hex format\n"
+	"\t<end>: test end address in hex format\n"
+	"\t<iterations>: number of iterations\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(ddr_si, "DDR si test", ddr_si_help_text,
+			U_BOOT_SUBCMD_MKENT(setptn, 5, 0, do_ddr_set_ptn),
+			U_BOOT_SUBCMD_MKENT(showptn, 1, 0, do_ddr_show_ptn),
+			U_BOOT_SUBCMD_MKENT(read, 4, 0, do_ddr_si_test),
+			U_BOOT_SUBCMD_MKENT(write, 4, 0, do_ddr_si_test));
diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h
index 935f340a8f2..77f35a6ab7b 100644
--- a/board/siemens/draco/board.h
+++ b/board/siemens/draco/board.h
@@ -11,6 +11,8 @@
 #ifndef _BOARD_DRACO_H_
 #define _BOARD_DRACO_H_
 
+#include "../common/board.h"
+
 #define PARGS(x)	#x , /* Parameter Name */ \
 			settings.ddr3.x, /* EEPROM Value */ \
 			ddr3_default.x, /* Default Value */ \
@@ -18,8 +20,6 @@
 
 #define PRINTARGS(y)	printf("%-20s, %8x, %8x, %4d\n", PARGS(y))
 
-#define MAGIC_CHIP	0x50494843
-
 /* Automatic generated definition */
 /* Wed, 16 Apr 2014 16:50:41 +0200 */
 /* From file: draco/[email protected] */
@@ -43,12 +43,6 @@ struct ddr3_data {
 	char manu_marking[32];			/* "default \0" */
 };
 
-struct chip_data {
-	unsigned int  magic;
-	char sdevname[16];
-	char shwver[7];
-};
-
 struct draco_baseboard_id {
 	struct ddr3_data ddr3;
 	struct chip_data chip;
diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
index 3c5dd50c369..c1c374610c3 100644
--- a/board/sifive/unleashed/unleashed.c
+++ b/board/sifive/unleashed/unleashed.c
@@ -114,15 +114,15 @@ int misc_init_r(void)
 
 #endif
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
-		if (gd->arch.firmware_fdt_addr)
-			return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+	if (gd->arch.firmware_fdt_addr) {
+		*fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+
+		return 0;
 	}
 
-	return (ulong *)_end;
+	return -EEXIST;
 }
 
 int board_init(void)
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index c8696270ba2..23e03e145ee 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -10,15 +10,14 @@
 #include <dm.h>
 #include <asm/sections.h>
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
-		if (gd->arch.firmware_fdt_addr)
-			return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+	if (gd->arch.firmware_fdt_addr) {
+		*fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+		return 0;
 	}
 
-	return (ulong *)_end;
+	return -EEXIST;
 }
 
 int board_init(void)
diff --git a/board/silinux/ek874/Makefile b/board/silinux/ek874/Makefile
index 6917a2418ca..879da9edacf 100644
--- a/board/silinux/ek874/Makefile
+++ b/board/silinux/ek874/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_XPL_BUILD
 obj-y	:= ../../renesas/rcar-common/gen3-spl.o
 else
-obj-y	:= ek874.o ../../renesas/rcar-common/common.o
+obj-y	:= ek874.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o
 endif
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index e9269ef5353..b543bf8c1fb 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -385,7 +385,7 @@ static int find_ethernet_phy(void)
 	int phy_addr = -ENOENT;
 
 #ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(ENET_BASE_ADDR, -1);
+	bus = fec_get_miibus(NULL, ENET_BASE_ADDR, -1);
 	if (!bus)
 		return -ENOENT;
 
diff --git a/board/sophgo/licheerv_nano/Kconfig b/board/sophgo/licheerv_nano/Kconfig
new file mode 100644
index 00000000000..660d3c5d095
--- /dev/null
+++ b/board/sophgo/licheerv_nano/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_LICHEERV_NANO
+
+config SYS_BOARD
+	default "licheerv_nano"
+
+config SYS_VENDOR
+	default "sophgo"
+
+config SYS_CPU
+	default "cv1800b"
+
+config SYS_CONFIG_NAME
+	default "licheerv_nano"
+
+config TEXT_BASE
+	default 0x80200000
+
+config ENV_SIZE
+	default 0x20000
+
+config ENV_SECT_SIZE
+	default 0x40000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOPHGO_CV1800B
+
+endif
diff --git a/board/sophgo/licheerv_nano/MAINTAINERS b/board/sophgo/licheerv_nano/MAINTAINERS
new file mode 100644
index 00000000000..c56060db081
--- /dev/null
+++ b/board/sophgo/licheerv_nano/MAINTAINERS
@@ -0,0 +1,5 @@
+LicheeRV Nano
+M:	Thomas Bonnefille <[email protected]>
+S:	Maintained
+F:	board/sophgo/licheerv_nano/
+F:	configs/sipeed_licheerv_nano_defconfig
diff --git a/board/sophgo/licheerv_nano/Makefile b/board/sophgo/licheerv_nano/Makefile
new file mode 100644
index 00000000000..59fcd5bfba9
--- /dev/null
+++ b/board/sophgo/licheerv_nano/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <[email protected]>
+
+obj-y += board.o
diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c
new file mode 100644
index 00000000000..eaa47be1739
--- /dev/null
+++ b/board/sophgo/licheerv_nano/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <[email protected]>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/bananapi-f3/Kconfig
new file mode 100644
index 00000000000..f89fa9af2c7
--- /dev/null
+++ b/board/spacemit/bananapi-f3/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_BANANAPI_F3
+
+config SYS_BOARD
+	default "bananapi-f3"
+
+config SYS_VENDOR
+	default "spacemit"
+
+config SYS_CPU
+	default "k1"
+
+config SYS_CONFIG_NAME
+	default "bananapi-f3"
+
+config TEXT_BASE
+	default 0x00200000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x00000000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SPACEMIT_K1
+
+endif
diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/bananapi-f3/MAINTAINERS
new file mode 100644
index 00000000000..131bad03181
--- /dev/null
+++ b/board/spacemit/bananapi-f3/MAINTAINERS
@@ -0,0 +1,6 @@
+BananaPi F3
+M:	Huan Zhou <pericycle.cc@@gmail.com>
+S:	Maintained
+F:	board/spacemit/bananapi-f3/
+F:	configs/bananapi-f3_defconfig
+F:	doc/board/spacemit/bananapi-f3.rst
diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/bananapi-f3/Makefile
new file mode 100644
index 00000000000..2168698402b
--- /dev/null
+++ b/board/spacemit/bananapi-f3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (c) 2024, Kongyang Liu <[email protected]>
+
+obj-y := board.o
diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c
new file mode 100644
index 00000000000..2631cdd49e0
--- /dev/null
+++ b/board/spacemit/bananapi-f3/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024, Kongyang Liu <[email protected]>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 3fd535e7cfc..22afd76c6b9 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -20,364 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define JH7110_CLK_CPU_ROOT_SHIFT		24
 #define JH7110_CLK_CPU_ROOT_MASK		GENMASK(29, 24)
 
-struct starfive_vf2_pro {
-	const char *path;
-	const char *name;
-	const char *value;
-};
-
-static const struct starfive_vf2_pro milk_v_mars[] = {
-	{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
-	{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
-
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-adj-enabled", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-100-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-1000-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,rx-clk-drv-microamp", "3970"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,rx-data-drv-microamp", "2910"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"rx-internal-delay-ps", "1500"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"tx-internal-delay-ps", "1500"},
-};
-
-static const struct starfive_vf2_pro starfive_vera[] = {
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps",
-		"1900"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps",
-		"1350"}
-};
-
-static const struct starfive_vf2_pro starfive_verb[] = {
-	{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
-	{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
-
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-adj-enabled", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-100-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-1000-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,rx-clk-drv-microamp", "3970"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,rx-data-drv-microamp", "2910"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"rx-internal-delay-ps", "1500"},
-
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,tx-clk-adj-enabled", NULL},
-	{ "/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,tx-clk-100-inverted", NULL},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,rx-clk-drv-microamp", "3970"},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,rx-data-drv-microamp", "2910"},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"rx-internal-delay-ps", "0"},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"tx-internal-delay-ps", "0"},
-};
-
-static const struct starfive_vf2_pro star64_pine64[] = {
-	{"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
-	{"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
-
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-adj-enabled", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-10-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-100-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,tx-clk-1000-inverted", NULL},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,rx-clk-drv-microamp", "2910"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"motorcomm,rx-data-drv-microamp", "2910"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"rx-internal-delay-ps", "1900"},
-	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
-		"tx-internal-delay-ps", "1500"},
-
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,tx-clk-adj-enabled", NULL},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,tx-clk-10-inverted", NULL},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,tx-clk-100-inverted", NULL},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,rx-clk-drv-microamp", "2910"},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"motorcomm,rx-data-drv-microamp", "2910"},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"rx-internal-delay-ps", "0"},
-	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
-		"tx-internal-delay-ps", "300"},
-};
-
-void spl_fdt_fixup_mars(void *fdt)
-{
-	static const char compat[] = "milkv,mars\0starfive,jh7110";
-	u32 phandle;
-	u8 i;
-	int offset;
-	int ret;
-
-	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
-			   "Milk-V Mars");
-
-	/* gmac0 */
-	offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
-	phandle = fdt_get_phandle(fdt, offset);
-	offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
-
-	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
-	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_AONCLK_GMAC0_RMII_RTX);
-
-	/* gmac1 */
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
-			   "status", "disabled");
-
-	for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) {
-		offset = fdt_path_offset(fdt, milk_v_mars[i].path);
-
-		if (milk_v_mars[i].value)
-			ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name,
-					      dectoul(milk_v_mars[i].value, NULL));
-		else
-			ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name);
-
-		if (ret) {
-			pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name);
-				break;
-		}
-	}
-}
-
-void spl_fdt_fixup_mars_cm(void *fdt)
-{
-	const char *compat;
-	const char *model;
-	int compat_size;
-
-	spl_fdt_fixup_mars(fdt);
-
-	if (!get_mmc_size_from_eeprom()) {
-		int offset;
-		static const char
-		compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110";
-
-		model = "Milk-V Mars CM Lite";
-		compat = compat_cm_lite;
-		compat_size = sizeof(compat_cm_lite);
-
-		offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
-		/* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
-		fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
-	} else {
-		static const char
-		compat_cm[] = "milkv,mars-cm\0starfive,jh7110";
-
-		model = "Milk-V Mars CM";
-		compat = compat_cm;
-		compat_size = sizeof(compat_cm);
-	}
-	fdt_setprop(fdt, fdt_path_offset(fdt, "/"),
-		    "compatible", compat, compat_size);
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
-}
-
-void spl_fdt_fixup_version_a(void *fdt)
-{
-	static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110";
-	u32 phandle;
-	u8 i;
-	int offset;
-	int ret;
-
-	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
-			   "StarFive VisionFive 2 v1.2A");
-
-	offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
-	phandle = fdt_get_phandle(fdt, offset);
-	offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
-
-	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX);
-
-	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_SYSCLK_GMAC1_RMII_RTX);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_SYSCLK_GMAC1_RMII_RTX);
-
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
-			   "phy-mode", "rmii");
-
-	for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) {
-		offset = fdt_path_offset(fdt, starfive_vera[i].path);
-
-		if (starfive_vera[i].value)
-			ret = fdt_setprop_u32(fdt, offset,  starfive_vera[i].name,
-					      dectoul(starfive_vera[i].value, NULL));
-		else
-			ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name);
-
-		if (ret) {
-			pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name);
-				break;
-		}
-	}
-}
-
-void spl_fdt_fixup_version_b(void *fdt)
-{
-	static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110";
-	u32 phandle;
-	u8 i;
-	int offset;
-	int ret;
-
-	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
-			   "StarFive VisionFive 2 v1.3B");
-
-	/* gmac0 */
-	offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
-	phandle = fdt_get_phandle(fdt, offset);
-	offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
-
-	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
-	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_AONCLK_GMAC0_RMII_RTX);
-
-	/* gmac1 */
-	offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
-	phandle = fdt_get_phandle(fdt, offset);
-	offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
-
-	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
-	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_SYSCLK_GMAC1_RMII_RTX);
-
-	for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) {
-		offset = fdt_path_offset(fdt, starfive_verb[i].path);
-
-		if (starfive_verb[i].value)
-			ret = fdt_setprop_u32(fdt, offset,  starfive_verb[i].name,
-					      dectoul(starfive_verb[i].value, NULL));
-		else
-			ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name);
-
-		if (ret) {
-			pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name);
-				break;
-		}
-	}
-}
-
-void spl_fdt_fixup_star64(void *fdt)
-{
-	static const char compat[] = "pine64,star64\0starfive,jh7110";
-	u32 phandle;
-	u8 i;
-	int offset;
-	int ret;
-
-	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
-	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
-			   "Pine64 Star64");
-
-	/* gmac0 */
-	offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
-	phandle = fdt_get_phandle(fdt, offset);
-	offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
-
-	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
-	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_AONCLK_GMAC0_RMII_RTX);
-
-	/* gmac1 */
-	offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000");
-	phandle = fdt_get_phandle(fdt, offset);
-	offset = fdt_path_offset(fdt, "/soc/ethernet@16040000");
-
-	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
-	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
-	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
-	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
-			   JH7110_SYSCLK_GMAC1_RMII_RTX);
-
-	for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
-		offset = fdt_path_offset(fdt, star64_pine64[i].path);
-
-		if (star64_pine64[i].value)
-			ret = fdt_setprop_u32(fdt, offset,  star64_pine64[i].name,
-					      dectoul(star64_pine64[i].value, NULL));
-		else
-			ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
-
-		if (ret) {
-			pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
-				break;
-		}
-	}
-}
-
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
-	u8 version;
-	const char *product_id;
-
-	product_id = get_product_id_from_eeprom();
-	if (!product_id) {
-		pr_err("Can't read EEPROM\n");
-		return;
-	}
-	if (!strncmp(product_id, "MARC", 4)) {
-		spl_fdt_fixup_mars_cm(spl_image->fdt_addr);
-	} else if (!strncmp(product_id, "MARS", 4)) {
-		spl_fdt_fixup_mars(spl_image->fdt_addr);
-	} else if (!strncmp(product_id, "VF7110", 6)) {
-		version = get_pcb_revision_from_eeprom();
-		switch (version) {
-		case 'a':
-		case 'A':
-			spl_fdt_fixup_version_a(spl_image->fdt_addr);
-			break;
-
-		case 'b':
-		case 'B':
-		default:
-			spl_fdt_fixup_version_b(spl_image->fdt_addr);
-		break;
-		};
-	} else if (!strncmp(product_id, "STAR64", 6)) {
-		spl_fdt_fixup_star64(spl_image->fdt_addr);
-	} else {
-		pr_err("Unknown product %s\n", product_id);
-	};
-
 	/* Update the memory size which read from eeprom or DT */
 	fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
 }
@@ -466,10 +110,39 @@ void board_init_f(ulong dummy)
 	}
 }
 
-#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+#if CONFIG_IS_ENABLED(LOAD_FIT)
 int board_fit_config_name_match(const char *name)
 {
-	/* boot using first FIT config */
-	return 0;
+	const char *product_id;
+	u8 version;
+
+	product_id = get_product_id_from_eeprom();
+
+	if (!strncmp(product_id, "VF7110", 6)) {
+		version = get_pcb_revision_from_eeprom();
+		if ((version == 'b' || version == 'B') &&
+		    !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b"))
+			return 0;
+
+		if ((version == 'a' || version == 'A') &&
+		    !strcmp(name, "jh7110-starfive-visionfive-2-v1.2a"))
+			return 0;
+	} else if (!strncmp(product_id, "MARS", 4) &&
+		   !strcmp(name, "jh7110-milkv-mars")) {
+		return 0;
+	} else if (!strncmp(product_id, "MARC", 4)) {
+		if (!get_mmc_size_from_eeprom()) {
+			if (!strcmp(name, "jh7110-milkv-mars-cm-lite"))
+				return 0;
+		} else {
+			if (!strcmp(name, "jh7110-milkv-mars-cm"))
+				return 0;
+		}
+	} else if (!strncmp(product_id, "STAR64", 6) &&
+		   !strcmp(name, "jh7110-pine64-star64")) {
+		return 0;
+	}
+
+	return -EINVAL;
 }
 #endif
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index f6114602f88..3940d45b13f 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -115,15 +115,14 @@ int board_late_init(void)
 	return 0;
 }
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
-		if (gd->arch.firmware_fdt_addr)
-			return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+	if (gd->arch.firmware_fdt_addr) {
+		*fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+		return 0;
 	}
 
-	return (ulong *)_end;
+	return -EEXIST;
 }
 
 int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index 97122fb57ba..96d9e1e2797 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,5 +1,6 @@
 #include <env/ti/ti_common.env>
 #include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
 #if CONFIG_CMD_REMOTEPROC
 #include <env/ti/k3_rproc.env>
 #endif
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index de44e4de211..821f02b09fc 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -41,6 +41,7 @@ config TI_COMMON_CMD_OPTIONS
 	imply CMD_I2C
 	imply CMD_MII
 	imply CMD_MMC
+	imply CMD_NFS
 	imply CMD_PART
 	imply CMD_PING
 	imply CMD_PMIC if DM_PMIC
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 2cfeb3bec6c..9bcf67b7bfb 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -326,4 +326,27 @@ int board_late_init(void)
 
 void spl_board_init(void)
 {
+	struct udevice *dev;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_ESM_K3)) {
+		const char * const esms[] = {"esm@700000", "esm@40800000", "esm@42080000"};
+
+		for (int i = 0; i < ARRAY_SIZE(esms); ++i) {
+			ret = uclass_get_device_by_name(UCLASS_MISC, esms[i],
+							&dev);
+			if (ret) {
+				printf("MISC init for %s failed: %d\n", esms[i], ret);
+				break;
+			}
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_ESM_PMIC) && ret == 0) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(pmic_esm),
+						  &dev);
+		if (ret)
+			printf("ESM PMIC init failed: %d\n", ret);
+	}
 }
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 570bf2a27d4..a8c38208693 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -243,25 +243,22 @@ static enum pcb_rev_t get_pcb_revision(void)
 
 static void select_dt_from_module_version(void)
 {
-	env_set("soc", "imx8qm");
-	env_set("variant", "-v1.1");
+	if (get_pcb_revision() == PCB_VERSION_1_0)
+		env_set("variant", "");
+	else
+		env_set("variant", "-v1.1");
 
 	switch (tdx_hw_tag.prodid) {
-	/* Select Apalis iMX8QM device trees */
-	case APALIS_IMX8QM_IT:
-	case APALIS_IMX8QM_WIFI_BT_IT:
-	case APALIS_IMX8QM_8GB_WIFI_BT_IT:
-		if (get_pcb_revision() == PCB_VERSION_1_0)
-			env_set("variant", "");
-		break;
 	/* Select Apalis iMX8QP device trees */
 	case APALIS_IMX8QP_WIFI_BT:
 	case APALIS_IMX8QP:
+	case APALIS_IMX8QP_WIFI_BT_1300MHZ:
+	case APALIS_IMX8QP_1300MHZ:
 		env_set("soc", "imx8qp");
 		break;
 	default:
-		printf("Unknown Apalis iMX8 module\n");
-		return;
+		env_set("soc", "imx8qm");
+		break;
 	}
 }
 
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index a6e3c6afae8..3855e15b83b 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -70,97 +70,100 @@ struct toradex_hw tdx_car_hw_tag;
 #define TARGET_IS_ENABLED(x) IS_ENABLED(CONFIG_TARGET_ ## x)
 
 const struct toradex_som toradex_modules[] = {
-	 [0] = { "UNKNOWN MODULE",                       0                                  },
-	 [1] = { "Colibri PXA270 312MHz",                0                                  },
-	 [2] = { "Colibri PXA270 520MHz",                0                                  },
-	 [3] = { "Colibri PXA320 806MHz",                0                                  },
-	 [4] = { "Colibri PXA300 208MHz",                0                                  },
-	 [5] = { "Colibri PXA310 624MHz",                0                                  },
-	 [6] = { "Colibri PXA320IT 806MHz",              0                                  },
-	 [7] = { "Colibri PXA300 208MHz XT",             0                                  },
-	 [8] = { "Colibri PXA270 312MHz",                0                                  },
-	 [9] = { "Colibri PXA270 520MHz",                0                                  },
-	[10] = { "Colibri VF50 128MB",                   TARGET_IS_ENABLED(COLIBRI_VF)      },
-	[11] = { "Colibri VF61 256MB",                   TARGET_IS_ENABLED(COLIBRI_VF)      },
-	[12] = { "Colibri VF61 256MB IT",                TARGET_IS_ENABLED(COLIBRI_VF)      },
-	[13] = { "Colibri VF50 128MB IT",                TARGET_IS_ENABLED(COLIBRI_VF)      },
-	[14] = { "Colibri iMX6S 256MB",                  TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[15] = { "Colibri iMX6DL 512MB",                 TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[16] = { "Colibri iMX6S 256MB IT",               TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[17] = { "Colibri iMX6DL 512MB IT",              TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[18] = { "UNKNOWN MODULE",                       0                                  },
-	[19] = { "UNKNOWN MODULE",                       0                                  },
-	[20] = { "Colibri T20 256MB",                    TARGET_IS_ENABLED(COLIBRI_T20)     },
-	[21] = { "Colibri T20 512MB",                    TARGET_IS_ENABLED(COLIBRI_T20)     },
-	[22] = { "Colibri T20 512MB IT",                 TARGET_IS_ENABLED(COLIBRI_T20)     },
-	[23] = { "Colibri T30 1GB",                      TARGET_IS_ENABLED(COLIBRI_T30)     },
-	[24] = { "Colibri T20 256MB IT",                 TARGET_IS_ENABLED(COLIBRI_T20)     },
-	[25] = { "Apalis T30 2GB",                       TARGET_IS_ENABLED(APALIS_T30)      },
-	[26] = { "Apalis T30 1GB",                       TARGET_IS_ENABLED(APALIS_T30)      },
-	[27] = { "Apalis iMX6Q 1GB",                     TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[28] = { "Apalis iMX6Q 2GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[29] = { "Apalis iMX6D 512MB",                   TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[30] = { "Colibri T30 1GB IT",                   TARGET_IS_ENABLED(COLIBRI_T30)     },
-	[31] = { "Apalis T30 1GB IT",                    TARGET_IS_ENABLED(APALIS_T30)      },
-	[32] = { "Colibri iMX7S 256MB",                  TARGET_IS_ENABLED(COLIBRI_IMX7)    },
-	[33] = { "Colibri iMX7D 512MB",                  TARGET_IS_ENABLED(COLIBRI_IMX7)    },
-	[34] = { "Apalis TK1 2GB",                       TARGET_IS_ENABLED(APALIS_TK1)      },
-	[35] = { "Apalis iMX6D 1GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[36] = { "Colibri iMX6ULL 256MB",                TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
-	[37] = { "Apalis iMX8QM 4GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
-	[38] = { "Colibri iMX8QXP 2GB WB IT",            TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
-	[39] = { "Colibri iMX7D 1GB",                    TARGET_IS_ENABLED(COLIBRI_IMX7)    },
-	[40] = { "Colibri iMX6ULL 512MB WB IT",          TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
-	[41] = { "Colibri iMX7D 512MB EPDC",             TARGET_IS_ENABLED(COLIBRI_IMX7)    },
-	[42] = { "Apalis TK1 4GB",                       TARGET_IS_ENABLED(APALIS_TK1)      },
-	[43] = { "Colibri T20 512MB IT SETEK",           TARGET_IS_ENABLED(COLIBRI_T20)     },
-	[44] = { "Colibri iMX6ULL 512MB IT",             TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
-	[45] = { "Colibri iMX6ULL 512MB WB",             TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
-	[46] = { "Apalis iMX8QXP 2GB WB IT",             0                                  },
-	[47] = { "Apalis iMX8QM 4GB IT",                 TARGET_IS_ENABLED(APALIS_IMX8)     },
-	[48] = { "Apalis iMX8QP 2GB WB",                 TARGET_IS_ENABLED(APALIS_IMX8)     },
-	[49] = { "Apalis iMX8QP 2GB",                    TARGET_IS_ENABLED(APALIS_IMX8)     },
-	[50] = { "Colibri iMX8QXP 2GB IT",               TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
-	[51] = { "Colibri iMX8DX 1GB WB",                TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
-	[52] = { "Colibri iMX8DX 1GB",                   TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
-	[53] = { "Apalis iMX8QXP 2GB ECC IT",            0                                  },
-	[54] = { "Apalis iMX8DXP 1GB",                   TARGET_IS_ENABLED(APALIS_IMX8)     },
-	[55] = { "Verdin iMX8M Mini Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[56] = { "Verdin iMX8M Nano Quad 1GB WB",        0                                  },
-	[57] = { "Verdin iMX8M Mini DualLite 1GB",       TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[58] = { "Verdin iMX8M Plus Quad 4GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[59] = { "Verdin iMX8M Mini Quad 2GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[60] = { "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[61] = { "Verdin iMX8M Plus Quad 2GB",           TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[62] = { "Colibri iMX6ULL 1GB IT",               TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
-	[63] = { "Verdin iMX8M Plus Quad 4GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[64] = { "Verdin iMX8M Plus Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[65] = { "Verdin iMX8M Plus QuadLite 1GB IT",    TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[66] = { "Verdin iMX8M Plus Quad 8GB WB",        TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[67] = { "Apalis iMX8QM 8GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
-	[68] = { "Verdin iMX8M Mini Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[69] = { "Verdin AM62 Quad 1GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[70] = { "Verdin iMX8M Plus Quad 8GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
-	[71] = { "Verdin AM62 Solo 512MB",               TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[72] = { "Verdin AM62 Solo 512MB WB IT",         TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[73] = { "Verdin AM62 Dual 1GB ET",              TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[74] = { "Verdin AM62 Dual 1GB IT",              TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[75] = { "Verdin AM62 Dual 1GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[76] = { "Verdin AM62 Quad 2GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
-	[77] = { "Colibri iMX6S 256MB",                  TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[78] = { "Colibri iMX6S 256MB IT",               TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[79] = { "Colibri iMX6DL 512MB",                 TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[80] = { "Colibri iMX6DL 512MB IT",              TARGET_IS_ENABLED(COLIBRI_IMX6)    },
-	[81] = { "Colibri iMX7D 512MB",                  TARGET_IS_ENABLED(COLIBRI_IMX7)    },
-	[82] = { "Apalis iMX6D 512MB",                   TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[83] = { "Apalis iMX6Q 1GB",                     TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[84] = { "Apalis iMX6D 1GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[85] = { "Apalis iMX6Q 2GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
-	[86] = { "Verdin iMX8M Mini DualLite 2GB IT",    TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[87] = { "Verdin iMX8M Mini Quad 2GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
-	[88] = { "Aquila AM69 Octa 32GB WB IT",          TARGET_IS_ENABLED(AQUILA_AM69_A72) },
-	[89] = { "Verdin iMX95 Hexa 16GB WB IT",         TARGET_IS_ENABLED(VERDIN_IMX95)    },
-	[90] = { "Verdin iMX8M Mini Quad 4GB WB ET",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ 0,                                     "UNKNOWN MODULE",                       0                                  },
+	{ COLIBRI_PXA270_V1_312MHZ,              "Colibri PXA270 312MHz",                0                                  },
+	{ COLIBRI_PXA270_V1_520MHZ,              "Colibri PXA270 520MHz",                0                                  },
+	{ COLIBRI_PXA320,                        "Colibri PXA320 806MHz",                0                                  },
+	{ COLIBRI_PXA300,                        "Colibri PXA300 208MHz",                0                                  },
+	{ COLIBRI_PXA310,                        "Colibri PXA310 624MHz",                0                                  },
+	{ COLIBRI_PXA320_IT,                     "Colibri PXA320IT 806MHz",              0                                  },
+	{ COLIBRI_PXA300_XT,                     "Colibri PXA300 208MHz XT",             0                                  },
+	{ COLIBRI_PXA270_312MHZ,                 "Colibri PXA270 312MHz",                0                                  },
+	{ COLIBRI_PXA270_520MHZ,                 "Colibri PXA270 520MHz",                0                                  },
+	{ COLIBRI_VF50,                          "Colibri VF50 128MB",                   TARGET_IS_ENABLED(COLIBRI_VF)      },
+	{ COLIBRI_VF61,                          "Colibri VF61 256MB",                   TARGET_IS_ENABLED(COLIBRI_VF)      },
+	{ COLIBRI_VF61_IT,                       "Colibri VF61 256MB IT",                TARGET_IS_ENABLED(COLIBRI_VF)      },
+	{ COLIBRI_VF50_IT,                       "Colibri VF50 128MB IT",                TARGET_IS_ENABLED(COLIBRI_VF)      },
+	{ COLIBRI_IMX6S,                         "Colibri iMX6S 256MB",                  TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX6DL,                        "Colibri iMX6DL 512MB",                 TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX6S_IT,                      "Colibri iMX6S 256MB IT",               TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX6DL_IT,                     "Colibri iMX6DL 512MB IT",              TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_T20_256MB,                     "Colibri T20 256MB",                    TARGET_IS_ENABLED(COLIBRI_T20)     },
+	{ COLIBRI_T20_512MB,                     "Colibri T20 512MB",                    TARGET_IS_ENABLED(COLIBRI_T20)     },
+	{ COLIBRI_T20_512MB_IT,                  "Colibri T20 512MB IT",                 TARGET_IS_ENABLED(COLIBRI_T20)     },
+	{ COLIBRI_T30,                           "Colibri T30 1GB",                      TARGET_IS_ENABLED(COLIBRI_T30)     },
+	{ COLIBRI_T20_256MB_IT,                  "Colibri T20 256MB IT",                 TARGET_IS_ENABLED(COLIBRI_T20)     },
+	{ APALIS_T30_2GB,                        "Apalis T30 2GB",                       TARGET_IS_ENABLED(APALIS_T30)      },
+	{ APALIS_T30_1GB,                        "Apalis T30 1GB",                       TARGET_IS_ENABLED(APALIS_T30)      },
+	{ APALIS_IMX6Q,                          "Apalis iMX6Q 1GB",                     TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ APALIS_IMX6Q_IT,                       "Apalis iMX6Q 2GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ APALIS_IMX6D,                          "Apalis iMX6D 512MB",                   TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ COLIBRI_T30_IT,                        "Colibri T30 1GB IT",                   TARGET_IS_ENABLED(COLIBRI_T30)     },
+	{ APALIS_T30_IT,                         "Apalis T30 1GB IT",                    TARGET_IS_ENABLED(APALIS_T30)      },
+	{ COLIBRI_IMX7S,                         "Colibri iMX7S 256MB",                  TARGET_IS_ENABLED(COLIBRI_IMX7)    },
+	{ COLIBRI_IMX7D,                         "Colibri iMX7D 512MB",                  TARGET_IS_ENABLED(COLIBRI_IMX7)    },
+	{ APALIS_TK1_2GB,                        "Apalis TK1 2GB",                       TARGET_IS_ENABLED(APALIS_TK1)      },
+	{ APALIS_IMX6D_IT,                       "Apalis iMX6D 1GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ COLIBRI_IMX6ULL,                       "Colibri iMX6ULL 256MB",                TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+	{ APALIS_IMX8QM_WIFI_BT_IT,              "Apalis iMX8QM 4GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ COLIBRI_IMX8QXP_WIFI_BT_IT,            "Colibri iMX8QXP 2GB WB IT",            TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
+	{ COLIBRI_IMX7D_EMMC,                    "Colibri iMX7D 1GB",                    TARGET_IS_ENABLED(COLIBRI_IMX7)    },
+	{ COLIBRI_IMX6ULL_WIFI_BT_IT,            "Colibri iMX6ULL 512MB WB IT",          TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+	{ COLIBRI_IMX7D_EPDC,                    "Colibri iMX7D 512MB EPDC",             TARGET_IS_ENABLED(COLIBRI_IMX7)    },
+	{ APALIS_TK1_4GB,                        "Apalis TK1 4GB",                       TARGET_IS_ENABLED(APALIS_TK1)      },
+	{ COLIBRI_T20_512MB_IT_SETEK,            "Colibri T20 512MB IT SETEK",           TARGET_IS_ENABLED(COLIBRI_T20)     },
+	{ COLIBRI_IMX6ULL_IT,                    "Colibri iMX6ULL 512MB IT",             TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+	{ COLIBRI_IMX6ULL_WIFI_BT,               "Colibri iMX6ULL 512MB WB",             TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+	{ APALIS_IMX8QXP_WIFI_BT_IT,             "Apalis iMX8QXP 2GB WB IT",             0                                  },
+	{ APALIS_IMX8QM_IT,                      "Apalis iMX8QM 4GB IT",                 TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ APALIS_IMX8QP_WIFI_BT,                 "Apalis iMX8QP 2GB WB",                 TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ APALIS_IMX8QP,                         "Apalis iMX8QP 2GB",                    TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ COLIBRI_IMX8QXP_IT,                    "Colibri iMX8QXP 2GB IT",               TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
+	{ COLIBRI_IMX8DX_WIFI_BT,                "Colibri iMX8DX 1GB WB",                TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
+	{ COLIBRI_IMX8DX,                        "Colibri iMX8DX 1GB",                   TARGET_IS_ENABLED(COLIBRI_IMX8X)   },
+	{ APALIS_IMX8QXP,                        "Apalis iMX8QXP 2GB ECC IT",            0                                  },
+	{ APALIS_IMX8DXP,                        "Apalis iMX8DXP 1GB",                   0                                  },
+	{ VERDIN_IMX8MMQ_WIFI_BT_IT,             "Verdin iMX8M Mini Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ VERDIN_IMX8MNQ_WIFI_BT,                "Verdin iMX8M Nano Quad 1GB WB",        0                                  },
+	{ VERDIN_IMX8MMDL,                       "Verdin iMX8M Mini DualLite 1GB",       TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ VERDIN_IMX8MPQ_WIFI_BT_IT,             "Verdin iMX8M Plus Quad 4GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ VERDIN_IMX8MMQ_IT,                     "Verdin iMX8M Mini Quad 2GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ VERDIN_IMX8MMDL_WIFI_BT_IT,            "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ VERDIN_IMX8MPQ,                        "Verdin iMX8M Plus Quad 2GB",           TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ COLIBRI_IMX6ULL_IT_EMMC,               "Colibri iMX6ULL 1GB IT",               TARGET_IS_ENABLED(COLIBRI_IMX6ULL) },
+	{ VERDIN_IMX8MPQ_IT,                     "Verdin iMX8M Plus Quad 4GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ VERDIN_IMX8MPQ_2GB_WIFI_BT_IT,         "Verdin iMX8M Plus Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ VERDIN_IMX8MPQL_IT,                    "Verdin iMX8M Plus QuadLite 1GB IT",    TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ VERDIN_IMX8MPQ_8GB_WIFI_BT,            "Verdin iMX8M Plus Quad 8GB WB",        TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ APALIS_IMX8QM_8GB_WIFI_BT_IT,          "Apalis iMX8QM 8GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN,      "Verdin iMX8M Mini Quad 2GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ VERDIN_AM62Q_WIFI_BT_IT,               "Verdin AM62 Quad 1GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ VERDIN_IMX8MPQ_8GB_WIFI_BT_IT,         "Verdin iMX8M Plus Quad 8GB WB IT",     TARGET_IS_ENABLED(VERDIN_IMX8MP)   },
+	{ VERDIN_AM62S_512MB,                    "Verdin AM62 Solo 512MB",               TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ VERDIN_AM62S_512MB_WIFI_BT_IT,         "Verdin AM62 Solo 512MB WB IT",         TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ VERDIN_AM62D_1G_ET,                    "Verdin AM62 Dual 1GB ET",              TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ VERDIN_AM62D_1G_IT,                    "Verdin AM62 Dual 1GB IT",              TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ VERDIN_AM62D_1G_WIFI_BT_IT,            "Verdin AM62 Dual 1GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ VERDIN_AM62Q_2G_WIFI_BT_IT,            "Verdin AM62 Quad 2GB WB IT",           TARGET_IS_ENABLED(VERDIN_AM62_A53) },
+	{ COLIBRI_IMX6S_NOWINCE,                 "Colibri iMX6S 256MB",                  TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX6S_IT_NOWINCE,              "Colibri iMX6S 256MB IT",               TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX6DL_NOWINCE,                "Colibri iMX6DL 512MB",                 TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX6DL_IT_NOWINCE,             "Colibri iMX6DL 512MB IT",              TARGET_IS_ENABLED(COLIBRI_IMX6)    },
+	{ COLIBRI_IMX7D_NOWINCE,                 "Colibri iMX7D 512MB",                  TARGET_IS_ENABLED(COLIBRI_IMX7)    },
+	{ APALIS_IMX6D_NOWINCE,                  "Apalis iMX6D 512MB",                   TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ APALIS_IMX6Q_NOWINCE,                  "Apalis iMX6Q 1GB",                     TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ APALIS_IMX6D_IT_NOWINCE,               "Apalis iMX6D 1GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ APALIS_IMX6Q_IT_NOWINCE,               "Apalis iMX6Q 2GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
+	{ VERDIN_IMX8MMDL_2G_IT,                 "Verdin iMX8M Mini DualLite 2GB IT",    TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ VERDIN_IMX8MMQ_2G_IT_NO_CAN,           "Verdin iMX8M Mini Quad 2GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ AQUILA_AM69O_32G_WIFI_BT_IT,           "Aquila AM69 Octa 32GB WB IT",          TARGET_IS_ENABLED(AQUILA_AM69_A72) },
+	{ VERDIN_IMX95H_16G_WIFI_BT_IT,          "Verdin iMX95 Hexa 16GB WB IT",         TARGET_IS_ENABLED(VERDIN_IMX95)    },
+	{ VERDIN_IMX8MMQ_4G_WIFI_BT_ET,          "Verdin iMX8M Mini Quad 4GB WB ET",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	{ APALIS_IMX8QM_WIFI_BT_IT_1300MHZ,      "Apalis iMX8QM 4GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ APALIS_IMX8QM_IT_1300MHZ,              "Apalis iMX8QM 4GB IT",                 TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ APALIS_IMX8QP_WIFI_BT_1300MHZ,         "Apalis iMX8QP 2GB WB",                 TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ APALIS_IMX8QP_1300MHZ,                 "Apalis iMX8QP 2GB",                    TARGET_IS_ENABLED(APALIS_IMX8)     },
+	{ APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ,  "Apalis iMX8QM 8GB WB IT",              TARGET_IS_ENABLED(APALIS_IMX8)     },
 };
 
 struct pid4list {
@@ -188,6 +191,20 @@ const u32 toradex_ouis[] = {
 	[1] = 0x8c06cbUL,
 };
 
+int get_toradex_modules_idx(int pid4)
+{
+	int i, index = 0;
+
+	for (i = 1; i < ARRAY_SIZE(toradex_modules); i++) {
+		if (pid4 == toradex_modules[i].pid4) {
+			index = i;
+			break;
+		}
+	}
+
+	return index;
+}
+
 const char * const get_toradex_carrier_boards(int pid4)
 {
 	int i, index = 0;
@@ -361,7 +378,7 @@ static int write_tdx_cfg_block_to_eeprom(unsigned char *config_block)
 
 int read_tdx_cfg_block(void)
 {
-	int ret = 0;
+	int idx, ret = 0;
 	u8 *config_block = NULL;
 	struct toradex_tag *tag;
 	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
@@ -430,7 +447,8 @@ int read_tdx_cfg_block(void)
 	}
 
 	/* Cap product id to avoid issues with a yet unknown one */
-	if (tdx_hw_tag.prodid >= ARRAY_SIZE(toradex_modules))
+	idx = get_toradex_modules_idx(tdx_hw_tag.prodid);
+	if (!toradex_modules[idx].pid4)
 		tdx_hw_tag.prodid = 0;
 
 out:
@@ -456,19 +474,21 @@ static int get_cfgblock_interactive(void)
 	int len = 0;
 	int ret = 0;
 	unsigned int prodid;
-	int i;
+	int i, idx;
 
 	printf("Enabled modules:\n");
 	for (i = 0; i < ARRAY_SIZE(toradex_modules); i++) {
 		if (toradex_modules[i].is_enabled)
-			printf(" %04d %s\n", i, toradex_modules[i].name);
+			printf(" %04d %s\n", toradex_modules[i].pid4,
+			       toradex_modules[i].name);
 	}
 
 	sprintf(message, "Enter the module ID: ");
 	len = cli_readline(message);
 
 	prodid = dectoul(console_buffer, NULL);
-	if (prodid >= ARRAY_SIZE(toradex_modules) || !toradex_modules[prodid].is_enabled) {
+	idx = get_toradex_modules_idx(prodid);
+	if (!toradex_modules[idx].pid4 || !toradex_modules[idx].is_enabled) {
 		printf("Parsing module id failed\n");
 		return -1;
 	}
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 0d6dd1c3a72..eaa52ed24f7 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -21,6 +21,7 @@ struct toradex_eth_addr {
 } __attribute__((__packed__));
 
 struct toradex_som {
+	int pid4;
 	const char *name;
 	int is_enabled;
 };
@@ -116,6 +117,11 @@ enum {
 	AQUILA_AM69O_32G_WIFI_BT_IT,
 	VERDIN_IMX95H_16G_WIFI_BT_IT,
 	VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */
+	APALIS_IMX8QM_WIFI_BT_IT_1300MHZ,
+	APALIS_IMX8QM_IT_1300MHZ,
+	APALIS_IMX8QP_WIFI_BT_1300MHZ,
+	APALIS_IMX8QP_1300MHZ,
+	APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, /* 95 */
 };
 
 enum {
@@ -139,6 +145,7 @@ extern u32 tdx_car_serial;
 
 int read_tdx_cfg_block(void);
 int read_tdx_cfg_block_carrier(void);
+int get_toradex_modules_idx(int pid4);
 const char * const get_toradex_carrier_boards(int pid4);
 const char * const get_toradex_display_adapters(int pid4);
 int try_migrate_tdx_cfg_block_carrier(void);
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index a6b45cdab81..f01fb369b4b 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -191,13 +191,16 @@ static int tdx_detect(struct udevice *dev)
 static int tdx_get_str(struct udevice *dev, int id, size_t size, char *val)
 {
 	int ret = -ENOTSUPP;
+	int idx;
 
 	switch (id) {
-	case SYSINFO_ID_BOARD_MODEL:
+	case SYSID_BOARD_MODEL:
+		idx = get_toradex_modules_idx(tdx_hw_tag.prodid);
+
 		snprintf(val, size,
 			 "Toradex %04d %s %s",
 			 tdx_hw_tag.prodid,
-			 toradex_modules[tdx_hw_tag.prodid].name,
+			 toradex_modules[idx].name,
 			 tdx_board_rev_str);
 
 		ret = 0;
diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c
index 4c3b9c9e278..216a022aa15 100644
--- a/board/xen/xenguest_arm64/xenguest_arm64.c
+++ b/board/xen/xenguest_arm64/xenguest_arm64.c
@@ -44,14 +44,14 @@ int board_init(void)
  * x0 is the physical address of the device tree blob (dtb) in system RAM.
  * This is stored in rom_pointer during low level init.
  */
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
-	*err = 0;
-	if (fdt_magic(rom_pointer[0]) != FDT_MAGIC) {
-		*err = -ENXIO;
-		return NULL;
-	}
-	return (void *)rom_pointer[0];
+	if (fdt_magic(rom_pointer[0]) != FDT_MAGIC)
+		return -ENXIO;
+
+	*fdtp = (void *)rom_pointer[0];
+
+	return 0;
 }
 
 /*
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index a12dccd4c51..deea6c71103 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -358,17 +358,17 @@ __maybe_unused int xilinx_read_eeprom(void)
 }
 
 #if defined(CONFIG_OF_BOARD)
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
 	void *fdt_blob;
 
-	*err = 0;
-
 	if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) {
 		fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
 
-		if (fdt_magic(fdt_blob) == FDT_MAGIC)
-			return fdt_blob;
+		if (fdt_magic(fdt_blob) == FDT_MAGIC) {
+			*fdtp = fdt_blob;
+			return 0;
+		}
 	}
 
 	if (!IS_ENABLED(CONFIG_XPL_BUILD) &&
@@ -376,8 +376,10 @@ void *board_fdt_blob_setup(int *err)
 	    !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
 		fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
 
-		if (fdt_magic(fdt_blob) == FDT_MAGIC)
-			return fdt_blob;
+		if (fdt_magic(fdt_blob) == FDT_MAGIC) {
+			*fdtp = fdt_blob;
+			return 0;
+		}
 
 		debug("DTB is not passed via %p\n", fdt_blob);
 	}
@@ -396,13 +398,15 @@ void *board_fdt_blob_setup(int *err)
 		fdt_blob = (ulong *)_end;
 	}
 
-	if (fdt_magic(fdt_blob) == FDT_MAGIC)
-		return fdt_blob;
+	if (fdt_magic(fdt_blob) == FDT_MAGIC) {
+		*fdtp = fdt_blob;
+
+		return 0;
+	}
 
 	debug("DTB is also not passed via %p\n", fdt_blob);
 
-	*err = -EINVAL;
-	return NULL;
+	return -EINVAL;
 }
 #endif