diff options
| author | Tom Rini <[email protected]> | 2026-02-03 17:36:07 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-02-03 18:13:54 -0600 |
| commit | 3c72973b7a7fbc3f57b20bf2e2e630ba9d31a686 (patch) | |
| tree | 59a8328c97c1428d41ab68671956ead21124950d /board | |
| parent | ede7198a37019266bfc4a992bdd22292196a97f9 (diff) | |
| parent | 800ebf7e94e3a7e375cf915ae21e14514fd81450 (diff) | |
Merge branch 'u-boot-nand-03022026' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/29183
This series provides a comprehensive cleanup of the Allwinner (sunxi)
NAND controller drivers and introduces full support for the H6 and H616
SoCs in both the main U-Boot driver and the SPL.
The series successfully deduplicates register maps between sunxi_nand.c
and sunxi_nand_spl.c while migrating to a capability-based architecture.
This approach allows the driver to handle the H616's specific
requirements—such as shifted register offsets for ECC/OOB, the removal
of 512B ECC block support, and mandatory MBUS clock gating—without
breaking compatibility for legacy A10/A23 devices.
Diffstat (limited to 'board')
| -rw-r--r-- | board/sunxi/board.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index e9e3fb9a571..954a8715075 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -307,15 +307,24 @@ static void nand_pinmux_setup(void) static void nand_clock_setup(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + void * const ccm = (void *)SUNXI_CCM_BASE; + +#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_H6) + setbits_le32(ccm + CCU_H6_NAND_GATE_RESET, + (1 << GATE_SHIFT) | (1 << RESET_SHIFT)); + setbits_le32(ccm + CCU_H6_MBUS_GATE, (1 << MBUS_GATE_OFFSET_NAND)); + setbits_le32(ccm + CCU_NAND1_CLK_CFG, CCM_NAND_CTRL_ENABLE | + CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); +#else + setbits_le32(ccm + CCU_AHB_GATE0, + (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I - setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); + setbits_le32(ccm + CCU_AHB_RESET0_CFG, (1 << AHB_GATE_OFFSET_NAND0)); +#endif #endif - setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); + setbits_le32(ccm + CCU_NAND0_CLK_CFG, CCM_NAND_CTRL_ENABLE | + CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); } void board_nand_init(void) |