Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

* Add RISC-V falcon mode documentation
* Add Clang build support
* Add cmd to detect Debug Trigger Extension support

* Add PWM setting for Unmatched board
* Add Milk-V Duo board support
* Add new device node and enable new config option for VisionFive2 board
* Add second virtio device for RISC-V QEMU

7 files changed, 112 insertions, 25 deletions

diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 4e53fee5d23..62b93b4ecba 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -21,8 +21,6 @@
 #include <fdtdec.h>
 #include <dm.h>
 #include <spl.h>
-#include <mapmem.h>
-#include <hang.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,29 +49,6 @@ int misc_init_r(void)
 }
 #endif
 
-#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
-#define ANDES_SPL_FDT_ADDR	(CONFIG_TEXT_BASE - 0x100000)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
-	/*
-	 * Originally, u-boot-spl will place DTB directly after the kernel,
-	 * but the size of the kernel did not include the BSS section, which
-	 * means u-boot-spl will place the DTB in the kernel BSS section
-	 * causing the DTB to be cleared by kernel BSS initializtion.
-	 * Moving DTB in front of the kernel can avoid the error.
-	 */
-	if (ANDES_SPL_FDT_ADDR < 0) {
-		printf("%s: CONFIG_TEXT_BASE needs to be larger than 0x100000\n",
-		       __func__);
-		hang();
-	}
-
-	memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
-	       fdt_totalsize(spl_image->fdt_addr));
-	spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
-}
-#endif
-
 int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 7c0beedc083..e69bed9d99d 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -15,6 +15,29 @@
 #include <asm/gpio.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/spl.h>
+#include <linux/io.h>
+#include <asm/arch/eeprom.h>
+
+struct pwm_sifive_regs {
+	unsigned int cfg;       /* PWM configuration register */
+	unsigned int pad0;      /* Reserved */
+	unsigned int cnt;       /* PWM count register */
+	unsigned int pad1;      /* Reserved */
+	unsigned int pwms;      /* Scaled PWM count register */
+	unsigned int pad2;      /* Reserved */
+	unsigned int pad3;      /* Reserved */
+	unsigned int pad4;      /* Reserved */
+	unsigned int cmp0;      /* PWM 0 compare register */
+	unsigned int cmp1;      /* PWM 1 compare register */
+	unsigned int cmp2;      /* PWM 2 compare register */
+	unsigned int cmp3;      /* PWM 3 compare register */
+};
+
+#define PWM0_BASE               0x10020000
+#define PWM1_BASE               0x10021000
+#define PWM_CFG_INIT            0x1000
+#define PWM_CMP_ENABLE_VAL      0x0
+#define PWM_CMP_DISABLE_VAL     0xffff
 
 #define UBRDG_RESET	SIFIVE_GENERIC_GPIO_NR(0, 7)
 #define ULPI_RESET	SIFIVE_GENERIC_GPIO_NR(0, 9)
@@ -26,6 +49,33 @@
 #define MODE_SELECT_SD		0xb
 #define MODE_SELECT_MASK	GENMASK(3, 0)
 
+void spl_pwm_device_init(void)
+{
+	struct pwm_sifive_regs *pwm0, *pwm1;
+
+	pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+	pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+
+	/* Set the 3-color PWM LEDs to yellow in SPL */
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+	writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
+
+	/* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
+	/* The SoC fan(J21) on the rev3 board cannot be controlled by PWM_COMP0,
+	 *            so here sets the initial value of PWM_COMP0 as DISABLE */
+	if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
+		writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
+	else
+		writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
+
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+	writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
+
 static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
 {
 	int ret;
@@ -90,6 +140,8 @@ int spl_board_init_f(void)
 		goto end;
 	}
 
+	spl_pwm_device_init();
+
 	ret = spl_gemgxl_init();
 	if (ret) {
 		debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
new file mode 100644
index 00000000000..2a458f291cc
--- /dev/null
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_MILKV_DUO
+
+config SYS_BOARD
+	default "milkv_duo"
+
+config SYS_VENDOR
+	default "sophgo"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "milkv_duo"
+
+config TEXT_BASE
+	default 0x80200000
+
+config ENV_SIZE
+	default 0x20000
+
+config ENV_SECT_SIZE
+	default 0x40000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+
+endif
diff --git a/board/sophgo/milkv_duo/MAINTAINERS b/board/sophgo/milkv_duo/MAINTAINERS
new file mode 100644
index 00000000000..651a0592f7a
--- /dev/null
+++ b/board/sophgo/milkv_duo/MAINTAINERS
@@ -0,0 +1,6 @@
+Milk-V Duo
+M:	Kongyang Liu <[email protected]>
+S:	Maintained
+F:	board/sophgo/milkv_duo/
+F:	configs/milkv_duo_defconfig
+F:	doc/board/sophgo/milkv_duo.rst
diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile
new file mode 100644
index 00000000000..a087013f5c6
--- /dev/null
+++ b/board/sophgo/milkv_duo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <[email protected]>
+
+obj-y := board.o
diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c
new file mode 100644
index 00000000000..eaa47be1739
--- /dev/null
+++ b/board/sophgo/milkv_duo/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <[email protected]>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 336f0cdfc90..1b49945d11b 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -45,6 +45,10 @@ static const struct starfive_vf2_pro starfive_verb[] = {
 	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
 		"motorcomm,tx-clk-1000-inverted", NULL},
 	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"motorcomm,rx-clk-drv-microamp", "3970"},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+		"motorcomm,rx-data-drv-microamp", "2910"},
+	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
 		"rx-internal-delay-ps", "1900"},
 	{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
 		"tx-internal-delay-ps", "1500"},
@@ -54,6 +58,10 @@ static const struct starfive_vf2_pro starfive_verb[] = {
 	{ "/soc/ethernet@16040000/mdio/ethernet-phy@1",
 		"motorcomm,tx-clk-100-inverted", NULL},
 	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+		"motorcomm,rx-clk-drv-microamp", "3970"},
+	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
+		"motorcomm,rx-data-drv-microamp", "2910"},
+	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
 		"rx-internal-delay-ps", "0"},
 	{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
 		"tx-internal-delay-ps", "0"},
@@ -61,11 +69,13 @@ static const struct starfive_vf2_pro starfive_verb[] = {
 
 void spl_fdt_fixup_version_a(void *fdt)
 {
+	static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110";
 	u32 phandle;
 	u8 i;
 	int offset;
 	int ret;
 
+	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
 	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
 			   "StarFive VisionFive 2 v1.2A");
 
@@ -106,11 +116,13 @@ void spl_fdt_fixup_version_a(void *fdt)
 
 void spl_fdt_fixup_version_b(void *fdt)
 {
+	static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110";
 	u32 phandle;
 	u8 i;
 	int offset;
 	int ret;
 
+	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
 	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
 			   "StarFive VisionFive 2 v1.3B");