diff options
| author | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-04-06 12:16:57 -0600 |
| commit | 93f84ee022a8401421cdaab84fe7d106d83fdb4a (patch) | |
| tree | fb15a4af876e8faf9893fd86c1c0e127265dbe9a /board | |
| parent | 88dc2788777babfd6322fa655df549a019aa1e69 (diff) | |
| parent | e2138cf1e6088f12ffa874e87cc8f4b198378635 (diff) | |
Merge branch 'next'
Diffstat (limited to 'board')
246 files changed, 8176 insertions, 3689 deletions
diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index c05eec6b35e..01d7a8c39e2 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -18,7 +18,6 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/gpio.h> #include <asm/emif.h> @@ -30,8 +29,6 @@ /* -- defines for used GPIO Hardware -- */ #define PER_RESET (2 * 32 + 0) -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_XPL_BUILD) static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 3513f43a9f5..bbafecd7909 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -13,12 +13,9 @@ #include <env.h> #include <fdtdec.h> #include <i2c.h> -#include <asm/global_data.h> #include <linux/delay.h> #include "bur_common.h" -DECLARE_GLOBAL_DATA_PTR; - /* --------------------------------------------------------------------------*/ int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig index b450a21bd98..c7010fb26b3 100644 --- a/board/BuR/zynq/Kconfig +++ b/board/BuR/zynq/Kconfig @@ -7,7 +7,6 @@ config TARGET_ZYNQ_BR bool "Support BR Zynq builds" depends on SYS_VENDOR = "BuR" select BINMAN - select SPL_BINMAN_FDT endif diff --git a/board/Marvell/octeontx/smc.c b/board/Marvell/octeontx/smc.c index 8df32049bda..ab6284a732c 100644 --- a/board/Marvell/octeontx/smc.c +++ b/board/Marvell/octeontx/smc.c @@ -5,13 +5,10 @@ * https://spdx.org/licenses */ -#include <asm/global_data.h> #include <asm/ptrace.h> #include <asm/system.h> #include <asm/arch/smc.h> -DECLARE_GLOBAL_DATA_PTR; - ssize_t smc_dram_size(unsigned int node) { struct pt_regs regs; diff --git a/board/Marvell/octeontx2/smc.c b/board/Marvell/octeontx2/smc.c index 9e3169576c6..10645a74f69 100644 --- a/board/Marvell/octeontx2/smc.c +++ b/board/Marvell/octeontx2/smc.c @@ -5,15 +5,12 @@ * https://spdx.org/licenses */ -#include <asm/global_data.h> #include <asm/io.h> #include <asm/psci.h> #include <asm/ptrace.h> #include <asm/system.h> #include <asm/arch/smc.h> -DECLARE_GLOBAL_DATA_PTR; - ssize_t smc_dram_size(unsigned int node) { struct pt_regs regs; diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 8c9e9830876..a9a12a4f659 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -26,8 +26,6 @@ #include <linux/kernel.h> #include <power/pmic.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index 1f7c1f25adc..fb8e8437759 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -29,8 +29,6 @@ #include <power/pmic.h> #include <power/pca9450.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { #ifdef CONFIG_SPL_BOOTROM_SUPPORT diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index accd300df04..fbe8b247e69 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -16,8 +16,6 @@ #include <asm/arch/sys_proto.h> /* #include <power-domain.h> */ -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 3def182f296..8214e627768 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -8,7 +8,6 @@ #include <env.h> #include <errno.h> #include <init.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/libfdt.h> #include <asm/io.h> @@ -19,8 +18,6 @@ #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/amarula/vyasa-rk3288/MAINTAINERS b/board/amarula/vyasa-rk3288/MAINTAINERS index 08ea208004a..d9cf639a31d 100644 --- a/board/amarula/vyasa-rk3288/MAINTAINERS +++ b/board/amarula/vyasa-rk3288/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/amarula/vyasa-rk3288 F: include/configs/vyasa-rk3288.h F: configs/vyasa-rk3288_defconfig -F: arch/arm/dts/rk3288-vyasa.dts F: arch/arm/dts/rk3288-vyasa-u-boot.dtsi diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index d8079c1cee0..d94c1494d53 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -18,6 +18,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <asm/sections.h> #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> @@ -27,6 +28,7 @@ #include <linux/bitfield.h> #include <debug_uart.h> #include <generated/dt.h> +#include <linux/ioport.h> DECLARE_GLOBAL_DATA_PTR; @@ -367,28 +369,71 @@ int board_late_init(void) int dram_init_banksize(void) { - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - - mem_map_fill(); - + fill_bd_mem_info(); return 0; } int dram_init(void) { - int ret; + struct mm_region bank_info[CONFIG_NR_DRAM_BANKS]; + ofnode mem = ofnode_null(); + struct resource res; + int ret, i, reg = 0; + u32 num_banks, reloc_use = 0; + u64 text = (u64)_start; + + gd->ram_base = (unsigned long)~0; + + mem = fdtdec_get_next_memory_node(mem); + if (!ofnode_valid(mem)) { + printf("%s: Missing /memory node\n", __func__); + return -EINVAL; + } - if (IS_ENABLED(CONFIG_SYS_MEM_RSVD_FOR_MMU)) - ret = fdtdec_setup_mem_size_base(); - else - ret = fdtdec_setup_mem_size_base_lowest(); + debug("%s: Text base = 0x%llx\n", __func__, text); - if (ret) - return -EINVAL; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + reloc_use = 0; + ret = ofnode_read_resource(mem, reg++, &res); + if (ret < 0) { + reg = 0; + mem = fdtdec_get_next_memory_node(mem); + if (!ofnode_valid(mem)) + break; + + ret = ofnode_read_resource(mem, reg++, &res); + if (ret < 0) + break; + } + + if (ret != 0) + return -EINVAL; + + bank_info[i].phys = (phys_addr_t)res.start; + bank_info[i].size = (phys_size_t)(res.end - res.start + 1); + + if (bank_info[i].size == 0) + break; + + if (text >= bank_info[i].phys && + text < (bank_info[i].phys + bank_info[i].size)) { + gd->ram_base = bank_info[i].phys; + gd->ram_size = bank_info[i].size; + reloc_use = 1; + } + + debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx %s", + __func__, i, (unsigned long long)bank_info[i].phys, + (unsigned long long)bank_info[i].size, + (reloc_use ? " - USED for RELOCATION\n" : "\n")); + + num_banks++; + } + + mem_map_fill(bank_info, num_banks); + + debug("%s: Initial DRAM: start = 0x%lx, size = 0x%lx\n", __func__, + gd->ram_base, (unsigned long)gd->ram_size); return 0; } diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c index dc8f1347775..23fd0910ef8 100644 --- a/board/andestech/voyager/voyager.c +++ b/board/andestech/voyager/voyager.c @@ -5,7 +5,6 @@ */ #include <asm/csr.h> -#include <asm/global_data.h> #include <asm/sbi.h> #include <config.h> #include <cpu_func.h> @@ -19,8 +18,6 @@ #include <net.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 9ef3fa1b379..49c7fda0b83 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -41,7 +41,8 @@ config TARGET_VEXPRESS64_BASER_FVP config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select PCIE_ECAM_GENERIC if PCI - select SATA_SIL + select SATA if PCI + select SATA_SIL if PCI select SMC911X if DM_ETH select SMC911X_32_BIT if SMC911X select CMD_USB if USB diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index e8f1c2fe9fe..d68da0e3d65 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -12,7 +12,6 @@ #include <errno.h> #include <net.h> #include <netdev.h> -#include <asm/global_data.h> #include <asm/io.h> #include <linux/compiler.h> #include <linux/sizes.h> @@ -24,8 +23,6 @@ #include <virtio.h> #endif -DECLARE_GLOBAL_DATA_PTR; - static const struct pl01x_serial_plat serial_plat = { .base = V2M_UART0, .type = TYPE_PL011, diff --git a/board/beacon/imx8mm/Makefile b/board/beacon/imx8mm/Makefile index 8484b85ae12..eb762504266 100644 --- a/board/beacon/imx8mm/Makefile +++ b/board/beacon/imx8mm/Makefile @@ -4,7 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx8mm_beacon.o obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c deleted file mode 100644 index 6459a99cb9d..00000000000 --- a/board/beacon/imx8mm/imx8mm_beacon.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks - */ - -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 93ee5b7ee0c..1e5935788ff 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -5,7 +5,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/arch/clock.h> @@ -23,8 +22,6 @@ #include <power/pmic.h> #include <power/bd71837.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/beacon/imx8mn/Makefile b/board/beacon/imx8mn/Makefile index 54735792b93..e8fe9f1822e 100644 --- a/board/beacon/imx8mn/Makefile +++ b/board/beacon/imx8mn/Makefile @@ -4,7 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx8mn_beacon.o obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/beacon/imx8mn/imx8mn_beacon.c b/board/beacon/imx8mn/imx8mn_beacon.c deleted file mode 100644 index 6459a99cb9d..00000000000 --- a/board/beacon/imx8mn/imx8mn_beacon.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks - */ - -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index e91d3fdcf5e..46db42ec921 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -9,7 +9,6 @@ #include <log.h> #include <asm/io.h> #include <errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/ddr.h> #include <asm/arch/imx8mn_pins.h> @@ -32,8 +31,6 @@ #include <dm/uclass-internal.h> #include <dm/device-internal.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 027fae38278..e82e385b774 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -8,7 +8,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/arch/clock.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> @@ -22,8 +21,6 @@ #include <dm/uclass.h> #include <dm/device.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index 500fcc58ed8..27b1f22562c 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -13,8 +13,6 @@ #include <fdt_support.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID, diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 9bc9ca30e95..70d296de9f8 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -14,8 +14,6 @@ #include <asm/arch/hardware.h> -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID, diff --git a/board/beagle/beagleplay/rm-cfg.yaml b/board/beagle/beagleplay/rm-cfg.yaml index e4221f82f92..aa999c2ef67 100644 --- a/board/beagle/beagleplay/rm-cfg.yaml +++ b/board/beagle/beagleplay/rm-cfg.yaml @@ -513,7 +513,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -543,7 +543,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 627 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 diff --git a/board/beagle/beaglev_fire/Kconfig b/board/beagle/beaglev_fire/Kconfig new file mode 100644 index 00000000000..7a8ecac8703 --- /dev/null +++ b/board/beagle/beaglev_fire/Kconfig @@ -0,0 +1,43 @@ +if TARGET_BEAGLEBOARD_BEAGLEVFIRE + +config SYS_BOARD + default "beaglev_fire" + +config SYS_VENDOR + default "beagle" + +config SYS_CPU + default "mpfs" + +config SYS_CONFIG_NAME + default "beaglev_fire" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select MICROCHIP_MPFS + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply PHY_LIB + imply PHY_VITESSE + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER +endif diff --git a/board/beagle/beaglev_fire/MAINTAINERS b/board/beagle/beaglev_fire/MAINTAINERS new file mode 100644 index 00000000000..a5dad93ee99 --- /dev/null +++ b/board/beagle/beaglev_fire/MAINTAINERS @@ -0,0 +1,7 @@ +BeagleBoard MPFS BeagleV-Fire +M: Cyril Jean <[email protected]> +M: Jamie Gibbons <[email protected]> +S: Maintained +F: board/beagle/beaglev_fire/ +F: include/configs/beaglev_fire.h +F: configs/beaglev_fire_defconfig
\ No newline at end of file diff --git a/board/beagle/beaglev_fire/Makefile b/board/beagle/beaglev_fire/Makefile new file mode 100644 index 00000000000..a4109a8aad4 --- /dev/null +++ b/board/beagle/beaglev_fire/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Microchip Technology Inc. +# + +obj-y += beaglev_fire.o
\ No newline at end of file diff --git a/board/beagle/beaglev_fire/beaglev_fire.c b/board/beagle/beaglev_fire/beaglev_fire.c new file mode 100644 index 00000000000..b2f18c455b7 --- /dev/null +++ b/board/beagle/beaglev_fire/beaglev_fire.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2023 Microchip Technology Inc. + */ + +#include <dm.h> +#include <dm/devres.h> +#include <env.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <linux/compat.h> +#include <mpfs-mailbox.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x800001e8u + +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) +static unsigned char mac_addr[6]; +#endif + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = devm_kzalloc(dev, sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mpfs_syscontroller_process_dtbo(sys_serv_priv); +#endif + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } +#endif + + return 0; +}
\ No newline at end of file diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 47a01227a35..cb53ec68cf8 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -9,12 +9,9 @@ #include <log.h> #include <ram.h> #include <serial.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/armv7m.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/chipspark/popmetal_rk3288/MAINTAINERS b/board/chipspark/popmetal_rk3288/MAINTAINERS index e12f128dcd7..c81905453f2 100644 --- a/board/chipspark/popmetal_rk3288/MAINTAINERS +++ b/board/chipspark/popmetal_rk3288/MAINTAINERS @@ -1,7 +1,6 @@ POPMETAL-RK3288 M: Lin Huang <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-popmetal.dts F: arch/arm/dts/rk3288-popmetal-u-boot.dtsi F: board/chipspark/popmetal_rk3288 F: include/configs/popmetal_rk3288.h diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.c b/board/cloos/imx8mm_phg/imx8mm_phg.c index 091c9a59a52..1ca1c07e08e 100644 --- a/board/cloos/imx8mm_phg/imx8mm_phg.c +++ b/board/cloos/imx8mm_phg/imx8mm_phg.c @@ -7,14 +7,11 @@ #include <init.h> #include <miiphy.h> #include <netdev.h> -#include <asm/global_data.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> -DECLARE_GLOBAL_DATA_PTR; - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c index b8892ed2fcc..b2340a0ded3 100644 --- a/board/cloos/imx8mm_phg/spl.c +++ b/board/cloos/imx8mm_phg/spl.c @@ -10,7 +10,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/arch/clock.h> @@ -28,8 +27,6 @@ #include <power/pmic.h> #include <power/pca9450.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 6d9af2538b6..daac6dca4ce 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -32,8 +32,6 @@ #include "ddr/ddr.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index f2ca1076768..d0e8db6cdfe 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -7,9 +7,6 @@ #include <init.h> #include <smbios.h> #include <asm/cb_sysinfo.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; int board_early_init_r(void) { diff --git a/board/corecourse/ac501soc/MAINTAINERS b/board/corecourse/ac501soc/MAINTAINERS new file mode 100644 index 00000000000..1feac0c0584 --- /dev/null +++ b/board/corecourse/ac501soc/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Brian Sune <[email protected]> +S: Maintained +F: board/corecourse/ac501soc/ +F: include/configs/socfpga_ac501soc.h +F: configs/socfpga_ac501soc_defconfig diff --git a/board/corecourse/ac501soc/qts/iocsr_config.h b/board/corecourse/ac501soc/qts/iocsr_config.h new file mode 100644 index 00000000000..cce43c54377 --- /dev/null +++ b/board/corecourse/ac501soc/qts/iocsr_config.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x000C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x80008000, + 0x0000007F, + 0x0001FE00, + 0x07F80000, + 0xE0000000, + 0x0000001F, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x00007F80, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x00000000, + 0x00000010, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x10018060, + 0x00000000, + 0x06000000, + 0x00010018, + 0x01806018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x41034030, + 0x02081A00, + 0x80A280D0, + 0x34030C06, + 0x01A02490, + 0x280D0000, + 0x30C0680A, + 0x00410340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x69A47A05, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A028A, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1EF228A3, + 0x48F4D145, + 0x000352D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0xFE120800, + 0x00000001, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xF228A3D5, + 0xF4D1451E, + 0x03429248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x00FF090C, + 0x00000000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x69A47A05, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0xC0000004, + 0x0000003F, + 0x0000FF00, + 0x03FC0000, + 0xF0000000, + 0x0000000F, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0xE0000002, + 0x0000001F, + 0x00007F80, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0xF0000001, + 0x0000000F, + 0x00003FC0, + 0x00FF0000, + 0xFC000000, + 0x00000003, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x0001FE00, + 0x07F80000, + 0xE0000000, + 0x0000001F, + 0x00004000, +}; + + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/pinmux_config.h b/board/corecourse/ac501soc/qts/pinmux_config.h new file mode 100644 index 00000000000..462cde84565 --- /dev/null +++ b/board/corecourse/ac501soc/qts/pinmux_config.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 1, /* GENERALIO5 */ + 1, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/pll_config.h b/board/corecourse/ac501soc/qts/pll_config.h new file mode 100644 index 00000000000..88e0b2a3776 --- /dev/null +++ b/board/corecourse/ac501soc/qts/pll_config.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CFG_HPS_DBCTRL_STAYOSC1 1 + +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 + +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/sdram_config.h b/board/corecourse/ac501soc/qts/sdram_config.h new file mode 100644 index 00000000000..43cf307847e --- /dev/null +++ b/board/corecourse/ac501soc/qts/sdram_config.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 12 +#define CALIB_VFIFO_OFFSET 10 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b5 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080471, + 0x10080570, + 0x10090006, + 0x100a0218, + 0x100b0000, + 0x10380400, + 0x10080469, + 0x100804e8, + 0x100a0006, + 0x10090218, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/MAINTAINERS b/board/corecourse/ac550soc/MAINTAINERS new file mode 100644 index 00000000000..c46d8c70702 --- /dev/null +++ b/board/corecourse/ac550soc/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Brian Sune <[email protected]> +S: Maintained +F: board/corecourse/ac550soc/ +F: include/configs/socfpga_ac550soc.h +F: configs/socfpga_ac550soc_defconfig diff --git a/board/corecourse/ac550soc/qts/iocsr_config.h b/board/corecourse/ac550soc/qts/iocsr_config.h new file mode 100644 index 00000000000..710ab602de6 --- /dev/null +++ b/board/corecourse/ac550soc/qts/iocsr_config.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x000C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x20000000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C820D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x802080D0, + 0x34051406, + 0x01A02490, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x41034051, + 0x02081A00, + 0x80A280D0, + 0x34051406, + 0x01A00040, + 0x080D0002, + 0x51406802, + 0x02490340, + 0xD012481A, + 0x06802080, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0xD9647A05, + 0xBB2CA3D0, + 0xF711451E, + 0x035E9248, + 0x821A0000, + 0x0000D000, + 0x01040680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035ED3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA24, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0xD9647A05, + 0xDA28A3D0, + 0xF711451E, + 0x0340D348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035ED3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA24, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xBB2CA3DF, + 0xF51E791E, + 0x0340D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035E92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x69A47A06, + 0xDA28A3DF, + 0xF51E791E, + 0x034E9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDF69A47A, + 0x1EDA28A3, + 0x48F51E79, + 0x00034E92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/pinmux_config.h b/board/corecourse/ac550soc/qts/pinmux_config.h new file mode 100644 index 00000000000..2e8df563141 --- /dev/null +++ b/board/corecourse/ac550soc/qts/pinmux_config.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 0, /* GENERALIO3 */ + 0, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 1, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 1, /* UART1USEFPGA */ + 1, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 1, /* I2C3USEFPGA */ + 1, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/pll_config.h b/board/corecourse/ac550soc/qts/pll_config.h new file mode 100644 index 00000000000..673b9de864f --- /dev/null +++ b/board/corecourse/ac550soc/qts/pll_config.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CFG_HPS_DBCTRL_STAYOSC1 1 + +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 71 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 17 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1800000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 1066666667 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 360000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 + +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/sdram_config.h b/board/corecourse/ac550soc/qts/sdram_config.h new file mode 100644 index 00000000000..eae9f57dd9c --- /dev/null +++ b/board/corecourse/ac550soc/qts/sdram_config.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation <www.intel.com> + * + */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 27 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 187 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 27 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x3FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 534 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 234 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 15 +#define IO_DQS_EN_DELAY_OFFSET 16 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b5 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 132 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 132 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080831, + 0x10080930, + 0x10090006, + 0x100a0208, + 0x100b0000, + 0x10380400, + 0x10080849, + 0x100808c8, + 0x100a0006, + 0x10090210, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 49c13056edc..552349d104a 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -26,8 +26,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - #define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE) #define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2)) #define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)(CONFIG_CPLD_BASE + 3)) diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index e271d060efa..ab4a484d393 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -14,8 +14,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int board_late_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index a9ef049652a..c6a5740c7a7 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -27,8 +27,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index d6f0a917023..5c319df1cde 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -17,8 +17,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - static void dmo_setup_second_mac_address(void) { u8 enetaddr[6]; diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index f81b7274556..314f7e87a9d 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -28,8 +28,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; diff --git a/board/dhelectronics/dh_imx8mp/Makefile b/board/dhelectronics/dh_imx8mp/Makefile index 7bc8dc21e64..12fb7b71ab6 100644 --- a/board/dhelectronics/dh_imx8mp/Makefile +++ b/board/dhelectronics/dh_imx8mp/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o +obj-y += spl.o lpddr4_timing_2G_32.o else obj-y += imx8mp_dhcom_pdk2.o endif diff --git a/board/dhelectronics/dh_imx8mp/common.c b/board/dhelectronics/dh_imx8mp/common.c index f6db9f67804..5d89c94970d 100644 --- a/board/dhelectronics/dh_imx8mp/common.c +++ b/board/dhelectronics/dh_imx8mp/common.c @@ -8,8 +8,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - u8 dh_get_memcfg(void) { struct gpio_desc gpio[4]; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 5c35a5bf447..3424be10936 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -20,8 +20,6 @@ #include "../common/dh_common.h" #include "../common/dh_imx.h" -DECLARE_GLOBAL_DATA_PTR; - int mach_cpu_init(void) { icache_enable(); @@ -30,12 +28,11 @@ int mach_cpu_init(void) int board_phys_sdram_size(phys_size_t *size) { - const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK; u8 memcfg = dh_get_memcfg(); /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */ - *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0)); + *size = (u64)dh_imx8mp_dhcom_dram_size[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0)); return 0; } diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h index c4d51174a33..5dc841a7f5a 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h @@ -6,12 +6,16 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32; -extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32; +static const u16 dh_imx8mp_dhcom_dram_size[] = { + 4096, 1024, 1536, 2048, 3072, 4096, 6144, 8192 +}; -typedef void (*scrub_func_t)(void); -extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void); -extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void); +extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32; +static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing = + &dh_imx8mp_dhcom_dram_timing_16g_x32; +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void); +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void); +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void); u8 dh_get_memcfg(void); diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c index add7a0bf23b..9574e920352 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c @@ -1854,16 +1854,197 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = { .fsp_table = { 3600, 400, 100, }, }; -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) -void dh_imx8mp_dhcom_dram_scrub_16g_x32(void) +/* + * Convert 2 GiB DRAM settings to 2 GiB DRAM settings. + * This does nothing and is only a placeholder to indicate + * that the 2 GiB DRAM settings are valid themselves. + */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void) { - ddrc_inline_ecc_scrub(0x0,0x3ffffff); - ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); - ddrc_inline_ecc_scrub(0x8000000,0xbffffff); - ddrc_inline_ecc_scrub(0xc000000,0xfffffff); - ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); - ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); - ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); - ddrc_inline_ecc_scrub_end(0x0,0x1fffffff); } + +/* Convert 2 GiB DRAM settings to 4 GiB 2-rank DRAM settings. */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) { + if (ddr_ddrc_cfg[i].reg == 0x3d400000) + ddr_ddrc_cfg[i].val = 0xa3080020; +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x14; + if (ddr_ddrc_cfg[i].reg == 0x3d40020c) + ddr_ddrc_cfg[i].val = 0x14141400; +#else + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x17; +#endif + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp0_cfg); i++) { + if (ddr_fsp0_cfg[i].reg == 0x54012) + ddr_fsp0_cfg[i].val = 0x310; + if (ddr_fsp0_cfg[i].reg == 0x5402c) + ddr_fsp0_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) { + if (ddr_fsp1_cfg[i].reg == 0x54012) + ddr_fsp1_cfg[i].val = 0x310; + if (ddr_fsp1_cfg[i].reg == 0x5402c) + ddr_fsp1_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) { + if (ddr_fsp2_cfg[i].reg == 0x54012) + ddr_fsp2_cfg[i].val = 0x310; + if (ddr_fsp2_cfg[i].reg == 0x5402c) + ddr_fsp2_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp0_2d_cfg); i++) { + if (ddr_fsp0_2d_cfg[i].reg == 0x54012) + ddr_fsp0_2d_cfg[i].val = 0x310; + if (ddr_fsp0_2d_cfg[i].reg == 0x5402c) + ddr_fsp0_2d_cfg[i].val = 0x3; + } +}; + +/* Convert 2 GiB DRAM settings to 4 GiB 1-rank DRAM settings. */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) { + if (ddr_ddrc_cfg[i].reg == 0x3d400064) + ddr_ddrc_cfg[i].val = 0x6d0156; + if (ddr_ddrc_cfg[i].reg == 0x3d400138) + ddr_ddrc_cfg[i].val = 0x15d; +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x1f; + if (ddr_ddrc_cfg[i].reg == 0x3d40020c) + ddr_ddrc_cfg[i].val = 0x14141400; +#else + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x17; #endif + if (ddr_ddrc_cfg[i].reg == 0x3d40021c) + ddr_ddrc_cfg[i].val = 0xf04; + if (ddr_ddrc_cfg[i].reg == 0x3d402024) + ddr_ddrc_cfg[i].val = 0x61a800; + if (ddr_ddrc_cfg[i].reg == 0x3d402064) + ddr_ddrc_cfg[i].val = 0x18004c; + if (ddr_ddrc_cfg[i].reg == 0x3d4020dc) + ddr_ddrc_cfg[i].val = 0x940009; + if (ddr_ddrc_cfg[i].reg == 0x3d402100) + ddr_ddrc_cfg[i].val = 0xc080609; + if (ddr_ddrc_cfg[i].reg == 0x3d402104) + ddr_ddrc_cfg[i].val = 0x3040d; + if (ddr_ddrc_cfg[i].reg == 0x3d402108) + ddr_ddrc_cfg[i].val = 0x3060a0c; + if (ddr_ddrc_cfg[i].reg == 0x3d402110) + ddr_ddrc_cfg[i].val = 0x4040204; + if (ddr_ddrc_cfg[i].reg == 0x3d402114) + ddr_ddrc_cfg[i].val = 0x2030303; + if (ddr_ddrc_cfg[i].reg == 0x3d402138) + ddr_ddrc_cfg[i].val = 0x4e; + if (ddr_ddrc_cfg[i].reg == 0x3d402144) + ddr_ddrc_cfg[i].val = 0x280014; + if (ddr_ddrc_cfg[i].reg == 0x3d402180) + ddr_ddrc_cfg[i].val = 0xc80006; + if (ddr_ddrc_cfg[i].reg == 0x3d402190) + ddr_ddrc_cfg[i].val = 0x3878202; + if (ddr_ddrc_cfg[i].reg == 0x3d4021b4) + ddr_ddrc_cfg[i].val = 0x702; + if (ddr_ddrc_cfg[i].reg == 0x3d403024) + ddr_ddrc_cfg[i].val = 0x493fe1; + if (ddr_ddrc_cfg[i].reg == 0x3d403064) + ddr_ddrc_cfg[i].val = 0x12003a; + if (ddr_ddrc_cfg[i].reg == 0x3d403100) + ddr_ddrc_cfg[i].val = 0xa070507; + if (ddr_ddrc_cfg[i].reg == 0x3d403104) + ddr_ddrc_cfg[i].val = 0x3040a; + if (ddr_ddrc_cfg[i].reg == 0x3d403108) + ddr_ddrc_cfg[i].val = 0x203070b; + if (ddr_ddrc_cfg[i].reg == 0x3d403110) + ddr_ddrc_cfg[i].val = 0x3040203; + if (ddr_ddrc_cfg[i].reg == 0x3d403114) + ddr_ddrc_cfg[i].val = 0x2030303; + if (ddr_ddrc_cfg[i].reg == 0x3d403138) + ddr_ddrc_cfg[i].val = 0x3b; + if (ddr_ddrc_cfg[i].reg == 0x3d403144) + ddr_ddrc_cfg[i].val = 0x1f0010; + if (ddr_ddrc_cfg[i].reg == 0x3d403180) + ddr_ddrc_cfg[i].val = 0x970005; + } + + for (i = 0; i < ARRAY_SIZE(ddr_ddrphy_cfg); i++) { + if (ddr_ddrphy_cfg[i].reg == 0x12002e) + ddr_ddrphy_cfg[i].val = 0x1; + if (ddr_ddrphy_cfg[i].reg == 0x22002e) + ddr_ddrphy_cfg[i].val = 0x1; + if (ddr_ddrphy_cfg[i].reg == 0x120008) + ddr_ddrphy_cfg[i].val = 0xc8; + if (ddr_ddrphy_cfg[i].reg == 0x220008) + ddr_ddrphy_cfg[i].val = 0x96; + if (ddr_ddrphy_cfg[i].reg == 0x200f0) + ddr_ddrphy_cfg[i].val = 0x500; + if (ddr_ddrphy_cfg[i].reg == 0x200f4) + ddr_ddrphy_cfg[i].val = 0x5555; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) { + if (ddr_fsp1_cfg[i].reg == 0x54002) + ddr_fsp1_cfg[i].val = 0x1; + if (ddr_fsp1_cfg[i].reg == 0x54003) + ddr_fsp1_cfg[i].val = 0x320; + if (ddr_fsp1_cfg[i].reg == 0x54019) + ddr_fsp1_cfg[i].val = 0x994; + if (ddr_fsp1_cfg[i].reg == 0x5401f) + ddr_fsp1_cfg[i].val = 0x994; + if (ddr_fsp1_cfg[i].reg == 0x54032) + ddr_fsp1_cfg[i].val = 0x9400; + if (ddr_fsp1_cfg[i].reg == 0x54033) + ddr_fsp1_cfg[i].val = 0xf309; + if (ddr_fsp1_cfg[i].reg == 0x54038) + ddr_fsp1_cfg[i].val = 0x9400; + if (ddr_fsp1_cfg[i].reg == 0x54039) + ddr_fsp1_cfg[i].val = 0xf309; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) { + if (ddr_fsp2_cfg[i].reg == 0x54002) + ddr_fsp2_cfg[i].val = 0x2; + if (ddr_fsp2_cfg[i].reg == 0x54003) + ddr_fsp2_cfg[i].val = 0x258; + if (ddr_fsp2_cfg[i].reg == 0x54019) + ddr_fsp2_cfg[i].val = 0x994; + if (ddr_fsp2_cfg[i].reg == 0x5401f) + ddr_fsp2_cfg[i].val = 0x994; + if (ddr_fsp2_cfg[i].reg == 0x54032) + ddr_fsp2_cfg[i].val = 0x9400; + if (ddr_fsp2_cfg[i].reg == 0x54033) + ddr_fsp2_cfg[i].val = 0xf309; + if (ddr_fsp2_cfg[i].reg == 0x54038) + ddr_fsp2_cfg[i].val = 0x9400; + if (ddr_fsp2_cfg[i].reg == 0x54039) + ddr_fsp2_cfg[i].val = 0xf309; + } + + for (i = 0; i < ARRAY_SIZE(ddr_phy_pie); i++) { + if (ddr_phy_pie[i].reg == 0x12000b) + ddr_phy_pie[i].val = 0xe1; + if (ddr_phy_pie[i].reg == 0x12000c) + ddr_phy_pie[i].val = 0x32; + if (ddr_phy_pie[i].reg == 0x12000d) + ddr_phy_pie[i].val = 0x1f4; + if (ddr_phy_pie[i].reg == 0x22000b) + ddr_phy_pie[i].val = 0xa8; + if (ddr_phy_pie[i].reg == 0x22000c) + ddr_phy_pie[i].val = 0x25; + if (ddr_phy_pie[i].reg == 0x22000d) + ddr_phy_pie[i].val = 0x177; + } +}; diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c deleted file mode 100644 index 41b078f6e9f..00000000000 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c +++ /dev/null @@ -1,1873 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Marek Vasut <[email protected]> - * - * Generated code from MX8M_DDR_tool - */ - -#include <linux/kernel.h> -#include <asm/arch/ddr.h> - -static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x1323 }, - { 0x3d400024, 0x1b77400 }, - { 0x3d400064, 0x6d00fc }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400070, 0x7027fd4 }, -#else - { 0x3d400070, 0x7027f90 }, -#endif - { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00306df }, - { 0x3d4000d4, 0xb10000 }, - { 0x3d4000dc, 0xe40036 }, - { 0x3d4000e0, 0xf30000 }, - { 0x3d4000e8, 0x660048 }, - { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x1d241e26 }, - { 0x3d400104, 0x70739 }, - { 0x3d40010c, 0xd0d000 }, - { 0x3d400110, 0x11040911 }, - { 0x3d400114, 0x2050e0e }, - { 0x3d400118, 0x1010008 }, - { 0x3d40011c, 0x502 }, - { 0x3d400130, 0x20700 }, - { 0x3d400134, 0xd100002 }, - { 0x3d400138, 0x103 }, - { 0x3d400144, 0xb4005a }, - { 0x3d400180, 0x384001b }, - { 0x3d400184, 0x2d06ddd }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820c }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0c }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x7 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x799 }, - { 0x3d400108, 0x8121b1a }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400200, 0x14 }, -#else - { 0x3d400200, 0x17 }, -#endif - { 0x3d400208, 0x0 }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d40020c, 0x14141400 }, -#else - { 0x3d40020c, 0x0 }, -#endif - { 0x3d400210, 0x1f1f }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400204, 0x50505 }, - { 0x3d400214, 0x4040404 }, - { 0x3d400218, 0x4040404 }, -#else - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, -#endif - { 0x3d40021c, 0xf0f }, - { 0x3d400250, 0x1705 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1021 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0xf30000 }, - { 0x3d4020e8, 0x660048 }, - { 0x3d4020ec, 0x160048 }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x302 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1021 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0xf30000 }, - { 0x3d4030e8, 0x660048 }, - { 0x3d4030ec, 0x160048 }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x302 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0x599 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x384 }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x1 }, - { 0x12002d, 0x1 }, - { 0x22002d, 0x1 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x22007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x22007c, 0x61 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xe10 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0xf336 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0xf336 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0xf300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0xf300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0xf300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0xf300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xe10 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0xf336 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0xf336 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xb }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x633 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x633 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x633 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x633 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x633 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x633 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x633 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x633 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x633 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xb }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x1 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x625 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x625 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a4, 0x0 }, - { 0x900a5, 0x790 }, - { 0x900a6, 0x11a }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7aa }, - { 0x900a9, 0x2a }, - { 0x900aa, 0x10 }, - { 0x900ab, 0x7b2 }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x0 }, - { 0x900ae, 0x7c8 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x10 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x1 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xd }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x8 }, - { 0x90159, 0xe8 }, - { 0x9015a, 0x109 }, - { 0x9015b, 0x0 }, - { 0x9015c, 0x8140 }, - { 0x9015d, 0x10c }, - { 0x9015e, 0x10 }, - { 0x9015f, 0x8138 }, - { 0x90160, 0x104 }, - { 0x90161, 0x8 }, - { 0x90162, 0x448 }, - { 0x90163, 0x109 }, - { 0x90164, 0xf }, - { 0x90165, 0x7c0 }, - { 0x90166, 0x109 }, - { 0x90167, 0x0 }, - { 0x90168, 0xe8 }, - { 0x90169, 0x109 }, - { 0x9016a, 0x47 }, - { 0x9016b, 0x630 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0x8 }, - { 0x9016e, 0x618 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x8 }, - { 0x90171, 0xe0 }, - { 0x90172, 0x109 }, - { 0x90173, 0x0 }, - { 0x90174, 0x7c8 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x8140 }, - { 0x90178, 0x10c }, - { 0x90179, 0x0 }, - { 0x9017a, 0x478 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x1 }, - { 0x9017e, 0x8 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x4 }, - { 0x90181, 0x0 }, - { 0x90006, 0x8 }, - { 0x90007, 0x7c8 }, - { 0x90008, 0x109 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x400 }, - { 0x9000b, 0x106 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x29 }, - { 0x90026, 0x68 }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x200be, 0x3 }, - { 0x2000b, 0x3f4 }, - { 0x2000c, 0xe1 }, - { 0x2000d, 0x8ca }, - { 0x2000e, 0x2c }, - { 0x12000b, 0x70 }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x1c }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x2060 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3600mts 1D */ - .drate = 3600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3600mts 2D */ - .drate = 3600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3600, 400, 100, }, -}; - -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) -void dh_imx8mp_dhcom_dram_scrub_32g_x32(void) -{ - ddrc_inline_ecc_scrub(0x0,0x7ffffff); - ddrc_inline_ecc_scrub(0x8000000,0xfffffff); - ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); - ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); - ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); - ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); - ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); - ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); -} -#endif diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 714f846521e..aab8550023e 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -29,8 +29,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) @@ -106,34 +104,36 @@ static int dh_imx8mp_board_power_init(void) return 0; } -static struct dram_timing_info *dram_timing_info[8] = { - NULL, /* 512 MiB */ - NULL, /* 1024 MiB */ - NULL, /* 1536 MiB */ - &dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */ - NULL, /* 3072 MiB */ - &dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */ - NULL, /* 6144 MiB */ - NULL, /* 8192 MiB */ +typedef void (*patch_func_t)(void); + +static const patch_func_t dram_patch_fn[8] = { + dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r, /* 4096 MiB 1-rank */ + NULL, /* 1024 MiB */ + NULL, /* 1536 MiB */ + dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32, /* 2048 MiB */ + NULL, /* 3072 MiB */ + dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r, /* 4096 MiB 2-rank */ + NULL, /* 6144 MiB */ + NULL, /* 8192 MiB */ }; static void spl_dram_init(void) { - const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; u8 memcfg = dh_get_memcfg(); int i; - printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg); + printf("DDR: %d MiB [0x%x]\n", dh_imx8mp_dhcom_dram_size[memcfg], memcfg); - if (!dram_timing_info[memcfg]) { + if (!dram_patch_fn[memcfg]) { printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n", memcfg); - for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++) - if (dram_timing_info[i]) /* Configuration found */ + for (i = 0; i < ARRAY_SIZE(dram_patch_fn); i++) + if (dram_patch_fn[i]) /* Configuration found */ break; } - ddr_init(dram_timing_info[memcfg]); + dram_patch_fn[memcfg](); + ddr_init(dh_imx8mp_dhcom_dram_timing); printf("DDR: Inline ECC %sabled\n", (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ? @@ -141,13 +141,39 @@ static void spl_dram_init(void) } #if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +static void dh_imx8mp_dhcom_dram_scrub_16g_x32(void) +{ + ddrc_inline_ecc_scrub(0x0,0x3ffffff); + ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xbffffff); + ddrc_inline_ecc_scrub(0xc000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); + ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); + ddrc_inline_ecc_scrub_end(0x0,0x1fffffff); +} + +static void dh_imx8mp_dhcom_dram_scrub_32g_x32(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} + +typedef void (*scrub_func_t)(void); + static const scrub_func_t dram_scrub_fn[8] = { - NULL, /* 512 MiB */ + dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB 1-rank */ NULL, /* 1024 MiB */ NULL, /* 1536 MiB */ dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */ NULL, /* 3072 MiB */ - dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */ + dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB 2-rank */ NULL, /* 6144 MiB */ NULL, /* 8192 MiB */ }; diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.env b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env index c19fe08648a..326023274e9 100644 --- a/board/emcraft/imx8mp_navqp/imx8mp_navqp.env +++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env @@ -11,7 +11,7 @@ image=Image console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 fdt_addr_r=0x43000000 boot_fdt=try -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE initrd_addr=0x43800000 bootm_size=0x10000000 mmcpart=1 diff --git a/board/emcraft/imx8mp_navqp/spl.c b/board/emcraft/imx8mp_navqp/spl.c index 7f30f3af742..5ee94d078f8 100644 --- a/board/emcraft/imx8mp_navqp/spl.c +++ b/board/emcraft/imx8mp_navqp/spl.c @@ -8,7 +8,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <asm/sections.h> #include <dm/device.h> @@ -20,8 +19,6 @@ #include <power/pmic.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 97c8211c100..ce5bc34ca71 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -15,8 +15,6 @@ #include <virtio_types.h> #include <virtio.h> -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_MTD_NOR_FLASH) int is_flash_available(void) { diff --git a/board/engicam/imx8mm/icore_mx8mm.c b/board/engicam/imx8mm/icore_mx8mm.c index 236337546ae..bb70e7d4ff8 100644 --- a/board/engicam/imx8mm/icore_mx8mm.c +++ b/board/engicam/imx8mm/icore_mx8mm.c @@ -19,8 +19,6 @@ #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/iomux-v3.h> -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_FEC_MXC) #define FEC_RST_PAD IMX_GPIO_NR(3, 7) diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index d51ae241e85..702f0caafab 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -17,8 +17,6 @@ #include <asm/arch/ddr.h> #include <asm/sections.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -54,11 +52,6 @@ int board_fit_config_name_match(const char *name) } #endif -int board_early_init_f(void) -{ - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -67,8 +60,6 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index bfdc447c478..864afa92aee 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -14,7 +14,6 @@ #include <miiphy.h> #include <netdev.h> #include <linux/delay.h> -#include <asm/global_data.h> #include <asm/mach-imx/iomux-v3.h> #include <asm-generic/gpio.h> #include <asm/arch/imx8mp_pins.h> @@ -22,8 +21,6 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index cd31aa6041d..46c581ea51f 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -12,20 +12,14 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/arch/clock.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/arch/ddr.h> #include <power/pmic.h> #include <power/pca9450.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -36,36 +30,22 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); #ifdef CONFIG_IMX8M_LPDDR4 /* @@ -76,22 +56,22 @@ int power_init_board(void) */ #ifdef CONFIG_IMX8M_VDD_SOC_850MV /* set DVS0 to 0.85v for special case*/ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); #else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); #endif - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Kernel uses OD/OD freq for SOC */ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); #elif defined(CONFIG_IMX8M_DDR4) /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set NVCC_DRAM to 1.2v for DDR4 */ - pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18); + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18); #endif return 0; @@ -139,8 +119,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c index 05e4d84460a..123dda21423 100644 --- a/board/gdsys/mpc8308/gazerbeam.c +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -17,13 +17,10 @@ #include <sysinfo.h> #include <tpm-v1.h> #include <video_osd.h> -#include <asm/global_data.h> #include "../common/ihs_mdio.h" #include "../../../drivers/sysinfo/gazerbeam.h" -DECLARE_GLOBAL_DATA_PTR; - struct ihs_mdio_info ihs_mdio_info[] = { { .fpga = NULL, .name = "ihs0", .base = 0x58 }, { .fpga = NULL, .name = "ihs1", .base = 0x58 }, diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c index 9544d6dd19a..2f16f1da26c 100644 --- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c +++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -7,7 +7,6 @@ #include <init.h> #include <malloc.h> #include <errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include <miiphy.h> #include <netdev.h> @@ -21,8 +20,6 @@ #include <asm/arch/clock.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS index 67341b5d556..382ad212569 100644 --- a/board/google/veyron/MAINTAINERS +++ b/board/google/veyron/MAINTAINERS @@ -1,7 +1,6 @@ CHROMEBOOK JERRY BOARD M: Simon Glass <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-veyron-jerry.dts F: arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -10,7 +9,6 @@ F: configs/chromebook_jerry_defconfig CHROMEBIT MICKEY BOARD M: Simon Glass <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-veyron-mickey.dts F: arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -19,7 +17,6 @@ F: configs/chromebit_mickey_defconfig CHROMEBOOK MINNIE BOARD M: Simon Glass <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-veyron-minnie.dts F: arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -28,7 +25,6 @@ F: configs/chromebook_minnie_defconfig CHROMEBOOK SPEEDY BOARD M: Simon Glass <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-veyron-speedy.dts F: arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -37,8 +33,4 @@ F: configs/chromebook_speedy_defconfig CHROMEBOOK VEYRON COMMON FILES M: Simon Glass <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-veyron.dtsi -F: arch/arm/dts/rk3288-veyron-analog-audio.dtsi -F: arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi -F: arch/arm/dts/rk3288-veyron-chromebook.dtsi -F: arch/arm/dts/rk3288-veyron-edp.dtsi +F: arch/arm/dts/rk3288-veyron-u-boot.dtsi diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 0ec88447384..62a7b5b0420 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -11,7 +11,6 @@ #include <init.h> #include <net.h> #include <scsi.h> -#include <asm/global_data.h> #include <linux/sizes.h> #include <asm/io.h> @@ -37,8 +36,6 @@ #define HB_SCU_A9_PWR_DORMANT 2 #define HB_SCU_A9_PWR_OFF 3 -DECLARE_GLOBAL_DATA_PTR; - void cphy_disable_overrides(void); /* diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index c21b083b62a..4dc7b608f0f 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -9,7 +9,6 @@ #include <malloc.h> #include <mtd.h> #include <net.h> -#include <status_led.h> #include <dm.h> #include <ns16550.h> #include <twl4030.h> diff --git a/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c b/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c index 3db7176f723..739a78d2c8b 100644 --- a/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c +++ b/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c @@ -5,7 +5,6 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <dm/uclass.h> @@ -22,8 +21,6 @@ #include "../common/hw-uid.h" -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_KONTRON_HW_UID) struct uid_otp_loc uid_otp_locations[] = { { diff --git a/board/kontron/osm-s-mx93/osm-s-mx93.c b/board/kontron/osm-s-mx93/osm-s-mx93.c index d4645285771..02bee34ac66 100644 --- a/board/kontron/osm-s-mx93/osm-s-mx93.c +++ b/board/kontron/osm-s-mx93/osm-s-mx93.c @@ -6,7 +6,6 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <dm/uclass.h> @@ -23,13 +22,6 @@ #include "../common/hw-uid.h" -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - return 0; -} - #if IS_ENABLED(CONFIG_KONTRON_HW_UID) struct uid_otp_loc uid_otp_locations[] = { { diff --git a/board/kontron/osm-s-mx93/spl.c b/board/kontron/osm-s-mx93/spl.c index 23a90e351fe..a47fc43c6aa 100644 --- a/board/kontron/osm-s-mx93/spl.c +++ b/board/kontron/osm-s-mx93/spl.c @@ -132,8 +132,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - spl_early_init(); preloader_console_init(); diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index 2ee97169c6f..f71fa57b808 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -15,8 +15,6 @@ #include <linux/delay.h> #include <linux/kernel.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/lg/star/star.c b/board/lg/star/star.c index 0b4a433a5df..ab700cbe828 100644 --- a/board/lg/star/star.c +++ b/board/lg/star/star.c @@ -46,6 +46,8 @@ void pinmux_init(void) #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *fdt, struct bd_info *bd) { - return star_fix_panel(fdt); + star_fix_panel(fdt); + + return 0; } #endif diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index c4b6c37e495..dc683bd082a 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -393,9 +393,9 @@ int board_fdt_blob_setup(void **fdtp) int board_fit_config_name_match(const char *name) { u8 rev_id = get_som_rev(); - char board[12]; + char board[15]; - sprintf(board, "imx28-btt3-%d", rev_id); + sprintf(board, "imx28-btt3-%u", rev_id); if (!strncmp(name, board, sizeof(board))) return 0; diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS new file mode 100644 index 00000000000..446a9e8e53c --- /dev/null +++ b/board/mediatek/MAINTAINERS @@ -0,0 +1,20 @@ +MT8365 EVK +M: Julien Masson <[email protected]> +S: Maintained +F: configs/mt8365_evk_defconfig + +MT8370 EVK +M: Macpaul Lin <[email protected]> +S: Maintained +F: configs/mt8370_evk_defconfig + +MT8390 EVK +M: Julien Masson <[email protected]> +M: Macpaul Lin <[email protected]> +S: Maintained +F: configs/mt8390_evk_defconfig + +MT8395 EVK +M: Macpaul Lin <[email protected]> +S: Maintained +F: configs/mt8395_evk_defconfig diff --git a/board/mediatek/mt7622/Makefile b/board/mediatek/mt7622/Makefile index 64f101337bf..35f3136e833 100644 --- a/board/mediatek/mt7622/Makefile +++ b/board/mediatek/mt7622/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y += mt7622_rfb.o +obj-y += diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c deleted file mode 100644 index 405f393aade..00000000000 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 MediaTek Inc. - * Author: Sam Shih <[email protected]> - */ - -#include <config.h> -#include <env.h> -#include <init.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mediatek/mt8365_evk/MAINTAINERS b/board/mediatek/mt8365_evk/MAINTAINERS deleted file mode 100644 index e0d65efe812..00000000000 --- a/board/mediatek/mt8365_evk/MAINTAINERS +++ /dev/null @@ -1,5 +0,0 @@ -MT8365 EVK -M: Julien Masson <[email protected]> -S: Maintained -F: board/mediatek/mt8365_evk/ -F: configs/mt8365_evk_defconfig diff --git a/board/mediatek/mt8365_evk/Makefile b/board/mediatek/mt8365_evk/Makefile deleted file mode 100644 index 90fc92b28c5..00000000000 --- a/board/mediatek/mt8365_evk/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-y += mt8365_evk.o diff --git a/board/mediatek/mt8365_evk/mt8365_evk.c b/board/mediatek/mt8365_evk/mt8365_evk.c deleted file mode 100644 index 41a6febf03d..00000000000 --- a/board/mediatek/mt8365_evk/mt8365_evk.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 BayLibre SAS - * Author: Julien Masson <[email protected]> - */ - -#include <asm/armv8/mmu.h> - -static struct mm_region mt8365_evk_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0xc0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8365_evk_mem_map; diff --git a/board/mediatek/mt8390_evk/MAINTAINERS b/board/mediatek/mt8390_evk/MAINTAINERS deleted file mode 100644 index d46b8b2e156..00000000000 --- a/board/mediatek/mt8390_evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MT8390 EVK -M: Julien Masson <[email protected]> -M: Macpaul Lin <[email protected]> -S: Maintained -F: board/mediatek/mt8390_evk/ -F: configs/mt8390_evk_defconfig diff --git a/board/mediatek/mt8390_evk/Makefile b/board/mediatek/mt8390_evk/Makefile deleted file mode 100644 index a26d46838c4..00000000000 --- a/board/mediatek/mt8390_evk/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-y += mt8390_evk.o diff --git a/board/mediatek/mt8390_evk/mt8390_evk.c b/board/mediatek/mt8390_evk/mt8390_evk.c deleted file mode 100644 index 1ca40366a55..00000000000 --- a/board/mediatek/mt8390_evk/mt8390_evk.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2026 BayLibre SAS - * Author: Julien Masson <[email protected]> - */ - -#include <linux/types.h> -#include <asm/armv8/mmu.h> - -int board_init(void) -{ - return 0; -} - -static struct mm_region mt8390_evk_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8390_evk_mem_map; diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig index d38e56c742d..3640cf69f3a 100644 --- a/board/microchip/mpfs_generic/Kconfig +++ b/board/microchip/mpfs_generic/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_MMC imply DOS_PARTITION imply EFI_PARTITION - imply IP_DYN imply ISO_PARTITION imply PHY_LIB imply PHY_VITESSE diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c index 6ee1c5c52a1..bcb31564a73 100644 --- a/board/mntre/imx8mq_reform2/imx8mq_reform2.c +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -8,7 +8,6 @@ #include <init.h> #include <malloc.h> #include <errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include <miiphy.h> #include <netdev.h> @@ -26,8 +25,6 @@ #include <linux/delay.h> #include <power/pmic.h> -DECLARE_GLOBAL_DATA_PTR; - #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) static iomux_v3_cfg_t const wdog_pads[] = { diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c index b1ce014bd55..b2f763dcc02 100644 --- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -18,8 +18,6 @@ #include <asm-generic/gpio.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c index b1b5561838d..902179aad29 100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@ -17,7 +17,6 @@ #include <log.h> #include <mmc.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/ddr.h> @@ -33,8 +32,6 @@ #include <power/pmic.h> #include <power/rn5t567_pmic.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/nxp/common/emc2305.c b/board/nxp/common/emc2305.c index 50252bb5007..7e5151eaf5f 100644 --- a/board/nxp/common/emc2305.c +++ b/board/nxp/common/emc2305.c @@ -4,15 +4,13 @@ * */ +#include <config.h> #include <command.h> #include <i2c.h> -#include <asm/global_data.h> #include <asm/io.h> #include "emc2305.h" -DECLARE_GLOBAL_DATA_PTR; - void set_fan_speed(u8 data, int chip_addr) { u8 index; diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env index 299b8472c74..d59bd6fd5ed 100644 --- a/board/nxp/imx8mm_evk/imx8mm_evk.env +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -6,7 +6,7 @@ boot_targets=mmc1 mmc2 dhcp bootm_size=0x10000000 console=ttymxc1,115200 fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x49000000 initrd_addr=0x48080000 image=Image diff --git a/board/nxp/imx8mm_evk/spl.c b/board/nxp/imx8mm_evk/spl.c index cd251d274ff..50bae3a2bcc 100644 --- a/board/nxp/imx8mm_evk/spl.c +++ b/board/nxp/imx8mm_evk/spl.c @@ -10,7 +10,6 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/arch/clock.h> @@ -28,8 +27,6 @@ #include <power/pmic.h> #include <power/pca9450.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -109,8 +106,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - timer_init(); /* Clear the BSS. */ diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env index 487893f9287..cffa83bf792 100644 --- a/board/nxp/imx8mn_evk/imx8mn_evk.env +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -6,7 +6,7 @@ boot_targets=mmc1 mmc2 dhcp bootm_size=0x10000000 console=ttymxc1,115200 fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x49000000 initrd_addr=0x48080000 image=Image diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.c b/board/nxp/imx8mp_evk/imx8mp_evk.c index 489e5ad4d43..e17100e51ec 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.c +++ b/board/nxp/imx8mp_evk/imx8mp_evk.c @@ -28,6 +28,13 @@ struct efi_capsule_update_info update_info = { }; #endif /* EFI_HAVE_CAPSULE_SUPPORT */ +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) +int board_mmc_get_env_dev(int devno) +{ + return devno; +} +#endif + int board_late_init(void) { #if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env index 18cdf3da056..e994b93b168 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.env +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -7,7 +7,7 @@ bootm_size=0x10000000 console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 fdt_addr_r=0x43000000 fdt_addr=0x43000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image ip_dyn=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c index 5b4aac42830..27cd82e745a 100644 --- a/board/nxp/imx8mp_evk/spl.c +++ b/board/nxp/imx8mp_evk/spl.c @@ -102,8 +102,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - ret = spl_early_init(); if (ret) { debug("spl_init() failed: %d\n", ret); diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env index cab8c6b70bf..6575dd7cb07 100644 --- a/board/nxp/imx8mq_evk/imx8mq_evk.env +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -5,7 +5,7 @@ boot_targets=mmc1 mmc2 dhcp bootm_size=0x10000000 console=ttymxc0,115200 fdt_addr_r=0x43000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE initrd_addr=0x43800000 image=Image ip_dyn=yes diff --git a/board/nxp/imx8qm_mek/imx8qm_mek.c b/board/nxp/imx8qm_mek/imx8qm_mek.c index 72527f774ca..56f577714e7 100644 --- a/board/nxp/imx8qm_mek/imx8qm_mek.c +++ b/board/nxp/imx8qm_mek/imx8qm_mek.c @@ -7,7 +7,6 @@ #include <env.h> #include <errno.h> #include <init.h> -#include <asm/global_data.h> #include <linux/libfdt.h> #include <fdt_support.h> #include <asm/io.h> @@ -18,8 +17,6 @@ #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/nxp/imx8qxp_mek/imx8qxp_mek.c b/board/nxp/imx8qxp_mek/imx8qxp_mek.c index adb9556a021..4bf6645b893 100644 --- a/board/nxp/imx8qxp_mek/imx8qxp_mek.c +++ b/board/nxp/imx8qxp_mek/imx8qxp_mek.c @@ -7,7 +7,6 @@ #include <env.h> #include <errno.h> #include <init.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/libfdt.h> #include <fsl_esdhc_imx.h> @@ -21,8 +20,6 @@ #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.c b/board/nxp/imx8ulp_evk/imx8ulp_evk.c index cc34ecdec20..f4e85efb931 100644 --- a/board/nxp/imx8ulp_evk/imx8ulp_evk.c +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.c @@ -101,11 +101,6 @@ int board_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_late_init(void) { ulong addr; diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.env b/board/nxp/imx8ulp_evk/imx8ulp_evk.env index 52d7f447029..da97631e03e 100644 --- a/board/nxp/imx8ulp_evk/imx8ulp_evk.env +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.env @@ -23,7 +23,7 @@ mmcdev=CONFIG_SYS_MMC_ENV_DEV mmcpart=1 image=Image cntr_file=os_cntr_signed.bin -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE console=ttyLP1,115200 earlycon bootm_size=0x10000000 boot_fit=no diff --git a/board/nxp/imx8ulp_evk/spl.c b/board/nxp/imx8ulp_evk/spl.c index 162b3a1a2e0..2d52e16007d 100644 --- a/board/nxp/imx8ulp_evk/spl.c +++ b/board/nxp/imx8ulp_evk/spl.c @@ -74,8 +74,6 @@ void spl_board_init(void) if (ret) return; - board_early_init_f(); - preloader_console_init(); puts("Normal Boot\n"); diff --git a/board/nxp/imx91_evk/imx91_evk.env b/board/nxp/imx91_evk/imx91_evk.env index 6c10784cf61..d669c6e3133 100644 --- a/board/nxp/imx91_evk/imx91_evk.env +++ b/board/nxp/imx91_evk/imx91_evk.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx91_frdm/imx91_frdm.env b/board/nxp/imx91_frdm/imx91_frdm.env index b0450ff576c..557e508bd6a 100644 --- a/board/nxp/imx91_frdm/imx91_frdm.env +++ b/board/nxp/imx91_frdm/imx91_frdm.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env index d5ed216f54b..b2ed1901a2b 100644 --- a/board/nxp/imx93_evk/imx93_evk.env +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx93_frdm/imx93_frdm.c b/board/nxp/imx93_frdm/imx93_frdm.c index fb78a9bd036..e187de74a72 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.c +++ b/board/nxp/imx93_frdm/imx93_frdm.c @@ -90,11 +90,6 @@ static int clear_pd_alert(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { return 0; diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env index 111f38ed72a..9af3bdfd714 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.env +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=1 mmcpart=1 diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 006c752d071..068091ba0e9 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -156,8 +156,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - spl_early_init(); preloader_console_init(); diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env index 6c10784cf61..d669c6e3133 100644 --- a/board/nxp/imx93_qsb/imx93_qsb.env +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c index 2aeb21c1de7..4731b79b55d 100644 --- a/board/nxp/imx94_evk/imx94_evk.c +++ b/board/nxp/imx94_evk/imx94_evk.c @@ -26,10 +26,3 @@ int board_late_init(void) return 0; } - -int board_phys_sdram_size(phys_size_t *size) -{ - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; - - return 0; -} diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env index 2baf1bbadcb..894f5975812 100644 --- a/board/nxp/imx94_evk/imx94_evk.env +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -28,7 +28,7 @@ fdt_addr=0x93000000 cntr_addr=0xA8000000 cntr_file=os_cntr_signed.bin boot_fit=no -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE bootm_size=0x10000000 mmcdev=CONFIG_SYS_MMC_ENV_DEV mmcautodetect=yes diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c index cc5b7f9ef0f..6eb0fff99f4 100644 --- a/board/nxp/imx94_evk/spl.c +++ b/board/nxp/imx94_evk/spl.c @@ -46,6 +46,16 @@ void spl_board_init(void) printf("Fail to start RNG: %d\n", ret); } +static void xspi_nor_reset(void) +{ + int ret; + u32 resp = 0; + + ret = ele_set_gmid(&resp); + if (ret) + printf("Fail to set GMID: %d, resp 0x%x\n", ret, resp); +} + /* SCMI support by default */ void board_init_f(ulong dummy) { @@ -76,5 +86,7 @@ void board_init_f(ulong dummy) get_reset_reason(true, false); + xspi_nor_reset(); + board_init_r(NULL, 0); } diff --git a/board/nxp/imx952_evk/Kconfig b/board/nxp/imx952_evk/Kconfig new file mode 100644 index 00000000000..96f01323aca --- /dev/null +++ b/board/nxp/imx952_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX952_EVK + +config SYS_BOARD + default "imx952_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx952_evk" + +endif diff --git a/board/nxp/imx952_evk/MAINTAINERS b/board/nxp/imx952_evk/MAINTAINERS new file mode 100644 index 00000000000..cc004f9467e --- /dev/null +++ b/board/nxp/imx952_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX952 EVK BOARD +M: Alice Guo <[email protected]> +S: Maintained +F: board/nxp/imx952_evk/ +F: include/configs/imx952_evk.h +F: configs/imx952_evk_defconfig diff --git a/board/nxp/imx952_evk/Makefile b/board/nxp/imx952_evk/Makefile new file mode 100644 index 00000000000..1581721dc78 --- /dev/null +++ b/board/nxp/imx952_evk/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Add include path for NXP device tree header files from Linux. +ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/ + +obj-y += imx952_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c new file mode 100644 index 00000000000..2a61817939e --- /dev/null +++ b/board/nxp/imx952_evk/imx952_evk.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025-2026 NXP + */ + +#include <env.h> +#include <init.h> +#include <asm/arch/sys_proto.h> + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env new file mode 100644 index 00000000000..6ecaf9724c1 --- /dev/null +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -0,0 +1,137 @@ +#ifdef CONFIG_ANDROID_SUPPORT +splashpos=m,m +splashimage=0x9FFF0000 +emmc_dev=0 +sd_dev=1 +#else + +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx952-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +domu-android-auto=no +xenhyper_bootargs=console=dtuart dom0_mem=4096M dom0_max_vcpus=2 pci-passthrough=on +xenlinux_bootargs= +xenlinux_console=hvc0 earlycon=xen +xenlinux_addr=0x9c000000 +dom0fdt_file=CONFIG_DEFAULT_FDT_FILE +xenboot_common=${get_cmd} ${loadaddr} xen; + ${get_cmd} ${fdt_addr} ${dom0fdt_file}; + ${get_cmd} ${xenlinux_addr} ${image}; + fdt addr ${fdt_addr}; + fdt resize 256; + fdt mknode /chosen module@0; + fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; + fdt set /chosen/module@0 bootargs "${bootargs} ${xenlinux_bootargs}"; + fdt set /soc/bus@49000000/iommu@490d0000 status disabled; + fdt set /chosen/module@0 compatible "xen,linux-zimage" "xen,multiboot-module"; + setenv bootargs ${xenhyper_bootargs}; + booti ${loadaddr} - ${fdt_addr}; +xennetboot=setenv get_cmd dhcp;setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run netargs;run xenboot_common; +xenmmcboot=setenv get_cmd "fatload mmc ${mmcdev}:${mmcpart}";setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run mmcargs;run xenboot_common; + +sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000; fdt addr ${fdt_addr_r}; + fdt set /soc/bus@44000000/mailbox@445b0000/sram@445b1000/scmi-sram-section@0 reg <0x00000000 0x00000080>; + fdt rm /soc/mailbox@47530000; + fdt rm /soc/usb@4c010010; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; + +#endif diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c new file mode 100644 index 00000000000..de9256dc267 --- /dev/null +++ b/board/nxp/imx952_evk/spl.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025-2026 NXP + */ + +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <hang.h> +#include <init.h> +#include <linux/delay.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + case USB2_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +static void xspi_nor_reset(void) +{ + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("GPIO5_11", &desc); + if (ret) { + printf("%s lookup GPIO5_11 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "XSPI_RST_B"); + if (ret) { + printf("%s request XSPI_RST_B failed ret = %d\n", __func__, ret); + return; + } + + /* assert the XSPI_RST_B */ + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + udelay(200); /* 50 ns at least, so use 200ns */ + dm_gpio_set_value(&desc, 0); /* deassert the XSPI_RST_B */ +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_SPL_RECOVER_DATA_SECTION + if (IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); +#endif + + timer_init(); + + /* Need dm_init() to run before any SCMI calls can be made. */ + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + xspi_nor_reset(); + + board_init_r(NULL, 0); +} + +#ifdef CONFIG_ANDROID_SUPPORT +int board_get_emmc_id(void) +{ + return 0; +} +#endif diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c index 620a69b53e5..99a37e0593f 100644 --- a/board/nxp/imx95_evk/imx95_evk.c +++ b/board/nxp/imx95_evk/imx95_evk.c @@ -14,10 +14,3 @@ int board_late_init(void) return 0; } - -int board_phys_sdram_size(phys_size_t *size) -{ - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; - - return 0; -} diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env index a7309d734b0..19f9bd5c16e 100644 --- a/board/nxp/imx95_evk/imx95_evk.env +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -12,7 +12,7 @@ fdt_addr=0x93000000 cntr_addr=0xA8000000 cntr_file=os_cntr_signed.bin boot_fit=no -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE bootm_size=0x10000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcautodetect=yes diff --git a/board/nxp/mx6sllevk/mx6sllevk.c b/board/nxp/mx6sllevk/mx6sllevk.c index 9e39e39ac90..3d2397c52c1 100644 --- a/board/nxp/mx6sllevk/mx6sllevk.c +++ b/board/nxp/mx6sllevk/mx6sllevk.c @@ -76,11 +76,6 @@ int power_init_board(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* Address of boot parameters */ diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index d80cfd4ab27..ac91da3f4f6 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -199,11 +199,6 @@ int board_ehci_hcd_init(int port) } #endif -int board_early_init_f(void) -{ - return 0; -} - #ifdef CONFIG_FSL_QSPI int board_qspi_init(void) { diff --git a/board/nxp/mx6ullevk/mx6ullevk.c b/board/nxp/mx6ullevk/mx6ullevk.c index 189eddefea3..7a02b571c56 100644 --- a/board/nxp/mx6ullevk/mx6ullevk.c +++ b/board/nxp/mx6ullevk/mx6ullevk.c @@ -41,11 +41,6 @@ int mmc_map_to_kernel_blk(int devno) return devno; } -int board_early_init_f(void) -{ - return 0; -} - #ifdef CONFIG_FEC_MXC static int setup_fec(int fec_id) { diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index b2bb6678c23..78136c1620a 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -13,9 +13,6 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_LED_STATUS -#include <status_led.h> -#endif #include <linux/delay.h> DECLARE_GLOBAL_DATA_PTR; @@ -61,9 +58,5 @@ int board_init(void) /* Adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_STATE); -#endif - return 0; } diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig index e4bd8903aab..b646aa8cbb2 100644 --- a/board/openpiton/riscv64/Kconfig +++ b/board/openpiton/riscv64/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply RISCV_TIMER imply SPL_RISCV_ACLINT imply CMD_CPU - imply SPL_CPU_SUPPORT + imply SPL_CPU imply SPL_SMP imply SPL_MMC imply SMP diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index 10469aecd0b..b55e92fb051 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -16,11 +16,6 @@ int dram_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - static int setup_fec_clock(void) { if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) { diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index a72f66ee3f5..6afd03086f7 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -19,13 +19,13 @@ config PHYTEC_IMX8M_SOM_DETECTION Support of I2C EEPROM based SoM detection. Supported for PHYTEC i.MX8MM/i.MX8MP boards -config PHYTEC_IMX93_SOM_DETECTION - bool "Support SoM detection for i.MX93 PHYTEC platforms" +config PHYTEC_IMX91_93_SOM_DETECTION + bool "Support SoM detection for i.MX91/93 PHYTEC platforms" depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION default y help Support of I2C EEPROM based SoM detection. Supported - for PHYTEC i.MX93 based boards + for PHYTEC i.MX91/93 based boards config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 948f9dab626..e09dea01d49 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -10,4 +10,4 @@ endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o -obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o +obj-$(CONFIG_ARCH_IMX9) += imx91_93_som_detection.o diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx91_93_som_detection.c index eb9574d43b5..bcc5500ae9f 100644 --- a/board/phytec/common/imx93_som_detection.c +++ b/board/phytec/common/imx91_93_som_detection.c @@ -10,18 +10,19 @@ #include <i2c.h> #include <u-boot/crc.h> -#include "imx93_som_detection.h" +#include "imx91_93_som_detection.h" extern struct phytec_eeprom_data eeprom_data; -#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) +#if IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) /* Check if the SoM is actually one of the following products: + * - i.MX91 * - i.MX93 * * Returns 0 in case it's a known SoM. Otherwise, returns 1. */ -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) { u8 som; @@ -35,7 +36,7 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) som = data->payload.data.data_api2.som_no; debug("%s: som id: %u\n", __func__, som); - if (som == PHYTEC_IMX93_SOM && is_imx93()) + if (som == PHYTEC_IMX91_93_SOM && (is_imx91() || is_imx93())) return 0; pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); @@ -43,15 +44,15 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) } /* - * Filter PHYTEC i.MX93 SoM options by option index + * Filter PHYTEC i.MX91/93 SoM options by option index * * Returns: * - option value * - PHYTEC_EEPROM_INVAL when the data is invalid * */ -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) { char *opt; u8 opt_id; @@ -73,39 +74,41 @@ u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, } /* - * Filter PHYTEC i.MX93 SoM voltage + * Filter PHYTEC i.MX91/93 SoM voltage * * Returns: - * - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3 + * - PHYTEC_IMX91_93_VOLTAGE_1V8 or PHYTEC_IMX91_93_VOLTAGE_3V3 * - PHYTEC_EEPROM_INVAL when the data is invalid * */ -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data) +enum phytec_imx91_93_voltage __maybe_unused +phytec_imx91_93_get_voltage(struct phytec_eeprom_data *data) { - u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT); + u8 option = phytec_imx91_93_get_opt(data, PHYTEC_IMX91_93_OPT_FEAT); if (option == PHYTEC_EEPROM_INVAL) - return PHYTEC_IMX93_VOLTAGE_INVALID; - return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3; + return PHYTEC_IMX91_93_VOLTAGE_INVALID; + return (option & 0x01) ? PHYTEC_IMX91_93_VOLTAGE_1V8 : + PHYTEC_IMX91_93_VOLTAGE_3V3; } #else -inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) { return 1; } -inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) +inline u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) { return PHYTEC_EEPROM_INVAL; } -inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage +inline enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage (struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */ +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) */ diff --git a/board/phytec/common/imx91_93_som_detection.h b/board/phytec/common/imx91_93_som_detection.h new file mode 100644 index 00000000000..05ea4cf0868 --- /dev/null +++ b/board/phytec/common/imx91_93_som_detection.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <[email protected]> + */ + +#ifndef _PHYTEC_IMX91_93_SOM_DETECTION_H +#define _PHYTEC_IMX91_93_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX91_93_SOM 77 + +enum phytec_imx91_93_option_index { + PHYTEC_IMX91_93_OPT_DDR = 0, + PHYTEC_IMX91_93_OPT_EMMC = 1, + PHYTEC_IMX91_93_OPT_CPU = 2, + PHYTEC_IMX91_93_OPT_FREQ = 3, + PHYTEC_IMX91_93_OPT_NPU = 4, + PHYTEC_IMX91_93_OPT_DISP = 5, + PHYTEC_IMX91_93_OPT_ETH = 6, + PHYTEC_IMX91_93_OPT_FEAT = 7, + PHYTEC_IMX91_93_OPT_TEMP = 8, + PHYTEC_IMX91_93_OPT_BOOT = 9, + PHYTEC_IMX91_93_OPT_LED = 10, + PHYTEC_IMX91_93_OPT_EEPROM = 11, +}; + +enum phytec_imx91_93_voltage { + PHYTEC_IMX91_93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_VOLTAGE_3V3 = 0, + PHYTEC_IMX91_93_VOLTAGE_1V8 = 1, +}; + +enum phytec_imx91_93_ddr_eeprom_code { + PHYTEC_IMX91_93_DDR_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_LPDDR4X_512MB = 0, + PHYTEC_IMX91_93_LPDDR4X_1GB = 1, + PHYTEC_IMX91_93_LPDDR4X_2GB = 2, + PHYTEC_IMX91_93_LPDDR4_512MB = 3, + PHYTEC_IMX91_93_LPDDR4_1GB = 4, + PHYTEC_IMX91_93_LPDDR4_2GB = 5, +}; + +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx); +enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage + (struct phytec_eeprom_data *data); + +#endif /* _PHYTEC_IMX91_93_SOM_DETECTION_H */ diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h deleted file mode 100644 index a0803b47cbe..00000000000 --- a/board/phytec/common/imx93_som_detection.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Author: Primoz Fiser <[email protected]> - */ - -#ifndef _PHYTEC_IMX93_SOM_DETECTION_H -#define _PHYTEC_IMX93_SOM_DETECTION_H - -#include "phytec_som_detection.h" - -#define PHYTEC_IMX93_SOM 77 - -enum phytec_imx93_option_index { - PHYTEC_IMX93_OPT_DDR = 0, - PHYTEC_IMX93_OPT_EMMC = 1, - PHYTEC_IMX93_OPT_CPU = 2, - PHYTEC_IMX93_OPT_FREQ = 3, - PHYTEC_IMX93_OPT_NPU = 4, - PHYTEC_IMX93_OPT_DISP = 5, - PHYTEC_IMX93_OPT_ETH = 6, - PHYTEC_IMX93_OPT_FEAT = 7, - PHYTEC_IMX93_OPT_TEMP = 8, - PHYTEC_IMX93_OPT_BOOT = 9, - PHYTEC_IMX93_OPT_LED = 10, - PHYTEC_IMX93_OPT_EEPROM = 11, -}; - -enum phytec_imx93_voltage { - PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_VOLTAGE_3V3 = 0, - PHYTEC_IMX93_VOLTAGE_1V8 = 1, -}; - -enum phytec_imx93_ddr_eeprom_code { - PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_LPDDR4X_512MB = 0, - PHYTEC_IMX93_LPDDR4X_1GB = 1, - PHYTEC_IMX93_LPDDR4X_2GB = 2, - PHYTEC_IMX93_LPDDR4_512MB = 3, - PHYTEC_IMX93_LPDDR4_1GB = 4, - PHYTEC_IMX93_LPDDR4_2GB = 5, -}; - -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data); -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx); -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage - (struct phytec_eeprom_data *data); - -#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */ diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env index f064bbe3d31..7ea7bde86a1 100644 --- a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env @@ -2,7 +2,7 @@ boot_script_dhcp=net_boot_fit.scr.uimg console=ttymxc3,CONFIG_BAUDRATE emmc_dev=2 /* This is needed by built-in uuu flash scripts */ fdt_addr_r=0x40480000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x404a0000 ip_dyn=yes kernel_addr_r=0x40a00000 diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c index d704d588579..aa22ad0030c 100644 --- a/board/phytec/imx8mp-libra-fpsc/spl.c +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -8,11 +8,7 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> #include <hang.h> #include <init.h> #include <log.h> @@ -24,8 +20,6 @@ #include "../common/imx8m_som_detection.h" #endif -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 int spl_board_boot_device(enum boot_device boot_dev_spl) @@ -49,45 +43,32 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(0, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } @@ -123,8 +104,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index eeb7cd6899a..e7b9cc0791c 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -13,7 +13,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml index 0f34b8c1bc0..38bcd46e7e7 100644 --- a/board/phytec/phycore_am62ax/rm-cfg.yaml +++ b/board/phytec/phycore_am62ax/rm-cfg.yaml @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 1038 - num_resource: 497 + num_resource: 496 type: 1805 host_id: 128 reserved: 0 diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index eeb7cd6899a..e7b9cc0791c 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -13,7 +13,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_am62x/rm-cfg.yaml b/board/phytec/phycore_am62x/rm-cfg.yaml index 26d99b03b80..f800fb28a69 100644 --- a/board/phytec/phycore_am62x/rm-cfg.yaml +++ b/board/phytec/phycore_am62x/rm-cfg.yaml @@ -525,7 +525,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 67d2b87f144..6cfe64e676f 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -12,7 +12,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_am68x/phycore_am68x.env b/board/phytec/phycore_am68x/phycore_am68x.env index 4908055b542..0c61e645c88 100644 --- a/board/phytec/phycore_am68x/phycore_am68x.env +++ b/board/phytec/phycore_am68x/phycore_am68x.env @@ -7,7 +7,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index f6ae0bf0308..9f6a4ec704d 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -5,14 +5,11 @@ */ #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> #include <miiphy.h> -DECLARE_GLOBAL_DATA_PTR; - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index f6d0c0553b5..7cd601f8cd5 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -2,7 +2,7 @@ boot_script_dhcp=net_boot_fit.scr.uimg console=ttymxc2,CONFIG_BAUDRATE emmc_dev=2 /* This is needed by built-in uuu flash scripts */ fdt_addr_r=0x40480000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x404a0000 ip_dyn=yes kernel_addr_r=0x40a00000 diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index faff064779c..e688793bc74 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -8,7 +8,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mm_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/sections.h> @@ -19,8 +18,6 @@ #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index b345dc7c985..5f0a7ee6a94 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -5,7 +5,6 @@ */ #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> @@ -17,8 +16,6 @@ #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index c339c315c30..652761d1f99 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -4,7 +4,7 @@ emmc_dev=2 /* This is needed by built-in uuu flash scripts */ fastboot_raw_partition_all=0 4194304 fastboot_raw_partition_bootloader=64 8128 fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x49000000 ip_dyn=yes kernel_addr_r=0x5A080000 diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index cb8e450b995..fc6f5104925 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -8,7 +8,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/mxc_i2c.h> @@ -23,8 +22,6 @@ #include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 @@ -120,45 +117,32 @@ out: ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(0, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } @@ -196,8 +180,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx91_93/Kconfig b/board/phytec/phycore_imx91_93/Kconfig new file mode 100644 index 00000000000..87fd915e5a8 --- /dev/null +++ b/board/phytec/phycore_imx91_93/Kconfig @@ -0,0 +1,47 @@ + +if TARGET_PHYCORE_IMX91 || TARGET_PHYCORE_IMX93 + +config SYS_BOARD + default "phycore_imx91_93" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_imx91_93" + +config PHYCORE_IMX91_93_RAM_TYPE_FIX + bool "Set phyCORE-i.MX91/93 RAM type and size fix instead of detecting" + default false + help + RAM type and size is being automatically detected with the help + of the PHYTEC EEPROM introspection data. + Set RAM type to a fix value instead. + +choice + prompt "phyCORE-i.MX91/93 RAM type" + depends on PHYCORE_IMX91_93_RAM_TYPE_FIX + default PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB + bool "LPDDR4 1GB RAM" + help + Set RAM type fixed to LPDDR4 and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + bool "LPDDR4X 1GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB + bool "LPDDR4X 2GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB + for phyCORE-i.MX91/93. + +endchoice + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/phycore_imx91_93/MAINTAINERS b/board/phytec/phycore_imx91_93/MAINTAINERS new file mode 100644 index 00000000000..573d1c36a5e --- /dev/null +++ b/board/phytec/phycore_imx91_93/MAINTAINERS @@ -0,0 +1,16 @@ +phyCORE-i.MX91/93 +M: Mathieu Othacehe <[email protected]> +R: Christoph Stoidner <[email protected]> +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ +S: Maintained +F: arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi +F: arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi +F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +F: board/phytec/phycore_imx91_93/ +F: board/phytec/common/imx91_93_som_detection.c +F: board/phytec/common/imx91_93_som_detection.h +F: configs/imx91-phycore_defconfig +F: configs/imx93-phycore_defconfig +F: include/configs/phycore_imx91_93.h +F: doc/board/phytec/imx91-93-phycore.rst diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx91_93/Makefile index dd5085e160f..976ecb306f7 100644 --- a/board/phytec/phycore_imx93/Makefile +++ b/board/phytec/phycore_imx91_93/Makefile @@ -7,8 +7,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += phycore-imx93.o +obj-y += phycore-imx91-93.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing.o +obj-y += spl.o +ifdef CONFIG_IMX91 +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx91.o +else +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx93.o +endif endif diff --git a/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c new file mode 100644 index 00000000000..ddc8094f080 --- /dev/null +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c @@ -0,0 +1,1998 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <[email protected]> + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x13542110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E88CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00A000A0}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00A0180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABA0068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x004C004C}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0x61f}, + {0x10149, 0x61f}, + {0x11049, 0x61f}, + {0x11149, 0x61f}, + {0x110049, 0x61f}, + {0x110149, 0x61f}, + {0x111049, 0x61f}, + {0x111149, 0x61f}, + {0x210049, 0x61f}, + {0x210149, 0x61f}, + {0x211049, 0x61f}, + {0x211149, 0x61f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x104}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x104}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x104}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x2352}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x2352}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a00}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a00}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x2309}, + {0x54034, 0x4400}, + {0x54035, 0x49}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x2309}, + {0x5403a, 0x4400}, + {0x5403b, 0x49}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c index f1261f6a92a..f1261f6a92a 100644 --- a/board/phytec/phycore_imx93/lpddr4_timing.c +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx91_93/phycore-imx91-93.c index cfc6d91f20f..2605a3bd09e 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx91_93/phycore-imx91-93.c @@ -7,14 +7,11 @@ */ #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> #include <fdt_support.h> -#include "../common/imx93_som_detection.h" - -DECLARE_GLOBAL_DATA_PTR; +#include "../common/imx91_93_som_detection.h" #define EEPROM_ADDR 0x50 @@ -44,6 +41,11 @@ int board_late_init(void) case MMC1_BOOT: env_set_ulong("mmcdev", 0); break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; default: break; } @@ -53,13 +55,13 @@ int board_late_init(void) static void emmc_fixup(void *blob, struct phytec_eeprom_data *data) { - enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data); + enum phytec_imx91_93_voltage voltage = phytec_imx91_93_get_voltage(data); int offset; - if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID) + if (voltage == PHYTEC_IMX91_93_VOLTAGE_INVALID) goto err; - if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) { + if (voltage == PHYTEC_IMX91_93_VOLTAGE_1V8) { offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc", 0x42850000); if (offset) diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx91_93/phycore_imx91_93.env index 4e89c4ae26c..a39359869d6 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx91_93/phycore_imx91_93.env @@ -4,11 +4,13 @@ boot_script_dhcp=net_boot_fit.scr.uimg console=ttyLP0 emmc_dev=0 /* This is needed by built-in uuu flash scripts */ fdt_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x900c0000 ip_dyn=yes kernel_addr_r=0x88000000 nfsroot=/srv/nfs +#ifdef CONFIG_IMX93 prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" +#endif scriptaddr=0x83500000 sd_dev=1 /* This is needed by built-in uuu flash scripts */ diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx91_93/spl.c index aa7d562911a..92441c5af32 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx91_93/spl.c @@ -19,7 +19,7 @@ #include <power/pca9450.h> #include <spl.h> -#include "../common/imx93_som_detection.h" +#include "../common/imx91_93_som_detection.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,32 +50,38 @@ void spl_board_init(void) void spl_dram_init(void) { int ret; - enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; + enum phytec_imx91_93_ddr_eeprom_code ddr_opt = PHYTEC_IMX91_93_DDR_INVALID; ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); - if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) goto out; - ret = phytec_imx93_detect(NULL); + ret = phytec_imx91_93_detect(NULL); if (!ret) phytec_print_som_info(NULL); - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) { - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB; - else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB; + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_2GB; } else { - ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR); + ddr_opt = phytec_imx91_93_get_opt(NULL, PHYTEC_IMX91_93_OPT_DDR); } switch (ddr_opt) { - case PHYTEC_IMX93_LPDDR4X_1GB: - if (is_voltage_mode(VOLT_LOW_DRIVE)) + case PHYTEC_IMX91_93_LPDDR4_1GB: + /* Timings statically set for i.MX91 LPDDR4 1GB. */ + break; + case PHYTEC_IMX91_93_LPDDR4X_1GB: + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); break; - case PHYTEC_IMX93_LPDDR4X_2GB: - set_dram_timings_2gb_lpddr4x(); + case PHYTEC_IMX91_93_LPDDR4X_2GB: + if (IS_ENABLED(CONFIG_IMX93)) + set_dram_timings_2gb_lpddr4x(); break; default: goto out; @@ -84,7 +90,7 @@ void spl_dram_init(void) return; out: puts("Could not detect correct RAM type and size. Fall back to default.\n"); - if (is_voltage_mode(VOLT_LOW_DRIVE)) + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); ddr_init(&dram_timing); } @@ -185,10 +191,12 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); + if (IS_ENABLED(CONFIG_IMX93)) { + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + } board_init_r(NULL, 0); } diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig deleted file mode 100644 index 09f26e89e33..00000000000 --- a/board/phytec/phycore_imx93/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ - -if TARGET_PHYCORE_IMX93 - -config SYS_BOARD - default "phycore_imx93" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "phycore_imx93" - -config PHYCORE_IMX93_RAM_TYPE_FIX - bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting" - default false - help - RAM type and size is being automatically detected with the help - of the PHYTEC EEPROM introspection data. - Set RAM type to a fix value instead. - -choice - prompt "phyCORE-i.MX93 RAM type" - depends on PHYCORE_IMX93_RAM_TYPE_FIX - default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - bool "LPDDR4X 1GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB - for phyCORE-i.MX93. - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB - bool "LPDDR4X 2GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB - for phyCORE-i.MX93. - -endchoice - -source "board/phytec/common/Kconfig" -endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS deleted file mode 100644 index 0b087bf1ef2..00000000000 --- a/board/phytec/phycore_imx93/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -phyCORE-i.MX93 -M: Mathieu Othacehe <[email protected]> -R: Christoph Stoidner <[email protected]> -W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ -S: Maintained -F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi -F: board/phytec/phycore_imx93/ -F: board/phytec/common/imx93_som_detection.c -F: board/phytec/common/imx93_som_detection.h -F: configs/imx93-phycore_defconfig -F: include/configs/phycore_imx93.h diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index c709d017483..7f0925074fa 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -8,7 +8,6 @@ #include <asm/arch/clock.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <env.h> @@ -18,8 +17,6 @@ #include <miiphy.h> #include <netdev.h> -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c index 6cbd1815cad..c154ad7a1ce 100644 --- a/board/polyhex/imx8mp_debix_model_a/spl.c +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -8,7 +8,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <asm/sections.h> #include <dm/device.h> @@ -20,8 +19,6 @@ #include <power/pmic.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 5178ee6929d..3640ef232c8 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -31,13 +31,6 @@ #include <usb/xhci.h> #include "librem5.h" -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - return 0; -} - #if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION) uint board_mmc_get_env_part(struct mmc *mmc) { diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index ed57554a2bc..a104ee5c2aa 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -29,8 +29,6 @@ #include <linux/usb/gadget.h> #include "librem5.h" -DECLARE_GLOBAL_DATA_PTR; - void spl_dram_init(void) { /* ddr init */ @@ -549,8 +547,6 @@ void board_init_f(ulong dummy) gpio_direction_output(WIFI_EN, 1); #endif - board_early_init_f(); - timer_init(); preloader_console_init(); diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index 4698b9d5e3e..36e4d49046e 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -15,13 +15,10 @@ #include <net.h> #include <usb.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <fdt_support.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - static u32 msm_board_serial(void) { struct mmc *mmc_dev; diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index 12a9273ec4b..236022a99f1 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -10,7 +10,6 @@ #include <init.h> #include <env.h> #include <asm/cache.h> -#include <asm/global_data.h> #include <linux/arm-smccc.h> #include <linux/psci.h> #include <dm.h> @@ -24,8 +23,6 @@ /* Strength (sdc1) */ #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) -DECLARE_GLOBAL_DATA_PTR; - static void sdhci_power_init(void) { const u32 TLMM_PULL_MASK = 0x3; diff --git a/board/renesas/common/gen3-common.c b/board/renesas/common/gen3-common.c index 94da00985d3..5c543807b64 100644 --- a/board/renesas/common/gen3-common.c +++ b/board/renesas/common/gen3-common.c @@ -12,14 +12,12 @@ #include <fdt_support.h> #include <hang.h> #include <init.h> -#include <asm/global_data.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <asm/arch/renesas.h> +#include <asm-generic/u-boot.h> #include <linux/libfdt.h> -DECLARE_GLOBAL_DATA_PTR; - /* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ extern u64 rcar_atf_boot_args[]; diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c index 38fba7a5ea7..ac87f2f08e3 100644 --- a/board/renesas/common/gen4-common.c +++ b/board/renesas/common/gen4-common.c @@ -8,16 +8,14 @@ #include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> #include <asm/armv8/mmu.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-types.h> #include <asm/processor.h> #include <asm/system.h> +#include <asm-generic/u-boot.h> #include <image.h> #include <linux/errno.h> -DECLARE_GLOBAL_DATA_PTR; - static void init_generic_timer(void) { const u32 freq = CONFIG_SYS_CLK_FREQ; diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c index a05a3e8abef..c60a76c5038 100644 --- a/board/renesas/common/gen5-common.c +++ b/board/renesas/common/gen5-common.c @@ -5,15 +5,13 @@ #include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-types.h> #include <asm/processor.h> #include <asm/system.h> +#include <asm-generic/u-boot.h> #include <linux/errno.h> -DECLARE_GLOBAL_DATA_PTR; - static void init_generic_timer(void) { const u32 freq = CONFIG_SYS_CLK_FREQ; diff --git a/board/rockchip/evb_rk3288/MAINTAINERS b/board/rockchip/evb_rk3288/MAINTAINERS index 9857ae33575..60f97d7eb3b 100644 --- a/board/rockchip/evb_rk3288/MAINTAINERS +++ b/board/rockchip/evb_rk3288/MAINTAINERS @@ -1,12 +1,10 @@ EVB-RK3288 M: Lin Huang <[email protected]> S: Maintained -F: arch/arm/dts/rk3288-evb.dts -F: arch/arm/dts/rk3288-evb.dtsi -F: arch/arm/dts/rk3288-evb-u-boot.dtsi +F: arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi F: board/rockchip/evb_rk3288 F: include/configs/evb_rk3288.h -F: configs/evb-rk3288_defconfig +F: configs/evb-rk3288-rk808_defconfig ROCK-PI-N8 M: Jagan Teki <[email protected]> diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c b/board/rockchip/evb_rk3308/evb_rk3308.c index c895da934a9..75536fe117d 100644 --- a/board/rockchip/evb_rk3308/evb_rk3308.c +++ b/board/rockchip/evb_rk3308/evb_rk3308.c @@ -4,9 +4,8 @@ */ #include <adc.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <stdio.h> +#include <linux/kernel.h> #define KEY_DOWN_MIN_VAL 0 #define KEY_DOWN_MAX_VAL 30 diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index 602216854ba..e41cfefe375 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -10,8 +10,6 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 68edd1ec282..2ba2d6330fd 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -9,7 +9,6 @@ #include <env.h> #include <fdtdec.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <errno.h> #include <i2c.h> @@ -36,8 +35,6 @@ #include <samsung/misc.h> #include <tmu.h> -DECLARE_GLOBAL_DATA_PTR; - static int exynos_set_regulator(const char *name, uint uv) { struct udevice *dev; diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index c134a9d70e2..85e564f27ee 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -8,7 +8,6 @@ #include <command.h> #include <env.h> #include <libtizen.h> -#include <asm/global_data.h> #include <linux/delay.h> #include <linux/printk.h> #include <samsung/misc.h> @@ -37,8 +36,6 @@ #include <power/pmic.h> #include <mmc.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SET_DFU_ALT_INFO void set_dfu_alt_info(char *interface, char *devstr) { diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index fe230971e97..d6d1aad75b2 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -1,5 +1,7 @@ if TARGET_CAPRICORN +config HUSH_INIT_VAR + def_bool y config SYS_BOARD default "capricorn" diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 390a7b0d841..ba6c96a409c 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -5,6 +5,7 @@ * Copyright 2019 Siemens AG * */ +#include <cli_hush.h> #include <command.h> #include <dm.h> #include <env.h> @@ -29,6 +30,7 @@ #include "../common/board.h" #include "../common/eeprom.h" #include "../common/factoryset.h" +#include <firmware/imx/sci/sci.h> #define GPIO_PAD_CTRL \ ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ @@ -355,16 +357,6 @@ int board_mmc_get_env_dev(int devno) return devno; } -static int check_mmc_autodetect(void) -{ - char *autodetect_str = env_get("mmcautodetect"); - - if (autodetect_str && (strcmp(autodetect_str, "yes") == 0)) - return 1; - - return 0; -} - /* This should be defined for each board */ __weak int mmc_map_to_kernel_blk(int dev_no) { @@ -373,23 +365,45 @@ __weak int mmc_map_to_kernel_blk(int dev_no) void board_late_mmc_env_init(void) { - char cmd[32]; - char mmcblk[32]; u32 dev_no = mmc_get_env_dev(); - if (!check_mmc_autodetect()) - return; - env_set_ulong("mmcdev", dev_no); +} - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", - mmc_map_to_kernel_blk(dev_no)); - env_set("mmcroot", mmcblk); +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + sc_misc_bt_t boot_type; - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); + if (sc_misc_get_boot_type(-1, &boot_type) != 0) { + puts("boottype cannot be retrieved\n"); + return 0; + } + + /* + * Set here explicitly a hush shell variable, so if a saveenv + * happens, this variable is *not* saved in U-Boot environment. + * + * This is for devices which are already in the field essential, + * as if such a device breaks, the cutsomer gets a new device + * with a new U-Boot version (and so a new U-Boot environment). + * + * But the customer makes a downgrade to an older U-Boot version, + * which does not have this code in, and runs now with a new + * U-Boot Environment (yes, protected Environment is not enabled + * there) and the old U-Boot must still work with the new U-Boot + * Environment. So we cannot store this variable in U-Boot + * Environment as a stored value will in this case never be over- + * written. + */ + if (boot_type == 1) { + printf("boot-container fallback ocured\n"); + set_local_var("fallback=1", 0); + } + + return 0; } +#endif #ifndef CONFIG_XPL_BUILD static int load_parameters_from_factoryset(void) diff --git a/board/siemens/capricorn/capricorn_default.env b/board/siemens/capricorn/capricorn_default.env index c8b5b3d7da3..10d612b04fe 100644 --- a/board/siemens/capricorn/capricorn_default.env +++ b/board/siemens/capricorn/capricorn_default.env @@ -1,17 +1,23 @@ -altbootcmd=run bootcmd +terminate_upgrade=bootcount reset; setenv upgrade_available 0 +altbootcmd=run terminate_upgrade; run toggle_partition baudrate=115200 bootcmd=run flash_self;reset; bootdelay=3 bootdir=targetdir/rootfs/boot bootlimit=3 -check_upgrade=if test ${upgrade_available} -eq 1; then echo upgrade_available is set; if test ${bootcount} -gt ${bootlimit}; then setenv upgrade_available 0;echo toggle partition;run toggle_partition;fi;fi; cntr_addr=0x88000000 cntr_file=os_cntr_signed.bin console=ttyLP2 dtb_name_default=default ethprime=eth1 fdt_addr=0x83000000 -flash_self=run mmc_boot +flash_self=if test -n "$fallback";then + echo "fallback: $fallback"; + run terminate_upgrade; + run toggle_partition; + else + run mmc_boot; + fi flash_self_test=setenv testargs test loglevel=3 systemd.unit=test.target; run mmc_boot hostname=capricorn initrd_addr=0x83100000 @@ -19,30 +25,88 @@ initrd_high=0xffffffffffffffff ip_method=none kernel_name=Image loadaddr=0x80400000 -mmc_boot=run set_bootargs;run check_upgrade; run set_partition;run set_bootargs_mmc;run mmc_load_bootfiles -mmc_boot_fit=ext4load mmc 0:${mmc_part_nr} 0x88000000 boot/fitImage;if test -n ${A};then setenv bootargs ${bootargs} rootfs_sig=${sig_a};fi;if test -n ${B};then setenv bootargs ${bootargs} rootfs_sig=${sig_b};fi;bootm 0x88000000#conf-${dtb_name}.dtb;bootm -mmc_boot_image=ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name}.dtb;if test $? -eq 1;then ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name_default}.dtb;fi; ext4load mmc 0:${mmc_part_nr} ${loadaddr} boot/${kernel_name}; booti ${loadaddr} - ${fdt_addr} -mmc_load_bootfiles=echo -n Loading from eMMC ...; if test -e mmc 0:${mmc_part_nr} boot/fitImage; then echo fit; setenv fdt_high; setenv initrd_high; run mmc_boot_fit; else echo image; run mmc_boot_image; fi -net_nfs=wdt dev scu-wdt; wdt stop; echo Booting from network ...; run set_bootargs_net; tftpboot ${loadaddr} ${bootdir}/${kernel_name}; printenv bootargs; if test ${kernel_name} = fitImage; then setenv fdt_high; setenv initrd_high; bootm ${loadaddr}#conf-${dtb_name}.dtb; else tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name}.dtb; if test $? -eq 1; then echo Loading default.dtb!; tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name_default}.dtb; fi; booti ${loadaddr} - ${fdt_addr}; fi -net_unfs=setenv nfsopts vers=3,udp,rsize=4096,wsize=4096,nolock,port=3049,mountport=3048 rw; run net_nfs -netdev=lan0 +mmc_boot=run set_bootargs; run set_partition;run set_bootargs_mmc;run mmc_load_bootfiles +mmc_boot_fit=ext4load mmc 0:${mmc_part_nr} 0x88000000 boot/fitImage; + if test -n ${A};then + setenv bootargs ${bootargs} rootfs_sig=${sig_a}; + fi; + if test -n ${B};then + setenv bootargs ${bootargs} rootfs_sig=${sig_b}; + fi; + bootm 0x88000000#conf-${dtb_name}.dtb;bootm 0x88000000 +mmc_boot_image=ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name}.dtb; + if test $? -eq 1;then + ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name_default}.dtb; + fi; + ext4load mmc 0:${mmc_part_nr} ${loadaddr} boot/${kernel_name}; + booti ${loadaddr} - ${fdt_addr} +mmc_load_bootfiles=echo -n Loading from eMMC ...; + if test -e mmc 0:${mmc_part_nr} boot/fitImage; then + echo fit; setenv fdt_high; setenv initrd_high; run mmc_boot_fit; + else + echo image; run mmc_boot_image; + fi +net_nfs=wdt dev scu-wdt; wdt stop; echo Booting from network ...; + run set_bootargs_net; tftpboot ${loadaddr} ${bootdir}/${kernel_name}; + printenv bootargs; + if test ${kernel_name} = fitImage; then + setenv fdt_high; setenv initrd_high; + bootm ${loadaddr}#conf-${dtb_name}.dtb; + else + tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name}.dtb; + if test $? -eq 1; then + echo Loading default.dtb!; + tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name_default}.dtb; + fi; + booti ${loadaddr} - ${fdt_addr}; + fi +net_unfs=setenv nfsopts vers=3,udp,rsize=4096,wsize=4096,nolock,port=3049,mountport=3048 rw; + run net_nfs +netdev=eth0 nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw partitionset_active=A rootfs_name=/dev/mmcblk0 rootpath=/home/projects/targetdir/rootfs script_file=u-boot-commands.img -set_bootargs_mmc=setenv bootargs ${bootargs} root=${mmc_active_vol} ro rootdelay=1 rootwait rootfstype=ext4 ip=${ip_method} -set_bootargs_net=run set_bootargs; if test ${kernel_name} = fitImage; then setenv loadaddr 0x88000000; fi; setenv bootargs ${bootargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off -set_bootargs=setenv bootargs console=${console},${baudrate} target_env=${target_env} ${testargs} ${optargs} -set_partition=setenv ${partitionset_active} true;if test -n ${A}; then setenv mmc_part_nr 1;fi;if test -n ${B}; then setenv mmc_part_nr 2;fi;setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} -tftp_run_script=tftpboot ${kernel_loadaddr} ${serverip}:${script_file};if test $? -eq 0;then source ${kernel_loadaddr};fi -toggle_partition=setenv ${partitionset_active} true; if test -n ${A}; then setenv partitionset_active B; mmc partconf 0 1 2 0; env delete A; fi; if test -n ${B}; then setenv partitionset_active A; mmc partconf 0 1 1 0; env delete B; fi;saveenv; reset +set_bootargs_mmc=setenv bootargs ${bootargs} root=${mmc_active_vol} ro rootdelay=1 + rootwait rootfstype=ext4 ip=${ip_method} +set_bootargs_net=run set_bootargs; + if test ${kernel_name} = fitImage; then + setenv loadaddr 0x88000000; + fi; + setenv bootargs ${bootargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off +set_bootargs=setenv bootargs console=${console},${baudrate} target_env=${target_env} ${testargs} + ${optargs} +set_partition=mmc partconf 0 v_mmc_part_nr; setenv mmc_part_nr $v_mmc_part_nr; + setenv mmc_active_vol ${rootfs_name}p$v_mmc_part_nr +tftp_run_script=tftpboot ${kernel_loadaddr} ${serverip}:${script_file}; + if test $? -eq 0;then + source ${kernel_loadaddr}; + fi +toggle_partition=mmc partconf 0 v_mmc_part_nr; + if test $v_mmc_part_nr -eq 1;then + mmc partconf 0 1 2 0; setenv partitionset_active B; + elif test $v_mmc_part_nr -eq 2;then + mmc partconf 0 1 1 0; setenv partitionset_active A; + else + echo error mmc_part_nr $v_mmc_part_nr; + fi; + saveenv;reset upgrade_available=0 emmc_dev=0 sd_dev=1 mfgtool_args=setenv bootargs console=${console},${baudrate} rdinit=/linuxrc clk_ignore_unused kboot=booti -bootcmd_mfg=run mfgtool_args; if iminfo ${initrd_addr}; then if test ${tee} = yes; then bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; else booti ${loadaddr} ${initrd_addr} ${fdt_addr}; fi; else echo "Run fastboot ..."; fastboot usb auto; fi; +bootcmd_mfg=run mfgtool_args; + if iminfo ${initrd_addr}; then + if test ${tee} = yes; then + bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; + else + booti ${loadaddr} ${initrd_addr} ${fdt_addr}; + fi; + else + echo "Run fastboot ..."; fastboot usb auto; + fi; fastboot_bytes=124c00 fastboot_dev=mmc -mmcautodetect=yes diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig index bf4a00d6f7f..36cf756e3f3 100644 --- a/board/sifive/unleashed/Kconfig +++ b/board/sifive/unleashed/Kconfig @@ -35,13 +35,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply CMD_FS_GENERIC imply CMD_GPT - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply CMD_NET imply CMD_PING imply CMD_SF imply DOS_PARTITION imply EFI_PARTITION - imply IP_DYN imply ISO_PARTITION imply PHY_LIB imply PHY_MSCC diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig index 991dd23f1d4..9245873927b 100644 --- a/board/sifive/unmatched/Kconfig +++ b/board/sifive/unmatched/Kconfig @@ -36,13 +36,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply CMD_FS_GENERIC imply CMD_GPT - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply CMD_NET imply CMD_PING imply CMD_SF imply DOS_PARTITION imply EFI_PARTITION - imply IP_DYN imply ISO_PARTITION imply PHY_LIB imply PHY_MSCC diff --git a/board/sifive/unmatched/unmatched.env b/board/sifive/unmatched/unmatched.env index 34425dc9efa..f309229481b 100644 --- a/board/sifive/unmatched/unmatched.env +++ b/board/sifive/unmatched/unmatched.env @@ -16,4 +16,4 @@ partitions= name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1}; name=loader2,size=4MB,type=${type_guid_gpt_loader2}; name=system,size=-,bootable,type=${type_guid_gpt_system}; -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 4b0defda1ec..333b78c27f3 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -14,13 +14,10 @@ #include <env.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/stm32.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 88c825334a8..feba46d38e4 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -8,13 +8,10 @@ #include <env.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/stm32.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 7aab7f71d0c..d153efdc2b4 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -8,13 +8,10 @@ #include <env.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/stm32.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 07bc8a5f0a2..4b1e443100d 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -15,7 +15,6 @@ #include <spl.h> #include <splash.h> #include <video.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> @@ -23,8 +22,6 @@ #include <asm/gpio.h> #include <linux/delay.h> -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { #ifndef CONFIG_XPL_BUILD diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index d00f55379c5..6c5c6710926 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -7,9 +7,6 @@ #include <dm.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index d00f55379c5..6c5c6710926 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -7,9 +7,6 @@ #include <dm.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c index 645685a64f1..24a229bf0a2 100644 --- a/board/st/stm32h747-disco/stm32h747-disco.c +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -8,9 +8,6 @@ #include <dm.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 31c85c6816e..244bb5eefb3 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -7,9 +7,6 @@ #include <dm.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig index 2186a939646..b4bf59676ac 100644 --- a/board/starfive/visionfive2/Kconfig +++ b/board/starfive/visionfive2/Kconfig @@ -44,9 +44,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply DOS_PARTITION imply EFI_PARTITION imply MII - imply IP_DYN imply ISO_PARTITION - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply PHY_LIB imply PHY_MSCC diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 2d9431d2976..e231467f2a1 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -131,6 +131,9 @@ int board_fit_config_name_match(const char *name) !strncmp(get_product_id_from_eeprom(), "MARC", 4) && !get_mmc_size_from_eeprom()) { return 0; + } else if (!strcmp(name, "starfive/jh7110-orangepi-rv") && + !strncmp(get_product_id_from_eeprom(), "XOPIRV", 6)) { + return 0; } else if (!strcmp(name, "starfive/jh7110-pine64-star64") && !strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { return 0; @@ -140,6 +143,9 @@ int board_fit_config_name_match(const char *name) } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") && !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { return 0; + } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-lite") && + !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { + return 0; } return -EINVAL; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 6c39fd4af35..1a76f745ec8 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -63,12 +63,16 @@ static void set_fdtfile(void) } else { fdtfile = "starfive/jh7110-milkv-marscm-lite.dtb"; } + } else if (!strncmp(get_product_id_from_eeprom(), "XOPIRV", 6)) { + fdtfile = "starfive/jh7110-orangepi-rv.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { fdtfile = "starfive/jh7110-pine64-star64.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) { fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; + } else if (!strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-lite.dtb"; } else { log_err("Unknown product\n"); return; diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index 17a44020bcf..b9197cdd34f 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -105,7 +105,8 @@ struct eeprom_atom4_data { u8 bom_revision; /* BOM version */ u8 mac0_addr[MAC_ADDR_BYTES]; /* Ethernet0 MAC */ u8 mac1_addr[MAC_ADDR_BYTES]; /* Ethernet1 MAC */ - u8 reserved[2]; + u8 onboard_module; /* Onboard module flag: bit7-1: reserved, bit0: WIFI/BT */ + u8 reserved; }; struct starfive_eeprom_atom4 { @@ -176,7 +177,7 @@ static void show_eeprom(void) printf("Vendor : %s\n", pbuf.eeprom.atom1.data.vstr); printf("Product full SN: %s\n", pbuf.eeprom.atom1.data.pstr); printf("data version: 0x%x\n", pbuf.eeprom.atom4.data.version); - if (pbuf.eeprom.atom4.data.version == 2) { + if (pbuf.eeprom.atom4.data.version == 2 || pbuf.eeprom.atom4.data.version == 3) { printf("PCB revision: 0x%x\n", pbuf.eeprom.atom4.data.pcb_revision); printf("BOM revision: %c\n", pbuf.eeprom.atom4.data.bom_revision); printf("Ethernet MAC0 address: %02x:%02x:%02x:%02x:%02x:%02x\n", @@ -187,6 +188,14 @@ static void show_eeprom(void) pbuf.eeprom.atom4.data.mac1_addr[0], pbuf.eeprom.atom4.data.mac1_addr[1], pbuf.eeprom.atom4.data.mac1_addr[2], pbuf.eeprom.atom4.data.mac1_addr[3], pbuf.eeprom.atom4.data.mac1_addr[4], pbuf.eeprom.atom4.data.mac1_addr[5]); + if (pbuf.eeprom.atom4.data.version == 3) { + char str[25] = "Onboard module: "; + + if (pbuf.eeprom.atom4.data.onboard_module & BIT(0)) + strcat(str, "WIFI/BT"); + + printf("%s\n", str); + } } else { printf("Custom data v%d is not Supported\n", pbuf.eeprom.atom4.data.version); dump_raw_eeprom(); @@ -260,6 +269,7 @@ static void init_local_copy(void) pbuf.eeprom.atom4.data.bom_revision = BOM_VERSION; set_mac_address(STARFIVE_DEFAULT_MAC0, 0); set_mac_address(STARFIVE_DEFAULT_MAC1, 1); + pbuf.eeprom.atom4.data.onboard_module = 0; } /** @@ -386,6 +396,23 @@ static void set_bom_revision(char *string) } /** + * set_onboard_module() - stores a StarFive onboard module flag into the local EEPROM copy + * + * Takes a pointer to a string representing the numeric onboard module flag in + * Hexadecimal ("0" - "FF"), stores it in the onboard_module field of the + * EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_onboard_module(char *string) +{ + u8 onboard_module; + + onboard_module = simple_strtoul(string, &string, 16); + pbuf.eeprom.atom4.data.onboard_module = onboard_module; + + update_crc(); +} + +/** * set_product_id() - stores a StarFive product ID into the local EEPROM copy * * Takes a pointer to a string representing the numeric product ID in @@ -478,6 +505,9 @@ int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } else if (!strcmp(cmd, "bom_revision")) { set_bom_revision(argv[2]); return 0; + } else if (!strcmp(cmd, "onboard_module")) { + set_onboard_module(argv[2]); + return 0; } else if (!strcmp(cmd, "product_id")) { set_product_id(argv[2]); return 0; @@ -535,38 +565,20 @@ int mac_read_from_eeprom(void) return 0; } -/** - * get_pcb_revision_from_eeprom - get the PCB revision - * - * 1.2A return 'A'/'a', 1.3B return 'B'/'b',other values are illegal - */ u8 get_pcb_revision_from_eeprom(void) { - u8 pv = 0xFF; - if (read_eeprom()) - return pv; + return 0; - return pbuf.eeprom.atom1.data.pstr[6]; + return pbuf.eeprom.atom4.data.pcb_revision; } -/** - * get_ddr_size_from_eeprom - get the DDR size - * pstr: VF7110A1-2228-D008E000-00000001 - * VF7110A1/VF7110B1 : VisionFive JH7110A /VisionFive JH7110B - * D008: 8GB LPDDR4 - * E000: No emmc device, ECxx: include emmc device, xx: Capacity size[GB] - * return: the field of 'D008E000' - */ - -u32 get_ddr_size_from_eeprom(void) +u8 get_ddr_size_from_eeprom(void) { - u32 pv = 0xFFFFFFFF; - if (read_eeprom()) - return pv; + return 0; - return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL); + return (hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL) >> 16) & 0xFF; } u32 get_mmc_size_from_eeprom(void) @@ -603,6 +615,8 @@ U_BOOT_LONGHELP(mac, " - stores a StarFive PCB revision into the local EEPROM copy\n" "mac bom_revision <A>\n" " - stores a StarFive BOM revision into the local EEPROM copy\n" + "mac onboard_module <?>\n" + " - stores a StarFive onboard module flag into the local EEPROM copy\n" "mac product_id <VF7110A1-2228-D008E000-xxxxxxxx>\n" " - stores a StarFive product ID into the local EEPROM copy\n" "mac vendor <Vendor Name>\n" diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 954a8715075..d7722d1858a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -50,7 +50,6 @@ #include <spl.h> #include <sy8106a.h> #include <asm/setup.h> -#include <status_led.h> DECLARE_GLOBAL_DATA_PTR; @@ -561,14 +560,23 @@ static void sunxi_spl_store_dram_size(phys_addr_t dram_size) spl->dram_size = dram_size >> 20; } +static void status_led_init(void) +{ +#if CONFIG_IS_ENABLED(SUNXI_LED_STATUS) + unsigned int state = CONFIG_SPL_SUNXI_LED_STATUS_STATE; + unsigned int gpio = CONFIG_SPL_SUNXI_LED_STATUS_BIT; + + gpio_request(gpio, "gpio_led"); + gpio_direction_output(gpio, state); +#endif +} + void sunxi_board_init(void) { int power_failed = 0; -#ifdef CONFIG_LED_STATUS - if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC)) + if (CONFIG_IS_ENABLED(SUNXI_LED_STATUS)) status_led_init(); -#endif #ifdef CONFIG_SY8106A_POWER power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 1659db112fa..5515fc09f99 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -7,7 +7,6 @@ #include <init.h> #include <malloc.h> #include <errno.h> -#include <asm/global_data.h> #include <asm/io.h> #include <miiphy.h> #include <netdev.h> @@ -24,8 +23,6 @@ #include <spl.h> #include <power/pmic.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index cbd087de797..4e238883b96 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62A # @@ -16,14 +16,14 @@ rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - # 1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - # 2 + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 1038 - num_resource: 497 + num_resource: 496 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62ax/tifs-rm-cfg.yaml b/board/ti/am62ax/tifs-rm-cfg.yaml index 151cd599b1b..78bbab38bb6 100644 --- a/board/ti/am62ax/tifs-rm-cfg.yaml +++ b/board/ti/am62ax/tifs-rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62AX +# Resource management configuration for AM62A # --- @@ -24,26 +24,26 @@ tifs-rm-cfg: allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - # 2 - host_id: 30 + host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - # 3 - host_id: 36 + host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - # 4 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - # 5 host_id: 0 allowed_atype: 0 @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 872 + resasg_entries_size: 880 reserved: 0 resasg_entries: - @@ -257,7 +257,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1677 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 18 @@ -287,7 +287,7 @@ tifs-rm-cfg: start_resource: 72 num_resource: 6 type: 1678 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 72 @@ -317,7 +317,7 @@ tifs-rm-cfg: start_resource: 44 num_resource: 6 type: 1679 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 44 @@ -347,7 +347,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1696 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 18 @@ -377,7 +377,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1697 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 18 @@ -407,7 +407,7 @@ tifs-rm-cfg: start_resource: 12 num_resource: 6 type: 1698 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 12 @@ -429,19 +429,25 @@ tifs-rm-cfg: reserved: 0 - start_resource: 6 - num_resource: 34 + num_resource: 26 type: 1802 host_id: 12 reserved: 0 - + start_resource: 32 + num_resource: 8 + type: 1802 + host_id: 20 + reserved: 0 + - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml index 73da85eeade..0db82fdaf79 100644 --- a/board/ti/am62px/rm-cfg.yaml +++ b/board/ti/am62px/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62px/tifs-rm-cfg.yaml b/board/ti/am62px/tifs-rm-cfg.yaml index 80269748057..73efceafc75 100644 --- a/board/ti/am62px/tifs-rm-cfg.yaml +++ b/board/ti/am62px/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -9,231 +9,231 @@ tifs-rm-cfg: rm_boardcfg: rev: - boardcfg_abi_maj : 0x0 - boardcfg_abi_min : 0x1 + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 host_cfg: subhdr: magic: 0x4C41 - size : 356 + size: 356 host_cfg_entries: - - #1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #2 + - # 2 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #3 + - # 3 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #4 + - # 4 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #5 + - # 5 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #6 + - # 6 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #7 + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #8 + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #9 + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #10 + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #11 + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #12 + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #13 + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #14 + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #15 + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #16 + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #17 + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #18 + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #19 + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #20 + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #21 + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #22 + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #23 + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #24 + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #25 + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #26 + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #27 + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #28 + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #29 + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #30 + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #31 + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #32 + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 @@ -244,684 +244,732 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 904 + resasg_entries_size: 968 reserved: 0 resasg_entries: - - start_resource: 0 - num_resource: 18 - type: 1677 - host_id: 12 - reserved: 0 - - - start_resource: 18 - num_resource: 6 - type: 1677 - host_id: 35 - reserved: 0 - - - start_resource: 18 - num_resource: 6 - type: 1677 - host_id: 36 - reserved: 0 - - - start_resource: 24 - num_resource: 2 - type: 1677 - host_id: 30 - reserved: 0 - - - start_resource: 26 - num_resource: 6 - type: 1677 - host_id: 128 - reserved: 0 - - - start_resource: 57 - num_resource: 18 - type: 1678 - host_id: 12 - reserved: 0 - - - start_resource: 75 - num_resource: 5 - type: 1678 - host_id: 35 - reserved: 0 - - - start_resource: 75 - num_resource: 5 - type: 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18 - type: 1697 - host_id: 12 - reserved: 0 - - - start_resource: 18 - num_resource: 5 - type: 1697 - host_id: 35 - reserved: 0 - - - start_resource: 18 - num_resource: 5 - type: 1697 - host_id: 36 - reserved: 0 - - - start_resource: 23 - num_resource: 2 - type: 1697 - host_id: 30 - reserved: 0 - - - start_resource: 0 - num_resource: 12 - type: 1698 - host_id: 12 - reserved: 0 - - - start_resource: 12 - num_resource: 6 - type: 1698 - host_id: 35 - reserved: 0 - - - start_resource: 12 - num_resource: 6 - type: 1698 - host_id: 36 - reserved: 0 - - - start_resource: 18 - num_resource: 2 - type: 1698 - host_id: 30 - reserved: 0 - - - start_resource: 20 - num_resource: 5 - type: 1698 - host_id: 128 - reserved: 0 - - - start_resource: 5 - num_resource: 35 - type: 1802 - host_id: 12 - reserved: 0 - - - start_resource: 44 - num_resource: 35 - type: 1802 - host_id: 35 - reserved: 0 - - - start_resource: 44 - num_resource: 35 - type: 1802 - host_id: 36 - reserved: 0 - - - start_resource: 168 - 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host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 2e8336900d1..49e58ad6d6c 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -32,8 +32,6 @@ #define board_is_am62x_lp_skevm() board_ti_k3_is("AM62-LP-SKEVM") #define board_is_am62x_sip_skevm() board_ti_k3_is("AM62SIP-SKEVM") -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(SPLASH_SCREEN) static struct splash_location default_splash_locations[] = { { diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index 26d99b03b80..a7035dc0bd9 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62X # @@ -525,7 +525,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62x/tifs-rm-cfg.yaml b/board/ti/am62x/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..8510fe9526e --- /dev/null +++ b/board/ti/am62x/tifs-rm-cfg.yaml @@ -0,0 +1,867 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62X +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + 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reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index c6ddc44d14c..05c5ca8740f 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -27,8 +27,6 @@ #define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \ board_ti_k3_is("AM64B-SKEVM")) -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID, diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 409454813f3..149909093b3 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -61,4 +61,6 @@ config TI_COMMON_CMD_OPTIONS imply CMD_SPL imply CMD_TIME imply CMD_USB if USB + imply CMD_TPM if TPM + imply CMD_OPTEE_RPMB if OPTEE && SUPPORT_EMMC_RPMB diff --git a/board/ti/common/k3_bist.config b/board/ti/common/k3_bist.config new file mode 100644 index 00000000000..671dda1a9dc --- /dev/null +++ b/board/ti/common/k3_bist.config @@ -0,0 +1 @@ +CONFIG_K3_BIST=y diff --git a/board/ti/common/k3_inline_ecc.config b/board/ti/common/k3_inline_ecc.config new file mode 100644 index 00000000000..143c814b41c --- /dev/null +++ b/board/ti/common/k3_inline_ecc.config @@ -0,0 +1 @@ +CONFIG_K3_INLINE_ECC=y diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index e22a954d8db..7bb63825c52 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -37,3 +37,11 @@ main_cpsw0_qsgmii_phyinit= #if CONFIG_TARGET_J7200_A72_EVM rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif + +#if CONFIG_CMD_REMOTEPROC +board_init= + if env exists do_main_cpsw0_qsgmii_phyinit; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; +#endif diff --git a/board/ti/j7200/rm-cfg.yaml b/board/ti/j7200/rm-cfg.yaml index 9da0ea91ada..e1973de821f 100644 --- a/board/ti/j7200/rm-cfg.yaml +++ b/board/ti/j7200/rm-cfg.yaml @@ -399,7 +399,7 @@ rm-cfg: reserved: 0 - start_resource: 224 - num_resource: 32 + num_resource: 30 type: 13386 host_id: 128 reserved: 0 @@ -441,7 +441,7 @@ rm-cfg: reserved: 0 - start_resource: 2578 - num_resource: 2030 + num_resource: 2028 type: 13389 host_id: 128 reserved: 0 @@ -1041,12 +1041,12 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 128 + num_resource: 126 type: 13632 host_id: 12 reserved: 0 - - start_resource: 138 + start_resource: 136 num_resource: 54 type: 13632 host_id: 13 diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 34f5f63d60a..9ecf7bfabde 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -37,3 +37,11 @@ main_cpsw0_qsgmii_phyinit= #if CONFIG_TARGET_J721E_A72_EVM rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif + +#if CONFIG_CMD_REMOTEPROC +board_init= + if env exists do_main_cpsw0_qsgmii_phyinit; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; +#endif diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml index 88ec2026db0..86d30a96375 100644 --- a/board/ti/j721e/rm-cfg.yaml +++ b/board/ti/j721e/rm-cfg.yaml @@ -495,7 +495,7 @@ rm-cfg: reserved: 0 - start_resource: 252 - num_resource: 4 + num_resource: 2 type: 13386 host_id: 128 reserved: 0 @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 3686 - num_resource: 922 + num_resource: 920 type: 13389 host_id: 128 reserved: 0 @@ -1635,18 +1635,18 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 100 + num_resource: 98 type: 13632 host_id: 12 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 32 type: 13632 host_id: 13 reserved: 0 - - start_resource: 142 + start_resource: 140 num_resource: 46 type: 13632 host_id: 21 diff --git a/board/ti/j721s2/rm-cfg.yaml b/board/ti/j721s2/rm-cfg.yaml index 8796463129d..86d572b4b33 100644 --- a/board/ti/j721s2/rm-cfg.yaml +++ b/board/ti/j721s2/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721S2 # @@ -429,24 +429,24 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 100 + num_resource: 98 type: 14528 host_id: 12 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 32 type: 14528 host_id: 13 reserved: 0 - - start_resource: 142 + start_resource: 140 num_resource: 21 type: 14528 host_id: 21 reserved: 0 - - start_resource: 163 + start_resource: 161 num_resource: 21 type: 14528 host_id: 23 @@ -1431,7 +1431,7 @@ rm-cfg: reserved: 0 - start_resource: 236 - num_resource: 20 + num_resource: 18 type: 16970 host_id: 128 reserved: 0 @@ -1497,7 +1497,7 @@ rm-cfg: reserved: 0 - start_resource: 3426 - num_resource: 1182 + num_resource: 1180 type: 16973 host_id: 128 reserved: 0 diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index 62730adf216..e5f7b24c1d1 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -591,7 +591,7 @@ rm-cfg: reserved: 0 - start_resource: 1297 - num_resource: 239 + num_resource: 238 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index cabb3017ee1..8a4d40a5a95 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -14,8 +14,6 @@ #include <asm/arch/k3-ddr.h> #include "../common/fdt_ops.h" -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = AM69_SK_TIBOOT3_IMAGE_GUID, diff --git a/board/ti/j784s4/rm-cfg.yaml b/board/ti/j784s4/rm-cfg.yaml index 6968d317522..6fb717e4808 100644 --- a/board/ti/j784s4/rm-cfg.yaml +++ b/board/ti/j784s4/rm-cfg.yaml @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J784S4 # @@ -454,36 +454,36 @@ rm-cfg: reserved: 0 - start_resource: 16 - num_resource: 80 + num_resource: 78 type: 18112 host_id: 12 reserved: 0 - - start_resource: 96 + start_resource: 94 num_resource: 14 type: 18112 host_id: 13 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 21 type: 18112 host_id: 21 reserved: 0 - - start_resource: 131 + start_resource: 129 num_resource: 21 type: 18112 host_id: 23 reserved: 0 - - start_resource: 152 + start_resource: 150 num_resource: 12 type: 18112 host_id: 25 reserved: 0 - - start_resource: 164 + start_resource: 162 num_resource: 12 type: 18112 host_id: 27 @@ -1720,72 +1720,72 @@ rm-cfg: reserved: 0 - start_resource: 56 - num_resource: 56 + num_resource: 54 type: 20554 host_id: 12 reserved: 0 - - start_resource: 112 + start_resource: 110 num_resource: 24 type: 20554 host_id: 13 reserved: 0 - - start_resource: 136 + start_resource: 134 num_resource: 12 type: 20554 host_id: 21 reserved: 0 - - start_resource: 148 + start_resource: 146 num_resource: 12 type: 20554 host_id: 23 reserved: 0 - - start_resource: 160 + start_resource: 158 num_resource: 10 type: 20554 host_id: 25 reserved: 0 - - start_resource: 170 + start_resource: 168 num_resource: 10 type: 20554 host_id: 27 reserved: 0 - - start_resource: 180 + start_resource: 178 num_resource: 28 type: 20554 host_id: 35 reserved: 0 - - start_resource: 208 + start_resource: 206 num_resource: 8 type: 20554 host_id: 37 reserved: 0 - - start_resource: 216 + start_resource: 214 num_resource: 12 type: 20554 host_id: 40 reserved: 0 - - start_resource: 228 + start_resource: 226 num_resource: 8 type: 20554 host_id: 42 reserved: 0 - - start_resource: 236 + start_resource: 234 num_resource: 10 type: 20554 host_id: 45 reserved: 0 - - start_resource: 246 + start_resource: 244 num_resource: 10 type: 20554 host_id: 47 @@ -1876,7 +1876,7 @@ rm-cfg: reserved: 0 - start_resource: 4472 - num_resource: 136 + num_resource: 134 type: 20557 host_id: 128 reserved: 0 diff --git a/board/ti/j784s4/tifs-rm-cfg.yaml b/board/ti/j784s4/tifs-rm-cfg.yaml index 992ea23155a..738fe0ea07d 100644 --- a/board/ti/j784s4/tifs-rm-cfg.yaml +++ b/board/ti/j784s4/tifs-rm-cfg.yaml @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J784S4 # @@ -1456,72 +1456,72 @@ tifs-rm-cfg: reserved: 0 - start_resource: 56 - num_resource: 56 + num_resource: 54 type: 20554 host_id: 12 reserved: 0 - - start_resource: 112 + start_resource: 110 num_resource: 24 type: 20554 host_id: 13 reserved: 0 - - start_resource: 136 + start_resource: 134 num_resource: 12 type: 20554 host_id: 21 reserved: 0 - - start_resource: 148 + start_resource: 146 num_resource: 12 type: 20554 host_id: 23 reserved: 0 - - start_resource: 160 + start_resource: 158 num_resource: 10 type: 20554 host_id: 25 reserved: 0 - - start_resource: 170 + start_resource: 168 num_resource: 10 type: 20554 host_id: 27 reserved: 0 - - start_resource: 180 + start_resource: 178 num_resource: 28 type: 20554 host_id: 35 reserved: 0 - - start_resource: 208 + start_resource: 206 num_resource: 8 type: 20554 host_id: 37 reserved: 0 - - start_resource: 216 + start_resource: 214 num_resource: 12 type: 20554 host_id: 40 reserved: 0 - - start_resource: 228 + start_resource: 226 num_resource: 8 type: 20554 host_id: 42 reserved: 0 - - start_resource: 236 + start_resource: 234 num_resource: 10 type: 20554 host_id: 45 reserved: 0 - - start_resource: 246 + start_resource: 244 num_resource: 10 type: 20554 host_id: 47 diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index a8c38208693..b915673d9e3 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -5,7 +5,6 @@ #include <cpu_func.h> #include <init.h> -#include <asm/global_data.h> #include <asm/arch/clock.h> #include <asm/arch/imx8-pins.h> @@ -24,8 +23,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 2c785da41ea..8dad41f4122 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -11,7 +11,6 @@ #include <asm/arch/pinmux.h> #include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> #include <dm.h> @@ -23,8 +22,6 @@ #include "pinmux-config-apalis_t30.h" -DECLARE_GLOBAL_DATA_PTR; - #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 diff --git a/board/toradex/aquila-am69/Makefile b/board/toradex/aquila-am69/Makefile index aa71c4bbb21..aa657ac8a42 100644 --- a/board/toradex/aquila-am69/Makefile +++ b/board/toradex/aquila-am69/Makefile @@ -6,4 +6,5 @@ obj-y += aquila-am69.o obj-y += ddrs_patch.o obj-y += aquila_ddrs_16GB.o +obj-y += aquila_ddrs_16GB_rank_2.o obj-y += aquila_ddrs_8GB.o diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c index e0975d5bc6f..0c7123a059e 100644 --- a/board/toradex/aquila-am69/aquila-am69.c +++ b/board/toradex/aquila-am69/aquila-am69.c @@ -17,26 +17,32 @@ #include <spl.h> #include "../common/tdx-common.h" -#include "aquila_ddrs_16GB.h" -#include "aquila_ddrs_8GB.h" +#include "aquila_ddrs.h" #include "ddrs_patch.h" #define CTRL_MMR_CFG0_MCU_ADC1_CTRL 0x40F040B4 #define HW_CFG_MEM_SZ_32GB 0x00 -#define HW_CFG_MEM_SZ_16GB 0x01 +#define HW_CFG_MEM_SZ_16GB_RANK_2 0x01 #define HW_CFG_MEM_SZ_8GB 0x02 +#define HW_CFG_MEM_SZ_16GB 0x03 -#define HW_CFG_MEM_SZ_MASK 0x03 +#define HW_CFG_MEM_CFG_MASK 0x03 DECLARE_GLOBAL_DATA_PTR; static u8 hw_cfg; +static u8 aquila_am69_memory_cfg(void) +{ + return hw_cfg & HW_CFG_MEM_CFG_MASK; +} + static u64 aquila_am69_memory_size(void) { - switch (hw_cfg & HW_CFG_MEM_SZ_MASK) { + switch (aquila_am69_memory_cfg()) { case HW_CFG_MEM_SZ_32GB: return SZ_32G; + case HW_CFG_MEM_SZ_16GB_RANK_2: case HW_CFG_MEM_SZ_16GB: return SZ_16G; case HW_CFG_MEM_SZ_8GB: @@ -79,12 +85,16 @@ static void update_ddr_timings(void) int ret = 0; void *fdt = (void *)gd->fdt_blob; - switch (aquila_am69_memory_size()) { - case SZ_8G: + switch (aquila_am69_memory_cfg()) { + case HW_CFG_MEM_SZ_8GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB, MULTI_DDR_CFG_INTRLV_SIZE_8GB); break; - case SZ_16G: + case HW_CFG_MEM_SZ_16GB_RANK_2: + ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB_rank_2, + MULTI_DDR_CFG_INTRLV_SIZE_16GB); + break; + case HW_CFG_MEM_SZ_16GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB, MULTI_DDR_CFG_INTRLV_SIZE_16GB); break; diff --git a/board/toradex/aquila-am69/aquila_ddrs.h b/board/toradex/aquila-am69/aquila_ddrs.h new file mode 100644 index 00000000000..7a58be3fd29 --- /dev/null +++ b/board/toradex/aquila-am69/aquila_ddrs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) Toradex - https://www.toradex.com/ + */ +#ifndef __AQUILA_DDRS_H +#define __AQUILA_DDRS_H + +#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9 +#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11 + +extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4]; +extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4]; +extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4]; + +#endif // __AQUILA_DDRS_H diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB.h b/board/toradex/aquila-am69/aquila_ddrs_16GB.h deleted file mode 100644 index 0740c0ef25c..00000000000 --- a/board/toradex/aquila-am69/aquila_ddrs_16GB.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2025 Toradex - https://www.toradex.com/ - */ -#ifndef __AQUILA_DDRS_16GB_H -#define __AQUILA_DDRS_16GB_H - -#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11 -extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4]; - -#endif // __AQUILA_DDRS_16GB_H diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c new file mode 100644 index 00000000000..c24e22b620b --- /dev/null +++ b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) Toradex - https://www.toradex.com/ + * This contains a diff against the 32GB register settings created from + * the 16GB dual rank tool output. + + * The 16GB dtsi file was generated with the following tool revisions: + * - SysConfig: Revision 1.26.2+4477 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Fri Mar 06 2026 10:39:50 GMT+0100 (Central European Standard Time) + */ + +#include <asm/u-boot.h> +#include <linux/kernel.h> +#include "ddrs_patch.h" + +#define DDRSS_PLL_FHS_CNT 3 + +#define DDRSS_CTL_268_DATA 0x01010000 +#define DDRSS_CTL_270_DATA 0x00000FFF +#define DDRSS_CTL_271_DATA 0x1FFF1000 +#define DDRSS_CTL_272_DATA 0x01FF0000 +#define DDRSS_CTL_273_DATA 0x000101FF + +#define DDRSS_PI_73_DATA 0x00080100 + +static struct ddr_reg_patch ctl_patch[] = { + { 268, DDRSS_CTL_268_DATA}, + { 270, DDRSS_CTL_270_DATA}, + { 271, DDRSS_CTL_271_DATA}, + { 272, DDRSS_CTL_272_DATA}, + { 273, DDRSS_CTL_273_DATA} +}; + +static struct ddr_reg_patch pi_patch[] = { + { 73, DDRSS_PI_73_DATA}, +}; + +static struct ddrss_patch ddrss_ctrl_patch = { + .ddr_fhs_cnt = DDRSS_PLL_FHS_CNT, + .ctl_patch = ctl_patch, + .ctl_patch_num = ARRAY_SIZE(ctl_patch), + .pi_patch = pi_patch, + .pi_patch_num = ARRAY_SIZE(pi_patch), + .phy_patch = NULL, + .phy_patch_num = 0 +}; + +struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4] = { + &ddrss_ctrl_patch, + &ddrss_ctrl_patch, + &ddrss_ctrl_patch, + &ddrss_ctrl_patch +}; diff --git a/board/toradex/aquila-am69/aquila_ddrs_8GB.h b/board/toradex/aquila-am69/aquila_ddrs_8GB.h deleted file mode 100644 index c82f236d55f..00000000000 --- a/board/toradex/aquila-am69/aquila_ddrs_8GB.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2025 Toradex - https://www.toradex.com/ - */ -#ifndef __AQUILA_DDRS_8GB_H -#define __AQUILA_DDRS_8GB_H - -#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9 -extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4]; - -#endif // __AQUILA_DDRS_8GB_H diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 2a71e7b92de..0a86420700d 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -5,7 +5,6 @@ #include <cpu_func.h> #include <init.h> -#include <asm/global_data.h> #include <asm/arch/clock.h> #include <asm/arch/imx8-pins.h> @@ -21,8 +20,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 05c3377a60b..ccfe2c4933c 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -13,7 +13,6 @@ #include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/tegra.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> #include <i2c.h> @@ -21,8 +20,6 @@ #include <linux/delay.h> #include "../common/tdx-common.h" -DECLARE_GLOBAL_DATA_PTR; - #define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 #define PMU_SUPPLYENE 0x14 diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 0fc3759695f..8c0278db0e2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <asm/global_data.h> #include "tdx-cfg-block.h" #include "tdx-eeprom.h" @@ -22,8 +21,6 @@ #include <nand.h> #include <asm/mach-types.h> -DECLARE_GLOBAL_DATA_PTR; - #define TAG_VALID 0xcf01 #define TAG_MAC 0x0000 #define TAG_CAR_SERIAL 0x0021 @@ -189,6 +186,7 @@ const struct toradex_som toradex_modules[] = { { OSM_IMX93D_2GB_IT, "OSM iMX93 Dual 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX93) }, { OSM_IMX91S_2GB_IT, "OSM iMX91 Solo 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX91) }, { VERDIN_AM62D_1G_ET_GPU_NODSI, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { AQUILA_TDA4O_16GB_IT, "Aquila TDA4 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index b28033d8332..3022ef615ad 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -6,6 +6,8 @@ #ifndef _TDX_CFG_BLOCK_H #define _TDX_CFG_BLOCK_H +#include <linux/types.h> + #include "tdx-common.h" struct toradex_hw { @@ -147,6 +149,7 @@ enum { OSM_IMX93D_2GB_IT, OSM_IMX91S_2GB_IT, /* 220 */ VERDIN_AM62D_1G_ET_GPU_NODSI, + AQUILA_TDA4O_16GB_IT = 223, }; enum { diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index d446e9f1d5c..db3369a8f9e 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -6,6 +6,8 @@ #ifndef _TDX_COMMON_H #define _TDX_COMMON_H +#include <asm-generic/u-boot.h> + #define TORADEX_USB_PRODUCT_NUM_OFFSET 0x4000 #define TDX_USB_VID 0x1B67 diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c index 915b413b15e..38fb3d61f5b 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.c +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c @@ -2,14 +2,11 @@ /* Copyright (C) 2024 Toradex */ #include <init.h> -#include <asm/global_data.h> #include <asm-generic/gpio.h> #include <linux/errno.h> #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - int board_phys_sdram_size(phys_size_t *size) { if (!size) diff --git a/board/toradex/smarc-imx8mp/spl.c b/board/toradex/smarc-imx8mp/spl.c index 32233c0e1ab..511f62e871b 100644 --- a/board/toradex/smarc-imx8mp/spl.c +++ b/board/toradex/smarc-imx8mp/spl.c @@ -8,7 +8,6 @@ #include <asm/arch/clock.h> #include <asm/arch/ddr.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <dm/device.h> #include <power/pmic.h> @@ -16,8 +15,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/toradex/smarc-imx95/MAINTAINERS b/board/toradex/smarc-imx95/MAINTAINERS index 73517d36f1f..96d349c06b2 100644 --- a/board/toradex/smarc-imx95/MAINTAINERS +++ b/board/toradex/smarc-imx95/MAINTAINERS @@ -1,6 +1,4 @@ Toradex SMARC iMX95 -F: arch/arm/dts/imx95-toradex-smarc.dtsi -F: arch/arm/dts/imx95-toradex-smarc-dev.dts F: arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi F: board/toradex/smarc-imx95/ F: configs/toradex-smarc-imx95_defconfig diff --git a/board/toradex/verdin-am62/rm-cfg.yaml b/board/toradex/verdin-am62/rm-cfg.yaml index ea5f2423cf3..8204031449e 100644 --- a/board/toradex/verdin-am62/rm-cfg.yaml +++ b/board/toradex/verdin-am62/rm-cfg.yaml @@ -525,7 +525,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/toradex/verdin-am62p/rm-cfg.yaml b/board/toradex/verdin-am62p/rm-cfg.yaml index 73da85eeade..bbbb208eb33 100644 --- a/board/toradex/verdin-am62p/rm-cfg.yaml +++ b/board/toradex/verdin-am62p/rm-cfg.yaml @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 3c2d0ba1dd4..10b9991e3bf 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -11,7 +11,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mm_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> @@ -27,8 +26,6 @@ #include <power/pmic.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - #define I2C_PMIC_BUS_ID 1 int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index b4402415845..b56f5bf30a8 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -7,7 +7,6 @@ #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <hang.h> #include <i2c.h> @@ -17,8 +16,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define I2C_PMIC 0 enum pcb_rev_t { diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 8628112a782..44678a976ca 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -7,14 +7,9 @@ #include <init.h> #include <log.h> #include <spl.h> -#include <asm/global_data.h> #include <asm/arch/clock.h> -#include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/arch/ddr.h> #include <dm/device.h> #include <dm/uclass.h> @@ -22,8 +17,6 @@ #include <power/pca9450.h> #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -71,36 +64,21 @@ void spl_board_init(void) puts("Normal Boot\n"); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed\n"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* * increase VDD_SOC to typical value 0.95V before first @@ -110,23 +88,22 @@ int power_init_board(void) */ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) /* set DVS0 to 0.85v for special case */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c); - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Kernel uses OD/OD freq for SoC */ /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); /* set LDO4 and CONFIG2 to enable the I2C level translator */ - pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59); - pmic_reg_write(p, PCA9450_CONFIG2, 0x1); + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); return 0; } -#endif #if IS_ENABLED(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) @@ -159,9 +136,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - /* Adjust PMIC voltage to 1.0V for 800 MHz */ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - /* PMIC initialization */ power_init_board(); diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 34ce25512e8..59b4607f065 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -8,7 +8,6 @@ #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm-generic/gpio.h> -#include <asm/global_data.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <errno.h> @@ -21,8 +20,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) /* Verdin UART_3, Console/Debug UART */ diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS new file mode 100644 index 00000000000..e6f3dc4da21 --- /dev/null +++ b/board/tq/MAINTAINERS @@ -0,0 +1,8 @@ +TQMA6 +M: Max Merchel <[email protected]> +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: arch/arm/dts/*mba6*.dts* +F: arch/arm/dts/*tqma6*.dts* +F: configs/tqma6*config diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig new file mode 100644 index 00000000000..a1896929ea3 --- /dev/null +++ b/board/tq/common/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Max Merchel +# + +config TQ_COMMON_BB + bool + default y + +config TQ_COMMON_SDMMC + bool diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile new file mode 100644 index 00000000000..ac564a713fd --- /dev/null +++ b/board/tq/common/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel +# + +obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o +obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o diff --git a/board/tq/common/tq_bb.c b/board/tq/common/tq_bb.c new file mode 100644 index 00000000000..40cff6ab178 --- /dev/null +++ b/board/tq/common/tq_bb.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include <linux/types.h> + +#include "tq_bb.h" + +int __weak tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + return 0; +} + +int __weak tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + return 0; +} + +int __weak tq_bb_board_mmc_init(struct bd_info *bis) +{ + return 0; +} + +int __weak tq_bb_board_early_init_f(void) +{ + return 0; +} + +int __weak tq_bb_board_init(void) +{ + return 0; +} + +int __weak tq_bb_board_late_init(void) +{ + return 0; +} + +int __weak tq_bb_checkboard(void) +{ + return 0; +} + +void __weak tq_bb_board_quiesce_devices(void) +{ + ; +} + +const char * __weak tq_bb_get_boardname(void) +{ + return "INVALID"; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void __weak tq_bb_board_init_f(ulong dummy) +{ + ; +} + +void __weak tq_bb_spl_board_init(void) +{ + ; +} +#endif /* IS_ENABLED(CONFIG_SPL_BUILD) */ + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int __weak tq_bb_ft_board_setup(void *blob, struct bd_info *bis) +{ + return 0; +} + +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/common/tq_bb.h b/board/tq/common/tq_bb.h new file mode 100644 index 00000000000..5b1b3f62a8c --- /dev/null +++ b/board/tq/common/tq_bb.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2013-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#ifndef __TQ_BB_H +#define __TQ_BB_H + +struct mmc; +struct bd_info; +struct node_info; + +int tq_bb_board_mmc_getwp(struct mmc *mmc); +int tq_bb_board_mmc_getcd(struct mmc *mmc); +int tq_bb_board_mmc_init(struct bd_info *bis); + +int tq_bb_board_early_init_f(void); +int tq_bb_board_init(void); +int tq_bb_board_late_init(void); +int tq_bb_checkboard(void); +void tq_bb_board_quiesce_devices(void); + +const char *tq_bb_get_boardname(void); + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void tq_bb_board_init_f(ulong dummy); +void tq_bb_spl_board_init(void); +#endif + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int tq_bb_ft_board_setup(void *blob, struct bd_info *bis); +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ + +#endif /* __TQ_BB_H */ diff --git a/board/tq/common/tq_sdmmc.c b/board/tq/common/tq_sdmmc.c new file mode 100644 index 00000000000..b7336faa0c7 --- /dev/null +++ b/board/tq/common/tq_sdmmc.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2018-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + */ + +#include <command.h> +#include <env.h> +#include <mmc.h> +#include <stdbool.h> +#include <vsprintf.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <linux/errno.h> + +#include "tq_bb.h" + +static int check_mmc_autodetect(void) +{ + /* NO or unset: 0 / YES: 1 */ + return (env_get_yesno("mmcautodetect") > 0); +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + u32 dev_no; + + dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + env_set_ulong("mmcblkdev", mmc_map_to_kernel_blk(dev_no)); + + snprintf(cmd, ARRAY_SIZE(cmd), "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig index e62228d73d0..21bcb8e0cb3 100644 --- a/board/tq/tqma6/Kconfig +++ b/board/tq/tqma6/Kconfig @@ -7,7 +7,8 @@ config SYS_VENDOR default "tq" config SYS_CONFIG_NAME - default "tqma6" + default "tqma6_mba6" if MBA6 + default "tqma6_wru4" if WRU4 choice prompt "TQMa6 SoC variant" @@ -71,6 +72,8 @@ choice config MBA6 bool "TQMa6 on MBa6 Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SDMMC select USB select CMD_USB select USB_STORAGE @@ -91,6 +94,7 @@ config MBA6 config WRU4 bool "OHB WRU-IV" + select TQ_COMMON_BB help Select the OHB Systems AG WRU-IV baseboard. @@ -106,4 +110,6 @@ config IMX_CONFIG default "board/tq/tqma6/tqma6dl.cfg" if TQMA6DL default "board/tq/tqma6/tqma6s.cfg" if TQMA6S +source "board/tq/common/Kconfig" + endif diff --git a/board/tq/tqma6/MAINTAINERS b/board/tq/tqma6/MAINTAINERS deleted file mode 100644 index 1d3f7d2cf63..00000000000 --- a/board/tq/tqma6/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -TQ-SYSTEMS TQMA6 BOARD -M: Markus Niebel <[email protected]> -L: TQ-Systems OSS Team <[email protected]> -S: Maintained -F: board/tq/tqma6/ -F: include/configs/tqma6.h -F: configs/tqma6*_defconfig diff --git a/board/tq/tqma6/Makefile b/board/tq/tqma6/Makefile index f1b39844ac6..ecebc28315d 100644 --- a/board/tq/tqma6/Makefile +++ b/board/tq/tqma6/Makefile @@ -6,6 +6,7 @@ # obj-y := tqma6.o +obj-y += tqma6_emmc.o obj-$(CONFIG_MBA6) += tqma6_mba6.o obj-$(CONFIG_WRU4) += tqma6_wru4.o diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 75d36240a1e..005f08c4e5f 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -26,7 +26,8 @@ #include <power/pfuze100_pmic.h> #include <power/pmic.h> -#include "tqma6_bb.h" +#include "tqma6_emmc.h" +#include "../common/tq_bb.h" DECLARE_GLOBAL_DATA_PTR; @@ -37,19 +38,21 @@ int dram_init(void) return 0; } -static const uint16_t tqma6_emmc_dsr = 0x0100; - int board_early_init_f(void) { - return tqma6_bb_board_early_init_f(); + return tq_bb_board_early_init_f(); } int board_init(void) { + struct mmc *mmc = find_mmc_device(0); + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - tqma6_bb_board_init(); + tqma6_mmc_detect_card_type(mmc); + + tq_bb_board_init(); return 0; } @@ -96,11 +99,12 @@ int board_late_init(void) { env_set("board_name", tqma6_get_boardname()); - tqma6_bb_board_late_init(); + tq_bb_board_late_init(); printf("Board: %s on a %s\n", tqma6_get_boardname(), - tqma6_bb_get_boardname()); - return 0; + tq_bb_get_boardname()); + + return tq_bb_checkboard(); } /* @@ -110,17 +114,24 @@ int board_late_init(void) #define MODELSTRLEN 32u int ft_board_setup(void *blob, struct bd_info *bd) { + struct mmc *mmc = find_mmc_device(0); char modelstr[MODELSTRLEN]; snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), - tqma6_bb_get_boardname()); + tq_bb_get_boardname()); do_fixup_by_path_string(blob, "/", "model", modelstr); fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); - /* bring in eMMC dsr settings */ - do_fixup_by_path_u32(blob, - "/soc/aips-bus@02100000/usdhc@02198000", - "dsr", tqma6_emmc_dsr, 2); - tqma6_bb_ft_board_setup(blob, bd); + + /* bring in eMMC dsr settings if needed */ + if (mmc && (!mmc_init(mmc))) { + if (tqma6_emmc_need_dsr(mmc) > 0) { + tqma6_ft_fixup_emmc_dsr(blob, + "/soc/bus@2100000/mmc@2198000", + TQMA6_EMMC_DSR); + } + } else { + puts("eMMC: not present?\n"); + } return 0; } diff --git a/board/tq/tqma6/tqma6.env b/board/tq/tqma6/tqma6.env new file mode 100644 index 00000000000..b1d7e5cbbcf --- /dev/null +++ b/board/tq/tqma6/tqma6.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6 environment + */ + +#include <env/tq/tq-imx-shared.env> + +board=tqma6 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6_INITRD_ADDRESS +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth0 +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6_SPI_UBOOT_START +uboot_spi_size=TQMA6_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6_MMC_UBOOT_SECTOR_START TQMA6_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/board/tq/tqma6/tqma6_bb.h b/board/tq/tqma6/tqma6_bb.h deleted file mode 100644 index e17e6ad3f57..00000000000 --- a/board/tq/tqma6/tqma6_bb.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2013-2014 TQ-Systems GmbH <[email protected]>, - * D-82229 Seefeld, Germany. - * Author: Markus Niebel - */ - -#ifndef __TQMA6_BB__ -#define __TQMA6_BB__ - -int tqma6_bb_board_mmc_getwp(struct mmc *mmc); -int tqma6_bb_board_mmc_getcd(struct mmc *mmc); -int tqma6_bb_board_mmc_init(struct bd_info *bis); - -int tqma6_bb_board_early_init_f(void); -int tqma6_bb_board_init(void); -int tqma6_bb_board_late_init(void); -int tqma6_bb_checkboard(void); - -const char *tqma6_bb_get_boardname(void); -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd); -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ - -#endif diff --git a/board/tq/tqma6/tqma6_emmc.c b/board/tq/tqma6/tqma6_emmc.c new file mode 100644 index 00000000000..dd7c4d45c5c --- /dev/null +++ b/board/tq/tqma6/tqma6_emmc.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2017-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include <fdt_support.h> +#include <mmc.h> + +#include "tqma6_emmc.h" + +struct emmc_dsr_lookup { + uint mfgid; + char *pnm; + int dsr_needed; +}; + +static const struct emmc_dsr_lookup dsr_tbl[] = { + /* Micron, eMMC 4.41 */ + { 0xfe, "MMC02G", 1 }, + { 0xfe, "MMC04G", 1 }, + { 0xfe, "MMC08G", 1 }, + /* Micron, eMMC 5.0 4 GB*/ + { 0x13, "Q1J54A", 1 }, + { 0x13, "Q2J54A", 1 }, + /* Micron, eMMC 5.0 8 GB*/ + { 0x13, "Q2J55L", 0 }, + /* Samsung, eMMC 5.0 */ + { 0x15, "8GSD3R", 0 }, + { 0x15, "AGSD3R", 0 }, + { 0x15, "BGSD3R", 0 }, + { 0x15, "CGSD3R", 0 }, + /* SanDisk, iNAND 7250 5.1 */ + { 0x45, "DG4008", 0 }, + { 0x45, "DG4016", 0 }, + { 0x45, "DG4032", 0 }, + { 0x45, "DG4064", 0 }, + /* Kingston */ + { 0x100, "?????", 0 }, +}; + +int tqma6_emmc_need_dsr(const struct mmc *mmc) +{ + uint mfgid = mmc->cid[0] >> 24; + char name[7]; + int ret = -1; + size_t i; + + if (IS_SD(mmc)) + return 0; + + sprintf(name, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24), + (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, + mmc->cid[1] & 0xff, (mmc->cid[2] >> 24)); + + for (i = 0; i < ARRAY_SIZE(dsr_tbl) && (ret < 0); ++i) { + if (dsr_tbl[i].mfgid == mfgid && + (!strncmp(name, dsr_tbl[i].pnm, 6))) { + ret = dsr_tbl[i].dsr_needed; + debug("MFG: %x PNM: %s\n", mfgid, name); + } + } + + if (ret < 0) { + printf("eMMC unknown: MFG: %x PNM: %s\n", mfgid, name); + /* request DSR, even if not known if supported to be safe */ + ret = 1; + } + + return ret; +} + +void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value) +{ + do_fixup_by_path_u32(blob, path, "dsr", value, 1); +} + +void tqma6_mmc_detect_card_type(struct mmc *mmc) +{ + struct mmc *emmc = find_mmc_device(0); + + if (emmc != mmc) + return; + + if (tqma6_emmc_need_dsr(mmc) > 0) + mmc_set_dsr(mmc, TQMA6_EMMC_DSR); +} diff --git a/board/tq/tqma6/tqma6_emmc.h b/board/tq/tqma6/tqma6_emmc.h new file mode 100644 index 00000000000..5ab6c3ac11d --- /dev/null +++ b/board/tq/tqma6/tqma6_emmc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2017-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#ifndef __TQMA6_EMMC_H__ +#define __TQMA6_EMMC_H__ + +#define TQMA6_EMMC_DSR 0x0100 + +struct mmc; + +int tqma6_emmc_need_dsr(const struct mmc *mmc); +void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value); +void tqma6_mmc_detect_card_type(struct mmc *mmc); + +#endif /* __TQMA6_EMMC_H__ */ diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 46989102fec..32aeb1b07c8 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -31,7 +31,7 @@ #include <mmc.h> #include <netdev.h> -#include "tqma6_bb.h" +#include "../common/tq_bb.h" #if defined(CONFIG_TQMA6Q) @@ -126,34 +126,20 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int tqma6_bb_board_early_init_f(void) -{ - return 0; -} - -int tqma6_bb_board_init(void) +int tq_bb_board_init(void) { mba6_setup_iomuxc_enet(); return 0; } -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) +const char *tq_bb_get_boardname(void) { return "MBa6x"; } -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) +int tq_bb_board_late_init(void) { - /* TBD */ + board_late_mmc_env_init(); + return 0; } -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma6/tqma6_wru4.c b/board/tq/tqma6/tqma6_wru4.c index 7acefc7b064..a7dc8fca109 100644 --- a/board/tq/tqma6/tqma6_wru4.c +++ b/board/tq/tqma6/tqma6_wru4.c @@ -33,7 +33,7 @@ #include <mmc.h> #include <netdev.h> -#include "tqma6_bb.h" +#include "../common/tq_bb.h" /* UART */ #define UART4_PAD_CTRL ( \ @@ -95,7 +95,7 @@ static struct fsl_esdhc_cfg usdhc2_cfg = { .max_bus_width = 4, }; -int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +int tq_bb_board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; @@ -106,7 +106,7 @@ int tqma6_bb_board_mmc_getcd(struct mmc *mmc) return ret; } -int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +int tq_bb_board_mmc_getwp(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; @@ -117,7 +117,7 @@ int tqma6_bb_board_mmc_getwp(struct mmc *mmc) return ret; } -int tqma6_bb_board_mmc_init(struct bd_info *bis) +int tq_bb_board_mmc_init(struct bd_info *bis) { int ret; @@ -256,14 +256,14 @@ static void gpio_init(void) gpio_direction_output(GPIO_UART3_PWRON, 0); } -int tqma6_bb_board_early_init_f(void) +int tq_bb_board_early_init_f(void) { setup_iomuxc_uart4(); return 0; } -int tqma6_bb_board_init(void) +int tq_bb_board_init(void) { setup_iomuxc_enet(); @@ -279,12 +279,7 @@ int tqma6_bb_board_init(void) return 0; } -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) +const char *tq_bb_get_boardname(void) { return "WRU-IV"; } @@ -331,13 +326,3 @@ int board_ehci_power(int port, int on) return 0; } - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) -{ - /* TBD */ -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c index 9eb0735f55d..52400672799 100644 --- a/board/xilinx/zynq/bootimg.c +++ b/board/xilinx/zynq/bootimg.c @@ -5,15 +5,12 @@ #include <log.h> #include <part.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <u-boot/md5.h> #include <zynq_bootimg.h> -DECLARE_GLOBAL_DATA_PTR; - #define ZYNQ_IMAGE_PHDR_OFFSET 0x09C #define ZYNQ_IMAGE_FSBL_LEN_OFFSET 0x040 #define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT 0x0F |