Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

This is a DRAM controller driver for the R-Car X5H and its enablement.
This makes the U-Boot on RSIP usable beyond U-Boot shell running on
Cortex-M33, as the U-Boot on RSIP can now load not only SCP firmware
into the SCP core STCM, but also TFA BL31, OPTEE-OS and U-Boot into DRAM
and start them on the Cortex-A720AE core. This is self-contained and
affects only the R-Car X5H and a bit of R-Car V4H, besides it went
through rounds of testing until now, therefore it is safe to include it
this late in the release cycle. I know this will make rc5 massive, sorry
about that.

2 files changed, 50 insertions, 1 deletions

diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c
index e07db9817f2..f06df824019 100644
--- a/board/renesas/common/gen5-cm33.c
+++ b/board/renesas/common/gen5-cm33.c
@@ -905,6 +905,24 @@ static void mfis_unprotect(void)
 }
 
 /**
+ * rsip_write_reg() - Write RSIP control register
+ * @reg: Register to write
+ * @val: Value to set in the register
+ */
+static void rsip_write_reg(const u32 reg, const int val)
+{
+	for (;;) {
+		writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD);
+		writel(val, reg);
+		writel(~val, reg);
+		writel(val, reg);
+
+		if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR)
+			break;
+	}
+}
+
+/**
  * rsip_irq_setup() - Configure RSIP interrupts
  */
 static void rsip_irq_setup(void)
@@ -1353,6 +1371,26 @@ int mach_cpu_init(void)
 	return 0;
 }
 
+int board_early_init_r(void)
+{
+	u32 remaptmp = readl(RSIP_CTL_ESICREMAP0);
+	struct udevice *dev;
+	int ret;
+
+	/* Remap DDR PHY during DRAM init. */
+	rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000);
+
+	/* Start DBSC5 */
+	ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev);
+	if (ret)
+		printf("DBSC5 init failed: %d\n", ret);
+
+	/* Restore remapping. */
+	rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp);
+
+	return 0;
+}
+
 /**
  * board_debug_uart_init() - Initialize all HSCIF
  */
@@ -1407,3 +1445,14 @@ void __weak reset_cpu(void)
 	writel(RST_KCPROT_DIS, RST_RESKCPROT0);
 	writel(0x1, RST_SWSRES1A);
 }
+
+/**
+ * lmb_arch_add_memory() - Add memory to LMB
+ *
+ * Add the window to a subset of 32bit DRAM are into LMB,
+ * to make it possible to TFTP into it.
+ */
+void lmb_arch_add_memory(void)
+{
+	lmb_add(0x60000000, 0x40000000);
+}
diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c
index f5b1a5614b1..a229542ba7e 100644
--- a/board/renesas/sparrowhawk/sparrowhawk.c
+++ b/board/renesas/sparrowhawk/sparrowhawk.c
@@ -5,7 +5,7 @@
 
 #include <asm/io.h>
 #include <compiler.h>
-#include <dbsc5.h>
+#include <r8a779g0-dbsc5.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <spl.h>