diff options
| author | Michal Simek <[email protected]> | 2026-06-23 14:53:32 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2026-07-08 08:55:51 +0200 |
| commit | ae8f2474fe6aad8dc3cbc0f940bf8643611bc7b7 (patch) | |
| tree | 79997a6e91422423dab7586c68e36a479dbc358b /board | |
| parent | 8a2586c3ef8cba7b5ef7a65229f322831f268b7c (diff) | |
arm64: versal2: Move board_early_init_r clock setup to mach code
board_early_init_r() programmed the IOU switch clock and the system
timestamp counter directly with readl()/writel() in board code. This is
SoC register setup rather than board policy, and the same block is
duplicated across the Xilinx SoCs.
Move it into versal2_timer_setup() in arch/arm/mach-versal2 so the board
hook only keeps the EL3 guard and calls the helper.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/08e835a183c39de6f666375ac390eee6a8f3f12e.1782219202.git.michal.simek@amd.com
Diffstat (limited to 'board')
| -rw-r--r-- | board/amd/versal2/board.c | 38 |
1 files changed, 1 insertions, 37 deletions
diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index c4e88440d64..7f2fb4c1ec6 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -132,46 +132,10 @@ bool soc_detection(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal2_timer_setup(); return 0; } |